JP2022552852A - Small loop delay clock and data recovery block for high speed next generation C-PHY - Google Patents

Abstract

A method, apparatus, and system for communicating over a multi-wire, polyphase interface is disclosed. The clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated in response to a transition in a difference signal representing a difference in the signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit, the logic circuit configured to provide a clock signal as an output thereof, wherein a pulse in the combination signal causes the clock signal to be driven to a first state. . The logic circuit receives a reset signal derived from the clock signal by delaying transitions to the first state and passing transitions from the first state without additional delay. The clock signal is driven from the first state after passing the transition of the clock signal to the first state. [Selection diagram] Figure 16

Description

priority claim

Cross-reference to related applications
[0001] This application is hereby incorporated by reference in its entirety as if fully set forth below and for all applicable purposes, on August 2020, 2020. Nonprovisional Patent Application No. 17/001,801 filed in the U.S. Patent and Trademark Office on Oct. 25, 2019; claim the priority and benefit of

[0002] This disclosure relates generally to high speed data communication interfaces, and more particularly to clock generation in receivers coupled to multi-wire, multi-phase data communication links.

[0003] Manufacturers of mobile devices, such as cellular phones, may obtain mobile device components from a variety of sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, an imaging device or camera may be obtained from a second manufacturer, and a display may be obtained from a third manufacturer. Application processors, imaging devices, display controllers, or other types of devices may be interconnected using standards-based or proprietary physical interfaces. In one example, the imaging device may be connected using the Camera Serial Interface (CSI) defined by the Mobile Industry Processor Interface (MIPI) Alliance. In another example, the display may include an interface that conforms to the Display Serial Interface (DSI) standard specified by the Mobile Industry Processor Interface (MIPI) Alliance.

[0004] The C-PHY interface is a multiphase three-wire interface defined by the MIPI Alliance that uses triplets of conductors to transmit information between devices. Each wire in a triplet can be in one of three signaling states during symbol transmission. Clock information is encoded in the sequence of transmitted symbols, and the receiver generates the clock signal from the transitions between successive symbols. The ability of clock and data recovery (CDR) circuits to recover clock information can be limited by the maximum time variations associated with the transitions of signals transmitted over different wires of a communication link. A CDR circuit in a C-PHY receiver may employ a feedback loop to control circuitry that generates pulses in the receive clock signal. A feedback loop ensures that the pulse generation circuit does not generate additional pulses triggered by transients that may occur before the conductors in the triad exhibit stable signaling conditions before giving the sampling edge. can be used to The maximum symbol transmission rate may be limited by feedback loops, and there is a continuing need for optimized clock generation circuits that can function reliably at higher signaling frequencies.

[0005] Embodiments disclosed herein provide systems, methods and apparatus that enable improved communication over multi-wire and/or polyphase communication links. A communication link may be deployed in a device such as a mobile terminal having multiple integrated circuit (IC) devices.

[0006] In various aspects of the disclosure, a clock recovery apparatus includes a plurality of pulse generation circuits, a first logic circuit, a second logic circuit, and an asymmetric delay circuit. Each pulse generation circuit is configured to generate a transition pulse in response to a transition in a difference signal representing a difference in signaling states of pairs of wires in the three-wire bus. A first logic circuit is configured to provide a combination signal including pulses corresponding to the transition pulses received from the plurality of pulse generator circuits. A second logic circuit is configured to respond to pulses in the combination signal and output a clock signal used to decode information from transitions in the signaling states of the three-wire bus. A pulse in the combination signal causes the clock signal to be driven to the first state. The asymmetric delay circuit is configured to generate a reset signal from the clock signal. The reset signal may be generated by delaying the transition to the first state and passing the transition out of the first state without added delay, and the clock signal may be generated when the reset signal transitions to the first state. can be driven from the first state.

[0007] In some aspects, each of the plurality of pulse generation circuits includes an exclusive OR gate configured to receive as inputs an associated differential signal and a delayed version of the associated differential signal. The first logic circuit may include a logic gate configured to provide a combined signal by combining output signals received from exclusive OR gates of each pulse generation circuit. Each of the plurality of pulse generator circuits may be configured to generate a pulse having a duration configured based on the minimum clock pulse duration defined for the second logic circuit. The duration of the pulses generated by the delay circuits in each of the plurality of pulse generation circuits may be configurable. The duration of the delay applied by the asymmetric delay circuit to the transition to the first state may be configurable.

[0008] In one aspect, an asymmetric delay circuit is a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state. A rising edge delay circuit may be configured to pass a transition from a high logic state to a low logic state without added delay. In one aspect, a wire state decoder is configured to decode symbols from transitions in signaling states of a three-wire bus based on timing information provided in a clock signal.

[0009] In various aspects of the present disclosure, a clock recovery method includes combining pulses corresponding to transition pulses generated in response to transitions in a difference signal representing differences in signaling states of pairs of wires in a three-wire bus. Including generating a signal. The clock recovery method further includes providing the combinatorial signal to a logic circuit, the logic circuit configured to provide the clock signal as an output thereof, wherein pulses in the combinatorial signal cause the clock signal to first cause it to be driven to the state of The clock recovery method further includes providing a reset signal to the logic circuit, wherein the reset signal delays the transition to the first state and transitions out of the first state without added delay. It is derived from the clock signal by passing. The clock signal is driven from the first state after passing the transition of the clock signal to the first state.

[0010] In various aspects of the present disclosure, a processor-readable storage medium has one or more instructions, the one or more instructions, when executed by at least one processor of processing circuitry in the receiver, , causing the at least one processor to generate a combined signal including pulses corresponding to transition pulses generated in response to transitions in the differential signal representing the difference in signaling states of pairs of wires in the three-wire bus. The instructions cause at least one processor to provide a combinatorial signal to a logic circuit, the logic circuit being configured to provide a clock signal as an output thereof, wherein the pulses in the combinatorial signal correspond to the clock signal. Cause the signal to be driven to the first state. The instructions cause at least one processor to provide a reset signal to a logic circuit, wherein the reset signal delays a transition to the first state and the first state without added delay. is derived from the clock signal by passing transitions from The clock signal is driven from the first state after passing the transition of the clock signal to the first state.

[0011] In various aspects of the present disclosure, the clock recovery apparatus includes combinations including pulses corresponding to transition pulses generated in response to transitions in a difference signal representing differences in signaling states of pairs of wires in a three-wire bus. including means for generating a signal. The clock recovery apparatus further includes means for providing a combinatorial signal to a logic circuit, the logic circuit being configured to provide the clock signal as an output thereof, wherein pulses in the combinatorial signal correspond to when the clock signal is Cause it to be driven to the first state. The clock recovery apparatus further includes means for providing a reset signal to the logic circuit, wherein the reset signal delays the transition to and from the first state without added delay. is derived from the clock signal by passing The clock signal is driven from the first state after passing the transition of the clock signal to the first state.

[0012] Fig. 2 illustrates an apparatus employing data links between IC devices selectively operated according to one of a plurality of available standards or protocols, which may include the C-PHY protocol; [0013] FIG. 1 illustrates a system architecture for an apparatus employing data links between IC devices that selectively operate according to one of multiple available standards. [0014] Fig. 2 illustrates a C-PHY three-phase transmitter; [0015] Fig. 3 illustrates signaling in a C-PHY three-phase encoded interface; [0016] Fig. 2 illustrates a C-PHY three-phase receiver; [0017] Fig. 3 is a state diagram showing potential state transitions in a C-PHY three-phase encoded interface; [0018] FIG. 4 is an illustration of an example of the effect of signal rise time on transition detection in a C-PHY decoder. [0019] Fig. 3 illustrates transition detection in a C-PHY decoder; [0020] FIG. 4 illustrates an example of signal transitions that occur between pairs of consecutive symbols transmitted over a C-PHY interface. [0021] Fig. 3 illustrates a transition region and an eye region in an eye pattern; [0022] FIG. 4 illustrates an example eye pattern generated for a C-PHY three-phase interface; [0023] Fig. 2 shows an example of a CDR circuit for a C-PHY three-phase interface; [0024] FIG. 13 illustrates timing associated with the CDR circuit of FIG. [0025] FIG. 4 illustrates timing associated with a CDR circuit having a loop time less than the skew between signals transmitted on the C-PHY three-phase signal. [0026] FIG. 4 illustrates timing associated with a CDR circuit having a loop time longer than the symbol interval of a C-PHY three-phase signal. [0027] FIG. 3 illustrates a CDR circuit provided in accordance with some aspects of the disclosure. [0028] FIG. 17 illustrates timing associated with the CDR circuit shown in FIG. [0029] FIG. 4 illustrates an example rising edge delay circuit that may be used in accordance with some aspects disclosed herein. [0030] FIG. 2 is a block diagram illustrating an example of an apparatus employing processing circuitry that may be adapted in accordance with certain aspects disclosed herein. [0031] A flowchart of a first method of calibration, according to certain aspects disclosed herein. [0032] FIG. 2 illustrates a first example hardware implementation for an apparatus employing processing circuitry adapted in accordance with certain aspects disclosed herein.

[0033] The detailed description below with reference to the accompanying drawings is intended to describe various configurations and not to represent the only configurations in which the concepts described herein may be implemented. . The detailed description includes specific details to provide a thorough understanding of various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0034] As used in this application, terms such as "component," "module," and "system" may include, but are not limited to, hardware, firmware, a combination of hardware and software, software, or software in execution. shall include computer-related entities such as For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program and/or computer. By way of example, both an application running on a computing device and that computing device can be a component. One or more components can reside within a process and/or thread of execution, one component being localized on one computer and/or distributed between two or more computers. obtain. In addition, these components can execute from various computer readable media having various data structures stored thereon. These components interact via signals with one component in a local system, another component in a distributed system, and/or with other systems over a network such as the Internet. , etc., may communicate via local and/or remote processes, such as by following signals having one or more data packets.

[0035] Moreover, the term "or" shall mean an inclusive "or" rather than an exclusive "or." That is, unless specified otherwise, or clear from context, the phrase "X employs A or B" shall mean any of the natural inclusive permutations. That is, the phrase "X adopts A or B" is satisfied if X adopts A, X adopts B, or X adopts both A and B. . Furthermore, as used in this application and the appended claims, the articles "a" and "an" generally refer to the singular form unless otherwise specified or clear from the context. It should be construed to mean "one or more."
Overview
[0036] Some aspects of the present invention may be deployed to connect electronic devices that are sub-components of mobile equipment, such as telephones, mobile computing devices, appliances, automotive electronics, avionics systems, etc. by the MIPI Alliance. It may be applicable to the specified C-PHY interface. Examples of mobile devices include mobile computing devices, cellular phones, smart phones, session initiation protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, global positioning systems. (GPS) devices, smart home devices, intelligent lighting, multimedia devices, video devices, digital audio players (e.g. MP3 players), cameras, game consoles, entertainment devices, vehicle components, avionics systems, wearable computing devices (e.g. , smart watches, health or fitness trackers, eyewear, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multicopters, or any other similarly functioning device.

[0037] A C-PHY interface is a high-speed serial interface that can provide high throughput over bandwidth-limited channels. A C-PHY interface can be deployed to connect the application processor to peripherals including displays and cameras. The C-PHY interface encodes data into symbols that are transmitted over sets of three wires, sometimes referred to as triplets or triplets of wires. For each symbol transmission interval, a three-phase signal is transmitted at different phases on the triplets of wires, where the phase of the three-phase signal on each wire is defined by the symbols transmitted in the symbol transmission interval. Each triplet gives a lane on the communication link. A symbol transmission interval may be defined as the time interval during which a single symbol controls a signaling state of a triplet. At each symbol transmission interval, one wire of the triplet is undriven and the remaining two wires are two differentially driven wires, one of which exhibits a first voltage level and the other. are differentially driven such that the differentially driven wires of are presented to a second voltage level different from the first voltage level. the non-driven wire is floated and driven such that it exhibits a third voltage level at or near an intermediate level voltage between the first voltage level and the second voltage level; and/or terminated. In one example, the drive voltage levels can be +V and -V and the undrive voltage is 0V. In another example, the drive voltage levels can be +V and 0V, and the undrive voltage is +1/2V. A different symbol is transmitted in each successively transmitted pair of symbols, and different pairs of wires may be driven differentially in different symbol intervals.

[0038] More recent implementations and proposed specifications for C-PHY, including the C-PHY 1.2 and C-PHY 2.0 specifications, use the conventional CDR to recover the clock signal in the receiver. Define the frequency of the symbol transmit clock signal that can exceed the capabilities of the circuit. The ability of a clock recovery circuit to recover clock information may be limited by the maximum time variations associated with transitions of signals transmitted over different wires of a communication link. Clock recovery circuits in C-PHY receivers typically employ feedback loops that control the generation of pulses in the received clock signal. A feedback loop ensures that the pulse generation circuit does not generate additional pulses triggered by transients that may occur before the conductors in the triad exhibit stable signaling conditions before giving the sampling edge. can be used to The maximum symbol transmission rate may be limited by feedback loops, and there is a continuing need for optimized clock generation circuits that can function reliably at the higher signaling frequencies defined by later generations of the C-PHY specification. .

[0039] Certain aspects disclosed herein provide a clock recovery circuit in a C-PHY receiver circuit, where the loop time of the C-PHY receiver circuit is the next generation clock recovery circuit. It is minimized so that it can operate at the C-PHY clock rate. In one example, the clock recovery circuit is configured to generate a combinatorial signal including one or more transition pulses, to provide the combinatorial signal to a logic circuit, and the logic circuit to provide the clock signal as its output. and providing a reset signal to the logic circuit, the reset signal being derived from the clock signal by delaying the transition to the first state and passing the transition out of the first state without added delay. be done. Each transition pulse is generated in response to a transition in a differential signal representing the difference in signaling states of a pair of wires in the three-wire bus. A pulse in the combination signal causes the clock signal to be driven to the first state, and the clock signal is driven from the first state after passing the transition of the clock signal to the first state.

[0040] The clock recovery circuit may generate transition pulses for the first difference signal by performing an exclusive OR gate function on the first difference signal and a delayed version of the first difference signal. . The clock recovery circuit may configure at least one pulse generation circuit to provide corresponding transition pulses having durations based on the minimum clock pulse duration defined for the logic circuit. The clock recovery circuit may calibrate the at least one pulse generator circuit based on operating conditions of the three-wire bus. The clock recovery circuit may configure the asymmetric delay circuit to select the duration of the delay applied to the transition to the first state. The asymmetric delay circuit is configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without added delay. , may include a rising edge delay circuit. A clock recovery circuit may provide a clock signal to a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal.
Examples of equipment adopting C-PHY interface
[0041] FIG. 1 illustrates an example apparatus 100 that may be adapted in accordance with certain aspects disclosed herein. Apparatus 100 may employ a C-PHY three-phase protocol to implement one or more communication links. Apparatus 100 may include processing circuitry 102 having a plurality of circuits or devices 104 , 106 and/or 108 . In some examples, the circuits or devices 104, 106 and/or 108 may be implemented in one or more ASICs or in a system-on-chip (SoC), where the SoC is a processor, computer or other electronic It may include an integrated circuit that implements all or substantially all of the components of the system. In one example, the apparatus 100 can be a communication device, the processing circuitry 102 includes a first circuit or device 104, one or more peripheral devices 106, and the apparatus can communicate with wireless access networks, core access networks, the Internet and/or It may include a processor 112 provided at the transceiver 108 that enables it to communicate with another network through an antenna 124 .

[0042] The first circuit or device 104 may include one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116 and/or other logic circuits or functions. . The processing circuitry 102 has an application programming interface (API) that enables one or more processors 112 to execute software modules residing in on-board memory 114 or processor readable storage 122 provided on the processing circuitry 102 . It can be controlled by an operating system that can provide layers. Software modules may include instructions and data stored in on-board memory 114 or other processor-readable storage 122 . A first circuit or device 104 may access its on-board memory 114 , processor readable storage 122 , and/or storage external to processing circuitry 102 . On-board memory 114 and/or processor readable storage 122 may be read only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM®), flash cards, or other processing system and computing memory. It can include any memory device that can be used in the platform. Processing circuitry 102 includes or implements a local database or other parameter storage capable of maintaining operating parameters and other information used to configure and operate device 100 and/or processing circuitry 102 , or have access to it. Local databases may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, soft or hard disks, and the like. The processing circuitry 102 may also be operatively coupled to external devices such as, among other components, an antenna 124 , a display 126 , switches or buttons 128 , 130 and/or operator controls such as an integrated or external keypad 132 . A user interface module may be configured to operate with display 126, external keypad 132, etc. through a dedicated communication link or through one or more serial data interconnects.

[0043] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that allow several circuits or devices 104, 106, and/or 108 to communicate. In one example, the first circuit or device 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, bus interface circuit 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100 .

[0044] FIG. 2 illustrates some aspects of an apparatus 200 including multiple IC devices 202 and 230 capable of exchanging data and control information over a communication link 220. As shown in FIG. Communication link 220 may be used to connect a pair of IC devices 202 and 230 located in close proximity to each other or physically located in different portions of apparatus 200 . In one example, communication link 220 may be provided on a chip carrier, substrate, or circuit board carrying IC devices 202 and 230 . In another example, the first IC device 202 may be placed in the keypad section of the flip phone and the second IC device 230 may be placed in the display section of the flip phone. In another example, a portion of communication link 220 may include a cable or optical connection.

[0045] Communication link 220 may include multiple channels 222, 224, and 226. Channels 222, 224, and 226 may include channels 222, 224, and 226; One or more channels 226 may be bi-directional and may operate in half-duplex and/or full-duplex modes. One or more of channels 222 and 224 may be unidirectional. Communication link 220 may be asymmetric and provide higher bandwidth in one direction. In one example described herein, first channel 222 may be referred to as forward channel 222 and second channel 224 may be referred to as reverse channel 224 . Even if both IC devices 202 and 230 are configured to transmit and receive on channel 222, the first IC device 202 can be designated as the host system or transmitter, and the second IC device 230 can be the client system. or may be designated as a receiver. In one example, forward channel 222 may operate at a higher data rate when communicating data from first IC device 202 to second IC device 230 , and reverse channel 224 may communicate data from second IC device 230 . It may operate at a lower data rate when communicating data to the first IC device 202 .

[0046] IC devices 202 and 230 may each include processors 206, 236, controllers or other processing and/or computing circuits or devices. In one example, the first IC device 202 may perform the core functions of the apparatus 200 including establishing and maintaining wireless communication through the wireless transceiver 204 and the antenna 214, and the second IC device 230 is the display controller 232. A camera controller 234 may be used to control the operation of the camera or video input device. Other features supported by one or more of IC devices 202 and 230 may include keyboards, voice recognition components, and other input or output devices. Display controller 232 may include circuitry and software drivers that support displays such as liquid crystal display (LCD) panels, touch screen displays, indicators, and the like. Storage media 208 and 238 are transient and/or non-transitory adapted to maintain instructions and data used by respective processors 206 and 236 and/or other components of IC devices 202 and 230. May include storage devices. Communication between each processor 206 , 236 and its corresponding storage media 208 and 238 and other modules and circuits is via one or more internal buses 212 and 242 and/or channels 222 of communication link 220 . , 224 and/or 226.

[0047] Reverse channel 224 may be operated in the same manner as forward channel 222, and forward channel 222 and reverse channel 224 may be capable of transmitting at equal or different speeds, where , the speed may be expressed as a data transfer rate, a symbol transmission rate and/or a clocking rate. The forward and reverse data rates may be substantially the same or may differ by several orders of magnitude, depending on the application. In some applications, a single bi-directional channel 226 may support communication between first IC device 202 and second IC device 230 . Forward channel 222 and/or reverse channel 224 are configured to operate in a bidirectional mode, for example, when forward channel 222 and reverse channel 224 share the same physical connection and operate in a half-duplex mode. May be configurable. In one example, communication link 220 may be operated to communicate control, command and other information between first IC device 202 and second IC device 230 according to industry standards or other standards.

[0048] Communication link 220 of FIG. 2 may be implemented according to the MIPI Alliance Specification for C-PHY and may provide a wired bus including multiple signal wires (shown as M wires). The M wires may be configured to carry N-phase encoded data in a high speed digital interface, such as the Mobile Display Digital Interface (MDDI). The M wires may facilitate N-phase polarity encoding on one or more of channels 222 , 224 and 226 . Physical layer drivers 210 and 240 may be configured or adapted to generate N-phase polarity encoded data for transmission over communication link 220 . The use of N-phase polarity encoding provides high speed data transfer and may consume half or less of the power of other interfaces because fewer drivers are active in N-phase polarity encoded data links.

[0049] Physical layer drivers 210 and 240 can generally encode multiple bits per transition on communication link 220 when configured for N-phase polarity encoding. In one example, a combination of three-phase encoding and polar encoding is used to support a wide video graphics array (WVGA) 80 frames per second LCD driver IC without a frame buffer and for display refresh. can deliver pixel data at 810 Mbps to .

[0050] FIG. 3 is a diagram 300 illustrating a three-wire, three-phase polarity encoder that may be used to implement some aspects of the communication link 220 shown in FIG. The example of 3-wire, 3-phase encoding is chosen merely to simplify the discussion of some aspects of the present invention. The principles and techniques disclosed for 3-wire, 3-phase encoders may be applied in other configurations of M-wire, N-phase polar encoders.

[0051] The signaling states defined for each of the three wires in the three-wire, three-phase polarity encoding scheme are an undriven state, a positively driven state, and a negatively driven state. driven state). The positive and negative drive states are established by applying a voltage difference between two of signal wires 318a, 318b and/or 318c and/or by connecting signal wires 318a, 318b and/or through termination resistors. or by driving current through two of 318c such that current flows in different directions through the two of signal wires 318a, 318b and/or 318c. A non-driven state may be achieved by placing the output of the driver on signal wire 318a, 318b or 318c into a high impedance mode. Alternatively or additionally, a voltage level that is substantially midway between the positive and negative voltage levels provided on drive signal wires 318a, 318b and/or 318c can be passively or actively " A non-driven state on the signal wire 318a, 318b or 318c may be obtained by reaching the non-driven signal wire 318a, 318b or 318c. Generally, there is no significant current flow through non-drive signal wires 318a, 318b or 318c. The signaling states defined for the 3-wire, 3-phase polarity encoding scheme can be indicated using three voltage or current states (+1, -1, and 0).

[0052] A three-wire, three-phase polarity encoder may employ line drivers 308 to control the signaling states of signal wires 318a, 318b and 318c. Line driver 308 may be implemented as a unit level current mode or voltage mode driver. In some implementations, each line driver 308 may receive a set of signals 316a, 316b and 316c that determine the output states of corresponding signal wires 318a, 318b and 318c. In one example, each set of signals 316a, 316b and 316c, when high, activates pull-up and pull-down circuits that drive signal wires 318a, 318b and 318c, respectively, toward higher or lower voltage levels. , may include two or more signals to activate, including a pull-up signal (PU signal) and a pull-down signal (PD signal). In this example, signal wires 318a, 318b and 318c may be terminated to a mid-level voltage when both the PU and PD signals are low.

[0053] For each symbol transmission interval in an M-wire, N-phase polar encoding scheme, at least one signal wire 318a, 318b or 318c is in a mid-level/undriven (0) voltage or current state and positively driven (+1 voltage or current state) signal wires 318a, 318b or 318c is the number of negative drive (-1 voltage or current state) signal wires 318a, 318b or 318c so that the sum of the currents flowing be equivalent to. For each symbol transmission interval, the signaling state of at least one signal wire 318a, 318b or 318c is changed from the wire state transmitted in the preceding transmission interval.

[0054] In operation, mapper 302 may receive 16-bit data 310 and map it into seven symbols 312. As shown in FIG. In the three-wire example, each of the seven symbols defines the state of signal wires 318a, 318b and 318c for one symbol transmission interval. The seven symbols 312 may be serialized using serializer 304 to provide a timed sequence of symbols 314 for each signal wire 318a, 318b and 318c. The sequence of symbols 314 is generally timed using a transmit clock sometimes referred to as the symbol clock (CLK _SYM ). In one example, the period of the symbol clock defines the duration of the symbol transmission interval. A three-wire, three-phase encoder 306 receives, one symbol at a time, the sequence of seven symbols 314 produced by the mapper and computes the state of each signal wire 318a, 318b and 318c for each symbol transmission interval. Three-wire, three-phase encoder 306 selects the states of signal wires 318a, 318b and 318c based on the current input symbol 314 and the previous states of signal wires 318a, 318b and 318c.

[0055] The use of M-wire, N-phase encoding allows some bits to be encoded in multiple symbols, where the bits per symbol is not an integer. In the example of a three-wire communication link, there are three possible combinations of two wires that can be driven simultaneously and two possible combinations of polarities on the pair of wires driven, giving six possible states. occur. Since each transition originates from the current state, 5 of the 6 states are available at every transition. At least one wire state is required to change at each transition. For five states, log ₂ (5)≈2.32 bits can be encoded per symbol. Thus, 7 symbols carrying 2.32 bits per symbol can encode 16.24 bits, so a mapper can accept a 16-bit word and convert it to 7 symbols. In other words, the 7 symbol combinations that encode the 5 states have 5 ⁷ (78,125) permutations. Therefore, 7 symbols can be used to encode 2 ¹⁶ (65,536) permutations of 16 bits.

[0056] FIG. 4 includes an example timing diagram 400 for signals encoded using a three-phase modulation data encoding scheme based on a circular state diagram 450. FIG. Information may be encoded in a sequence of signaling states, where, for example, a wire or connector is in one of three phase states S ₁ , S ₂ and S ₃ defined by circular state diagram 450 . Each state can be separated from other states by a 120° phase shift. In one example, data may be encoded in the direction of rotation of phase states on a wire or connector. The phase states in the signals may rotate in the clockwise direction 452 and 452' or the counterclockwise direction 454 and 454'. For example, in the clockwise direction 452 and 452', the _phase states are sequences that include _one or _more of the transitions S1 to S2 _, S2 to S3 _, and _S3 to S1. can proceed in In the counterclockwise direction 454 and 454', the phase states are _a sequence including _one or _more of the transitions _S3 to S2 _, S2 to S1 _, and S1 to S3. can proceed in The three signal wires 318a, 318b and 318c carry different versions of the same signal, where the versions can be phase shifted with respect to each other by 120°. Each signaling state can be represented as a different voltage level on the wire or connector and/or the direction of current flow through the wire or connector. During each sequence of signaling states in a three-wire system, each signal wire 318a, 318b and 318c is in a different signaling state than the other wires. When more than three signal wires 318a, 318b and 318c are used in a three-phase encoding system, two or more signal wires 318a, 318b and/or 318c are in the same signaling state in each signaling interval. Obtained, each state is present on at least one signal wire 318a, 318b and/or 318c in every signaling interval.

[0057] Information may be encoded in the direction of rotation at each phase transition 410, and the three-phase signal may change direction for each signaling state. The direction of rotation is such that the non-drive signal wires 318a, 318b and/or 318c change at every signaling condition in a rotating three-phase signal regardless of the direction of rotation, so that any signal wire 318a, 318b and/or 318c It can be determined by considering whether it is in the '0' state before and after the phase transition.

[0058] The encoding scheme may also encode information in the polarity 408 of the two actively driven signal wires 318a, 318b and/or 318c. At any given time in the three-wire implementation, exactly two of the signal wires 318a, 318b, 318c are driven with currents in opposite directions and/or with voltage differences. In one implementation, data may be encoded using a two-bit value 412, where one bit is encoded in the direction of the phase transition 410 and the second bit is encoded in the polarity 408 for the current state. become.

[0059] Timing diagram 400 illustrates data encoding using both phase rotation direction and polarity. Curves 402, 404 and 406 relate to signals carried on three signal wires 318a, 318b and 318c, respectively, for multiple phase states. Initially, the phase transition 410 is in a clockwise direction with the most significant bit set to a binary '1', then the rotation of the phase transition 410 is represented at time 414 by a binary '0' in the most significant bit. so that it switches to the counterclockwise direction. The least significant bit reflects the polarity 408 of the signal in each state.

[0060] According to some aspects disclosed herein, one bit of data may be encoded in rotation or phase change in a three-wire, three-phase encoding system, and an additional bit may be encoded in two can be encoded in one drive wire polarity. Additional information can be encoded at each transition of a three-wire, three-phase encoding system by allowing the transition from the current state to any of the possible states. Assuming 3 rotational phases and 2 polarities for each phase, 6 states are available in a 3-wire, 3-phase encoding system. Thus, with 5 states available from the current state, there can be log ₂ (5)≈2.32 bits encoded per symbol (transition), which means that mapper 302 accepts 16-bit words. , allowing it to be encoded in 7 symbols.

[0061] FIG. 5 is a diagram illustrating some aspects of a three-wire, three-phase decoder 500. As shown in FIG. Differential receivers 502a, 502b, 502c and wire state decoder 504 provide a digital representation 522 of the state of the three transmission lines (eg, signal wires 318a, 318b and 318c shown in FIG. 3) relative to each other, is configured to detect changes in the state of the three transmission lines compared to the transmitted state in the symbol periods of . Seven successive states are assembled by deserializer 506 to obtain a set of seven symbols 516 to be processed by demapper 508 . Demapper 508 produces 16 bits of data 518 that can be buffered in first-in-first-out (FIFO) register 510 to provide output data 520 .

[0062] Wire state decoder 504 may extract a sequence of symbols 514 from the phase-encoded signals received on signal wires 318a, 318b and 318c. Symbols 514 are encoded as a combination of phase rotation and polarity as disclosed herein. The wire state decoder may include a CDR circuit 524 that extracts a clock 526 that may be used to reliably capture wire states from signal wires 318a, 318b and 318c. A transition occurs on at least one of signal wires 318a, 318b and 318c at each symbol boundary, and CDR circuit 524 may be configured to generate clock 526 based on the occurrence of the one or more transitions. . The clock edges may be delayed to allow time for all signal wires 318a, 318b and 318c to be stable, thereby ensuring that the current wire state is captured for decoding purposes.

[0063] Figure 6 is a state diagram 600 showing three possible signaling states 602, 604, 606, 612, 614, 616 of the wire, with the possible transitions from each state indicated. In the example of a 3-wire, 3-phase communication link, 6 states and 30 state transitions are available. The possible signaling states 602, 604, 606, 612, 614 and 616 in state diagram 600 are detailed, including the states shown in circular state diagram 450 of FIG. As shown in the sample state element 628, each signaling state 602, 604, 606, 612, 614 and 616 in the state diagram 600 has signal wires 318a, 318b labeled A, B and C respectively. , 318c. For example, in signaling state 602(+x), wire A=+1, wire B=−1 and wire C=0, which means differential receiver 502a(A−B)=+2, differential receiver 502b( BC)=-1 and differential receiver 502c(C-A)=-1 outputs. Transition decisions made by phase change detection circuitry in the receiver are based on five possible levels generated by the differential receivers 502a, 502b, 502c, including -2, -1, 0, +1 and +2 voltage states. .

[0064] The transitions in state diagram 600 are Flip, Rotate, Polarity symbols with one of the 3-bit binary values in the set {000, 001, 010, 011, 100}. (eg, FRP symbol 626). Rotation bit 622 of FRP symbol 626 indicates the direction of phase rotation associated with the transition to the next state. Polarity bit 624 of FRP symbol 626 is set to a binary one when the transition to the next state involves a change in polarity. When flip bit 620 of FRP symbol 626 is set to a binary one, the rotation and polarity values may be ignored and/or zeroed. A flip represents a state transition involving only a change in polarity. Therefore, the phase of a 3-phase signal is not considered rotating when a flip occurs, and the polarity bit is redundant when a flip occurs. FRP symbols 626 correspond to wire state changes for each transition. The state diagram 600 can be separated into an inner circle 608 containing positive signaling states 602 , 604 , 606 and an outer circle 618 containing negative signaling states 612 , 614 , 616 .
Jitter in 3-phase interfaces
[0065] A three-phase transmitter includes a driver that provides high, low and medium level voltages on the transmission channel. This results in several fluctuating transitions between successive symbol intervals. Low-to-high and high-to-low voltage transitions are sometimes called full-swing transitions, and low-to-medium and high-to-medium voltage transitions are called half-swing transitions. Sometimes. Different types of transitions may have different rise or fall times, resulting in different zero crossings at the receiver. These differences can result in "encoding jitter", which can affect link signal integrity performance.

[0066] Figure 7 is a timing diagram 700 illustrating some aspects of transition variability in the output of a C-PHY three-phase transmitter. Variability in signal transition times can result from the presence of different voltage and/or current levels used in three-phase signaling. Timing diagram 700 illustrates transition times in signals received from a single signal wire 310a, 310b or 310c. A first symbol Sym _n 702 is sent in a first symbol interval, which ends at time 722, after which a second symbol Sym _n+1 704 is sent in a second symbol interval. be. The second symbol interval may end at time 724, after which a third symbol Sym _n+2 706 is transmitted in the third symbol interval, the third symbol interval ends at time 726, after which A fourth symbol Sym _n+3 708 is sent in the fourth symbol interval. The transition from the state determined by the first symbol 702 to the state corresponding to the second symbol 704 takes the voltage in signal wire 310a, 310b or 310c to reach threshold voltages 718 and/or 720. It may be detectable after a delay 712 due to time. The threshold voltage can be used to determine the state of signal wire 310a, 310b or 310c. The transition from the state determined by the second symbol 704 to the state for the third symbol 706 is such that the voltage in signal wire 310a, 310b or 310c is one of threshold voltages 718 and/or 720. may be detectable after a delay 714 due to the time it takes to reach . The transition from the state determined by the third symbol 706 to the state for the fourth symbol 708 takes the voltage in signal wire 310a, 310b or 310c to reach threshold voltages 718 and/or 720. It may be detectable after a delay 716 due to time. Delays 712, 714 and 716 may have different durations, which may be due in part to variations in device manufacturing processes and operating conditions, and variations between different voltage or current levels associated with the three states. transitions, and/or different transition magnitudes. These differences can cause jitter and other problems in C-PHY three-phase receivers.

[0067] FIG. 8 illustrates some aspects of CDR circuitry that may be provided in a receiver at C-PHY interface 800. FIG. Differential receivers 802a, 802b and 802c are configured to generate a set of differential signals 810a, 810b, 810c by comparing signaling states of each different pair of signal wires 310a, 310b and 310c in the triad. be. In the example shown, a first differential receiver 802a provides an AB differential signal 810a representing the difference in signaling states of A signal wire 310a and B signal wire 310b, and a second differential receiver 802b provides a B signal A third differential receiver 802c provides a BC differential signal 810b representing the difference in signaling states of wire 310b and C signal wire 310c, and a CA differential signal representing the difference in signaling states of C signal wire 310c and A signal wire 310a. 810c. Accordingly, transition detection circuit 804 may be configured to detect the occurrence of a phase change as the output of at least one of differential receivers 802a, 802b and 802c changes at the end of each symbol interval.

[0068] Transitions between some consecutively transmitted pairs of symbols may be detectable by a single differential receiver 802a, 802b or 802c, other transitions may be detected by differential receivers 802a, It can be detected by two or more of 802b and 802c. In one example, the state, or relative state, of the two wires may be unchanged after a transition, and the output of the corresponding differential receiver 802a, 802b or 802c may also be unchanged after a phase transition. Accordingly, clock generation circuit 806 may include transition detection circuit 804 and/or other logic to monitor the outputs of all differential receivers 802a, 802b and 802c to determine when phase transitions have occurred. may include or cooperate with Clock generation circuitry may generate receive clock signal 808 based on the detected phase transitions.

[0069] A change in the signaling state of the three wires in the triplet may be detected at different times, which may cause the difference signals 810a, 810b, 810c to exhibit a steady state at different times. The state of the differential signal 810a, 810b, 810c may switch before stability is reached after the signaling state of each signal wire 310a, 310b and/or 310c transitions to its defined state for a symbol transmission interval. . The result of such variability is shown in timing diagram 820 of FIG.

[0070] The timing of signaling state change detection may vary according to the type of signaling state change that has occurred. Markers 822 , 824 and 826 represent the occurrence of transitions in differential signals 810 a , 810 b , 810 c provided to transition detection circuit 804 . Markers 822, 824 and 826 are only assigned different heights in timing diagram 820 for clarity of illustration, and the relative heights of markers 822, 824 and 826 depend on clock generation or data decoding. It does not imply any particular relationship to the voltage or current levels, polarities or weighting values used for . Timing diagram 820 shows the effect of the timing of transitions associated with transmitted symbols on the phase and polarity on the three signal wires 310a, 310b and 310c. In timing diagram 820, transitions between several symbols create variable acquisition windows 830a, 830b, 830c, 830d, 830e, 830f and/or 830g (collectively symbol acquisition windows 830) during which symbols can be reliably acquired. can occur. The number of state changes detected and their relative timing can cause jitter on clock signal 808 .

[0071] The throughput of a C-PHY communication link can be affected by the duration and variability in signal transition times. For example, variability in the detection circuit can be caused by manufacturing process tolerances, variations and instabilities of voltage and current sources and operating temperature, and by electrical properties of signal wires 310a, 310b and 310c. Variability in the detection circuit can limit the channel bandwidth.

[0072] FIG. 9 includes timing diagrams 900 and 920 that represent some examples of transitions from a first signaling state to a second signaling state between several consecutive symbols. The signaling state transitions shown in timing diagrams 900 and 920 are chosen for illustrative purposes, other transitions and combinations of transitions may occur in the MIPI Alliance C-PHY interface. Timing diagrams 900 and 920 illustrate a three-wire, three-phase communication link in which multiple receiver output transitions can occur at each symbol interval boundary due to rise and fall time differences between signal levels on the three wires. Regarding an example of Referring also to FIG. 8, a first timing diagram 900 shows the signaling states of the triad of signal wires 310a, 310b and 310c (A, B and C) before and after the transition, and a second timing diagram 920. show the outputs of differential receivers 802a, 802b and 802c that provide differential signals 810a, 810b, 810c representing the difference between signal wires 310a, 310b and 310c. In many cases, a set of differential receivers 802a, 802b and 802c can be configured to capture transitions by comparing different combinations for the two signal wires 310a, 310b and 310c. In one example, these differential receivers 802a, 802b and 802c may be configured to generate an output by determining the difference (eg, by subtraction) of their respective input voltages.

[0073] In each of the examples shown in timing diagrams 900 and 920, the initial symbol representing the -z state 616 (see Figure 6) transitions to a different symbol. As shown in timing diagrams 902, 904 and 906, signal A is initially in the +1 state, signal B is in the 0 state and signal C is in the -1 state. Thus, as shown in timing diagrams 922, 932, 938 for differential receiver outputs, differential receivers 802a, 802b first measure +1 difference 924 and differential receiver 802c measures -2 difference. Measure 926.

[0074] In a first example, corresponding to timing diagrams 902, 922, a transition occurs from the symbol representing the -z state 616 to the symbol representing the -x signaling state 612 (see FIG. 6), where signal A transitions to the −1 state, signal B transitions to the +1 state, signal C transitions to the 0 state, differential receiver 802a transitions from +1 differential 924 to −2 differential 930, and differential receiver 802b transitions to Staying at +1 deltas 924 , 928 , differential receiver 802 c transitions from −2 deltas 926 to +1 deltas 928 .

[0075] In a second example, corresponding to timing diagrams 904, 932, a transition occurs from the symbol representing the -z state 616 to the symbol representing the +z signaling state 606, where signal A transitions to the -1 state. Then signal B remains in the 0 state, signal C transitions to the +1 state, the two differential receivers 802a and 802b transition from +1 differential 924 to -1 differential 936, and differential receiver 802c transitions to -2 differential. Transition from 926 to +2 difference 934 .

[0076] In a third example, corresponding to timing diagrams 906, 938, a transition occurs from the symbol representing the -z state 616 to the symbol representing the +x signaling state 602, where signal A remains in the +1 state and Signal B transitions to the −1 state, signal C transitions to the 0 state, differential receiver 802a transitions from +1 delta 924 to +2 delta 940, and differential receiver 802b transitions from +1 delta 924 to −1 delta 942. and the differential receiver 802c transitions from the -2 delta 926 to the -1 delta 942.

[0077] These examples show transitions in difference values over 0, 1, 2, 3, 4 and 5 levels. Pre-emphasis techniques used for generic differential or single-ended series transmitters have been developed for two-level transitions, and when used on MIPI Alliance C-PHY three-phase signals, some can have adverse effects. In particular, pre-emphasis circuits that overdrive signals during transitions can cause overshoot during transitions across one or two levels, causing false triggering in edge sensitive circuits.

[0078] FIG. 10 shows a binary eye pattern 1000 generated as a superposition of multiple symbol intervals, including a single symbol interval 1002. FIG. Signal transition region 1004 represents a time period of uncertainty at the boundary between two symbols where variable signal rise times prevent reliable decoding. The state information can be reliably determined in the region defined by the eye mask 1006 within the "eye opening," which represents the time period during which the symbols are stable and can be reliably received and decoded. . The eye mask 1006 masks off areas where zero crossings do not occur, and the eye mask is used by the decoder to prevent multiple clocking due to the effects of subsequent zero crossings at symbol interval boundaries following the first signal zero crossing. be done.

[0079] The concept of periodic sampling and display of a signal has been used during the design, adaptation and construction of systems that employ clock data recovery circuits that regenerate the received data timing signal using frequent transitions appearing in the received data. Useful. A communication system based on serializer/deserializer (SERDES) technology is an example of a system in which the binary eye pattern 1000 may be utilized as a basis for determining the ability to reliably recover data based on the eye opening of the binary eye pattern 1000. .

[0080] An M-wire N-phase encoding system, such as a 3-wire, 3-phase encoder, can encode a signal with at least one transition at every symbol boundary, and the receiver uses those guaranteed transitions to clock can be recovered. The receiver can require reliable data immediately prior to the first signal transition at a symbol boundary and must be able to reliably mask the occurrence of multiple transitions correlated to the same symbol boundary. Due to small differences in rise and fall times between signals carried on M-wires (e.g., triads of wires) and due to differences in received signal pairs (e.g., differential receivers 802a, 802b and 802c of FIG. 8) A slight difference in signal propagation time between AB, BC, and CA outputs) combinations can cause multiple receiver transitions.

[0081] Figure 11 shows an example of a multi-level eye pattern 1100 generated for a C-PHY three-phase signal. A multi-level eye pattern 1100 may be generated from the superposition of multiple symbol intervals 1102 . A multilevel eye pattern 1100 may be generated using a fixed and/or symbol independent trigger 1110 . The multi-level eye pattern 1100 has an increased number of voltage levels 1120, 1122 that can be attributed to multiple voltage levels measured by the differential receivers 802a, 802b, 802c and the N-phase receiver circuit (see FIG. 8). , 1124, 1126, 1128. In this example, multi-level eye pattern 1100 may correspond to possible transitions in a three-wire, three-phase encoded signal provided to differential receivers 802a, 802b, and 802c. The three voltage levels may cause differential receivers 802a, 802b, and 802c to generate strong voltage levels 1126, 1128 and weak voltage levels 1122, 1124 for both positive and negative polarities. Generally, only one signal wire 310a, 310b and 310c is undriven in a symbol and differential receivers 802a, 802b and 802c do not produce a 0 state (here 0 volts) output. The voltages associated with strong and weak levels need not be evenly spaced with respect to the 0 volt level. For example, weak voltage levels 1122, 1124 represent voltage comparisons that may include voltage levels reached by non-driven signal wires 310a, 310b and 310c. Multi-level eye pattern 1100 represents the waveforms produced by differential receivers 802a, 802b, and 802c because all three pairs of signals are assumed to be simultaneous when the data is captured at the receiving device. can overlap. The waveforms produced by differential receivers 802a, 802b, and 802c represent differential signals 810a, 810b, 810c representing a comparison of three pairs of signals (AB, BC, and CA).

[0082] Drivers, receivers and other devices used in a C-PHY three-phase decoder may exhibit different switching characteristics that can result in relative delays between signals received from the three wires. Signal propagation times due to slight differences in rise and fall times between the three signals on the triad of signal wires 310a, 310b, 310c and between pair combinations of signals received from the signal wires 310a, 310b, 310c. Multiple receiver output transitions may be observed at each symbol interval boundary 1108 and/or 1114 due to slight differences in . Multi-level eye pattern 1100 may capture rise and fall time differences as relative delays of transitions near each symbol interval boundary 1108 and 1114 . Differences in rise and fall times may be due to different characteristics of three-phase drivers. Differences in rise and fall times can also result in an effective shortening or lengthening of the duration of symbol interval 1102 for a given symbol.

[0083] Signal transition region 1104 represents a time, or period of uncertainty, where variable signal rise times prevent reliable decoding. State information can be reliably determined at an "eye opening" 1106, which represents a time period during which symbols are stable and can be reliably received and decoded. In one example, eye opening 1106 may be determined to start at tail 1112 of signal transition region 1104 and end at symbol interval boundary 1114 of symbol interval 1102 . In the example shown in FIG. 11, the eye opening 1106 begins at the tail 1112 of the signal transition region 1104 and the signaling states of the signal wires 310a, 310b, 310c and/or the three differential receivers 802a, 802b and 802c. can be determined to end at time 1116 when the output of has changed to reflect the next symbol.

[0084] The maximum speed of a communication link 220 configured for N-phase encoding may be limited by the duration of the signal transition region 1104 compared to the eye opening 1106 corresponding to the received signal. The minimum duration for symbol interval 1102 may be constrained, for example, by tight design margins associated with CDR circuit 524 in decoder 500 shown in FIG. Different signaling state transitions may be associated with different variations in signal transition times corresponding to two or more signal wires 310a, 310b and/or 310c, thereby causing differential receivers 802a, 802b and The output of 802c is changed at different times and/or rates relative to the symbol interval boundary 1108 where the inputs of differential receivers 802a, 802b and 802c begin to change. Differences between signal transition times can result in timing skew between signaling transitions in two or more difference signals 810a, 810b, 810c. The CDR circuitry may include delay circuitry and other circuitry to accommodate timing skews between differential signals 810a, 810b, and 810c.

[0085] Figure 12 provides an example of a CDR circuit 1200 for a 3-wire, 3-phase interface. The illustrated CDR circuit 1200 includes several features and functional elements common to many different types of clock recovery circuits. CDR circuit 1200 receives differential signals 1202, 1204, 1206, which may be derived from, for example, differential signals 810a, 810b, 810c generated by differential receivers 802a, 802b, and 802c of FIG. In CDR circuit 1200, each differential signal 1202, 1204, 1206 clocks a pair of D-type flip-flops 1210a, 1210b, 1210c to produce output signals 1230a-1230f. The output signals 1230a-1230f carry pulses when transitions are detected on the corresponding difference signals 1202, 1204, 1206. FIG. A rising edge applied to the clock input on the D-type flip-flop clocks a logic one through the D-type flip-flop. Inverters 1208a, 1208b, 1208c may be used to provide an inverted version of the difference signal 1202, 1204, 1206 to one of the D-type flip-flops in each corresponding pair of D-type flip-flops 1210a, 1210b, 1210c. Thus, each pair of D-type flip-flops 1210a, 1210b, 1210c generates pulses in response to the rising and falling edges detected in the corresponding difference signal 1202, 1204, 1206. FIG.

[0086] For example, the AB difference signal 1202 is provided to the first D-type flip-flop 1232 of the first pair of D-type flip-flops 1210a, and the inverter 1208a is applied to the first pair of D-type flip-flops 1210a. 2 D-type flip-flop 1234 is provided with an inverted version of the AB difference signal 1202 . A D-type flip-flop is initially in a reset state. A rising edge on the AB difference signal 1202 clocks a logic one through the first D-type flip-flop 1232, causing the output of the first flip-flop (r_AB) 1230a to transition to a logic one state. A falling edge on the AB difference signal 1202 clocks a logic one through the second D-type flip-flop 1234, causing the output of the second flip-flop (f_AB) 1230b to transition to a logic one state.

[0087] Output signals 1230a-1230f are provided to logic, such as OR gate 1212, which generates an output signal that may serve as a receiver clock (RxCLK) signal 1222. The RxCLK signal 1222 transitions to a logic 1 state when a transition occurs in the signaling state of any of the differential signals 1202,1204,1206. RxCLK signal 1222 is provided to programmable delay circuit 1214, which drives a reset signal (rb signal 1228) that resets the D-type flip-flops in D-type flip-flop pair 1210a, 1210b, 1210c. In the illustrated example, an inverter 1216 may be included when the D-type flip-flops 1210a, 1210b, 1210c are reset by a low signal. When D-type flip-flops 1210a, 1210b, 1210c are reset, the output of OR gate 1212 returns to a logic 0 state and the pulse on RxCLK signal 1222 is terminated. When this logic 0 state propagates through programmable delay circuit 1214 and inverter 1216, the reset condition on D-type flip-flops 1210a, 1210b, 1210c is released. Transitions on the difference signals 1202, 1204, 1206 are ignored while the D-type flip-flops 1210a, 1210b, 1210c are in the reset condition.

[0088] Programmable delay circuit 1214 is generally designed to produce a delay having a duration that exceeds the timing skew difference between the occurrence of the first and last transitions on difference signals 1202, 1204, 1206. configured to Programmable delay circuit 1214 configures the duration (ie, pulse width) of the pulses on RxCLK signal 1222 . Programmable delay circuit 1214 may be configured when set signal 1226 is asserted by a processor or other control and/or configuration logic.

[0089] The RxCLK signal 1222 may also be provided to a set of three flip-flops 1220 that capture the signaling states of the differential signals 1202, 1204, 1206 to provide a stable output symbol 1224 for each pulse occurring on the RxCLK signal 1222. . Delay or alignment logic 1218 may adjust the timing of the set of difference signals 1202 , 1204 , 1206 . For example, the delay or match logic 1218 may apply a delay on the RxCLK signal 1222 to ensure that the flip-flop 1220 captures the signaling state of the differential signals 1202, 1204, 1206 when the differential signals 1202, 1204, 1206 are stable. can be used to adjust the timing of the difference signals 1202, 1204, 1206 with respect to the pulses of . Delay or match logic 1218 may delay edges in difference signals 1202 , 1204 , 1206 based on the delay configured for programmable delay circuit 1214 .

[0090] A programmable delay circuit 1214 may be configured in the CDR circuit 1200 to accommodate possible large variations in transition times in the differential signals 1202, 1204, 1206. FIG. In one example, the programmable delay circuit 1214 is generally configured to provide a minimum delay period that exceeds the duration of the timing skew between the occurrence of the first transition on the differential signals 1202, 1204, 1206 and the occurrence of the last transition. be done. The delay time provided by programmable delay circuit 1214 is calculated to take into account the number of logic gates in the delay loop of CDR circuit 1200, a manufacturing process that may affect the operation of logic gates and/or programmable delay circuit 1214. , circuit supply voltage, and temperature (PVT) conditions are constrained to a minimum delay time that takes into account expected or observed variations. For reliable operation of CDR circuit 1200, the maximum delay time provided by programmable delay circuit 1214 may not be greater than the symbol interval. At faster data rates, the timing skew and delay time provided by the delay loop of CDR circuit 1200 increases as a fraction of symbol interval 1102 . Eye opening 1106 may be small compared to symbol spacing 1102, and eye opening 1106 may close at higher frequencies. The maximum symbol transmission rate reduces the percentage of symbol interval 1102 occupied by eye opening 1106 where the delay time provided by programmable delay circuit 1214 is below a threshold size that can support reliable capture of symbols. can be restricted when

[0091] FIG. 13 is a timing diagram 1300 illustrating some aspects of the operation of the CDR circuit 1200. As shown in FIG. The diagram relates to operation after programmable delay circuit 1214 is configured, set signal 1226 is inactive. CDR circuit 1200 operates as an edge detector. C-PHY three-phase encoding provides a single signaling state transition per unit interval (UI) 1302 . The state of each wire in the triplet and/or differences in the transmission characteristics of the triplet can cause transitions to appear at different times on two or more wires. The maximum difference in the times of occurrence of transitions in difference signals 1202 , 1204 , 1206 is sometimes referred to as skew time (t _skew ) 1304 . Other delays associated with CDR circuit 1200 are the propagation delay (t _ck2q ) 1314 through D-type flip-flop pairs 1210 a , 1210 b , 1210 c and the propagation delay associated with the rising edge passed through OR gate 1212 (t _{OR_0} ) 1306, the propagation delay (t _{OR_1} ) 1308 associated with the falling edge passed through the OR gate 1212, and the programmable delay (t _pgm ) that combines the delay introduced by the programmable delay circuit 1214 and the driver and/or inverter 1216. 1310 and a reset delay (t _rst ) 1312 corresponding to the delay between the time the rb signal 1228 is received by a pair of D-type flip-flops 1210a, 1210b, 1210c and the time the flip-flop outputs are cleared.

[0092] A loop delay (t _loop 1320) may be defined as follows.

The relationship between t _loop 1320 and UI 1302 may determine the reliability of operation of CDR circuit 1200 . This relationship is affected by the clock frequency used for transmission and variability in the operation of programmable delay circuit 1214, which has a direct impact on UI 1302. FIG.

[0093] In some devices, the operation of programmable delay circuit 1214 in FIG. 12 may suffer from variations in operating conditions, including variations in PVT conditions. The delay time provided by programmable delay circuit 1214 for a configured value can vary significantly from device to device and/or from circuit to circuit within a device. In conventional systems, the nominal operating conditions of the CDR circuit 1200 are generally such that the clock edge after the end 1112 of the signal transition region 1104 and before the beginning of the transition region to the next symbol, even under worst-case PVT effects. It is set by design to generate a clock edge somewhere in the middle of the eye opening 1106 under all PVT conditions to ensure that it occurs. Difficulties may arise in designing the CDR circuit 1200 to guarantee clock edges within the eye opening 1106 as the transmission frequency increases and the timing skew of the difference signals 1202 , 1204 , 1206 is large compared to the UI 1302 . For example, a typical delay circuit may produce delay values that vary by factor of 2 over all PVT conditions.

[0094] Figure 14 is a timing diagram 1400 that illustrates the effect of programmable delay circuit 1214 (see Figure 12) providing insufficient delay. In this example, t _loop 1406 is too short for the observed t _skew 1404 and multiple clock pulses 1408 , 1410 are generated in one UI 1402 . That is, the loop delay t _loop 1406 is not large enough relative to t _skew 1404 so that subsequent transitions on the differential signals 1202, 1204, 1206 are not masked. In the illustrated example, a second transition 1414 in one of the difference signals 1206 is detected after a pulse 1408 is generated in response to a first occurring transition 1412 in another one of the difference signals 1202. can be In this example, the recovered clock frequency may be twice the clock frequency used to transmit symbols on the three-phase interface.

[0095] Figure 15 is a timing diagram 1500 that illustrates the effect of programmable delay circuit 1214 providing too long a delay. In this example, there is an observed skew duration t _skew 1504 and t _loop 1506 is greater than UI 1502 . The CDR circuit 1200 may generate a clock pulse 1508 in response to the first occurring transition 1514 in the first UI 1502, while the rb signal 1228 is generated when transitions 1516, 1518 occur in the second UI 1512. , can be active. In the illustrated example, the transitions 1516, 1518 in the second UI 1512 are masked and the expected pulse 1510 corresponding to the second UI 1512 is suppressed. In this example, the recovered clock frequency may be 1/2 the clock frequency used to transmit symbols on the three-phase interface.

[0096] As illustrated by the examples of FIGS. 14 and 15, the CDR circuit 1200 may be subject to the following constraints.

Empirical evidence suggests that t loops 1320, 1406, 1506 are highly sensitive to _PVT . t _loop 1320 for CDR circuit 1200 can be restated as follows.

The loop time is susceptible to reliability at higher symbol rates due to multiple delays that are sensitive to PVT variations, and the double t - - _pgm delay and large delay associated with the 6-input OR gate 1212 contribute to the CDR It may limit the maximum frequency of the clock signal that can be recovered by circuit 1200 . Increasing the delay provided by programmable delay circuit 1214 to accommodate the range of potential PVT variations serves to further limit the maximum frequency of the clock signal that can be recovered by CDR circuit 1200 .

[0097] More recent implementations and proposed specifications for C-PHY, including the C-PHY 1.2 and C-PHY 2.0 specifications, use the conventional CDR to recover the clock signal in the receiver. Define the frequency of the symbol transmit clock signal that can exceed the capabilities of the circuit. The symbol transmit clock signal is used to control the rate of symbol transmission and determines the duration of UI 1302 . The duration of UI 1302 is reduced when the frequency of the symbol transmit clock signal is increased. Constraints imposed by loop delays in CDR circuit 1200 limit the minimum duration of UI 1302 that can be supported by CDR circuit 1200, which limits the maximum frequency of the symbol transmit clock signal that can be supported by CDR circuit 1200. Even using advanced device technology, the loop delay in CDR circuit 1200 can exceed 300 picoseconds under some PVT conditions, which compares conventional C-PHY applications to 2.5 picoseconds per second. It may be limited to a maximum symbol transmission rate of Gigasymbols. In some implementations, the constraint on the duration of the UI 1302 introduced by the loop delay in the CDR circuit 1200 makes the conventional CDR circuit 1200 conform to later generations of the C-PHY specification. may be voided for use in

[0098] A clock recovery circuit implemented in accordance with certain aspects disclosed herein may support higher clock frequencies defined by later generation C-PHY specifications. FIG. 16 provides an example clock recovery circuit 1640 that may be configured in accordance with some aspects of the present disclosure to support higher symbol transmit clock frequencies. Clock recovery circuit 1640 uses an optimized feedback loop that minimizes or reduces loop delays and enables clock recovery circuit 1640 to generate receive clock signal 1646 at a frequency of at least 8 GHz. A delay loop may be implemented using an asymmetric delay circuit that delays certain types of edges and passes other types of edges with a minimum delay. In the example shown, the delay loop is implemented using a few logic gates and a PVT insensitive delay block that responds only to rising edges. The illustrated clock recovery circuit 1640 can be configured to optimize loop timing and support very fast symbol transmission rates. A pulse generation and merging circuit 1600 generates and merges transition pulses representing detected transitions in difference signals 1602 , 1604 , 1606 . FIG. 17 is a timing diagram 1700 illustrating the timing associated with pulse generation and merging circuitry 1600 and clock recovery circuitry 1640. FIG.

[0099] The pulse generation and merging circuit 1600 receives difference signals 1602, 1604, 1606 representing differences in the signaling states of pairs of wires of the A, B and C wire triad. Differential signals 1602, 1604, 1606 may be received from differential receivers or comparators, such as differential receivers 802a, 802b and 802c that produce differential signals 810a, 810b, 810c shown in FIG. The pulse generation and merging circuit 1600 uses three exclusive pulses to generate limited-duration transition pulses 1704, 1706, 1708 in response to transitions occurring in the difference signals 1602, 1604, 1606. Target OR gates 1608, 1610, 1612 and corresponding delay circuits 1616, 1618 and 1620 are used. In the example timing diagram 1700 shown, transitions in the AB difference signal 1602, the BC difference signal 1604 and the CA difference signal 1606 occur at each of the symbol boundaries 1710a, 1710b, 1710c, 1710d shown. The transitions in the difference signals 1602, 1604, 1606 may occur at different times, so a skew 1702 may be observed between the first occurring transition and the last occurring transition. In the illustrated example, at the first illustrated symbol boundary 1710 a , the first occurring transition is observed on AB difference signal 1602 and the last occurring transition is observed on CA difference signal 1606 . The relationship between transitions may be different at each symbol boundary 1710a, 1710b, 1710c, 1710d. In operation, transitions occur on at least one difference signal 1602, 1604, 1606 at each symbol boundary 1710a, 1710b, 1710c, 1710d and more than three at one or more symbol boundaries 1710a, 1710b, 1710c, 1710d. may occur on the difference signals 1602, 1604, 1606 with less.

[0100] A first exclusive-OR gate 1608 receives AB difference signal 1602 and a delayed version of AB difference signal 1602 provided by AB delay circuit 1616 and determines the duration of the delay provided by AB delay circuit 1616. provides an AB_p signal 1622 containing a transition pulse 1704 having a duration controlled by . A second exclusive OR gate 1610 receives BC difference signal 1604 and a delayed version of BC difference signal 1604 provided by BC delay circuit 1618 and is controlled by the duration of the delay provided by BC delay circuit 1618. provides a BC_p signal 1624 that includes a transition pulse 1706 having a duration of . A third exclusive OR gate 1612 receives CA difference signal 1606 and a delayed version of CA difference signal 1606 provided by CA delay circuit 1620 and is controlled by the duration of the delay provided by CA delay circuit 1620. provides a CA_p signal 1626 that includes a transition pulse 1708 having a duration of . AB_p signal 1622, BC_p signal 1624, and CA_p signal 1626 are provided to OR gate 1614, which is derived from transition pulses 1704, 1706, 1708 in AB_p signal 1622, BC_p signal 1624, and CA_p signal 1626, and and/or provides an eg_pulse signal 1630, sometimes referred to herein as a combined signal, including pulses 1714 corresponding thereto. In some instances, two or more of transition pulses 1704, 1706, 1708 may overlap in time and merge in pulse 1714 of the combined signal.

[0101] The eg_pulse signal 1630 clocks a delay flip-flop (DFF 1642) in the clock recovery circuit 1640 . In some implementations, different types of flip-flops, latches, registers or other sequential logic circuits may be configured for use as alternatives to DFF1642. Each rising edge on eg_pulse signal 1630 clocks a logic 1 from the D input to the output (Q) of DFF 1642 . The output of DFF 1642 provides receive clock signal 1646 (Rclk_q). Delay circuits 1616, 1618 and 1620 may be configured to provide transition pulses 1704, 1706, 1708 with sufficient duration to clock DFF 1642 under expected or observed PVT conditions. For example, the duration of transition pulses 1704, 1706, 1708 can be configured based on the minimum duration for a clock pulse. Receive clock signal 1646 transitions high from an initial state in which receive clock signal 1646 is in the reset state (ie, set to a logic 0 state). Receive clock signal 1646 transitions high in response to the first rising edge in eg_pulse signal 1630 and after a delay caused by gate propagation delay (clk_q 1716), which may correspond to the cumulative transition time of OR gate 1614 and DFF 1642. do. Receive clock signal 1646 transitions high in response to the first rising edge in eg_pulse signal 1630, and additional edges in eg_pulse signal 1630 have no effect until DFF 1642 is reset.

[0102] DFF 1642 is reset when the output of rising edge delay circuit 1644 (Rclk_rst signal 1648) transitions high. Rising edge delay circuit 1644 passes a falling edge at its input with no delay or with a minimum delay before causing Rclk_rst signal 1648 to fall, and causes Rclk_rst signal 1648 to rise. It is configured to delay rising edges at the input. In the illustrated example, rising edge delay circuit 1644 receives receive clock signal 1646 as its input and delays rising edges in receive clock signal 1646 by a selected delay duration (rise_dly 1718). A falling edge in receive clock signal 1646 is delayed by a duration (fall_dly 1720 ) that may be due to transition times associated with one or more logic gates in DFF 1642 and/or rising edge delay circuit 1644 . Rising edge delay circuit 1644 is an example of an asymmetric delay circuit. It should be appreciated that other types of asymmetric delay circuits may be used in various implementations, including, for example, falling edge delay circuits.

[0103] After the Rclk_rst signal 1648 rises, the output of the DFF 1642 is reset and the receive clock signal 1646 returns to logic 0 after a delay (rst_dly 1722) that may be due to the gate transition time. The falling edge in receive clock signal 1646 is delayed by the duration of fall_dly 1720 and clock recovery circuit 1640 is returned to its initial state. In some implementations, the receive clock signal 1646 may be used to capture and/or decode data from the differential signals 1602, 1604, 1606. In some implementations, a driver circuit 1652 is provided to buffer and/or delay the received clock signal 1646 and provide the clock signal (RxCLK signal 1650) as an output of the clock recovery circuit 1640. RxCLK signal 1650 may be used to capture and/or decode data from differential signals 1602 , 1604 , 1606 .

[0104] In one example, the data recovery circuit 1660 may include one or more latches, registers or flip-flops 1664 that receive the RxCLK signal 1650. A latch, register or flip-flop 1664 may be configured to capture the signaling state of differential signals 1602 , 1604 , 1606 and provide a stable output symbol 1670 for each pulse occurring on RxCLK signal 1650 . Delay or match logic 1662 may adjust the timing of the difference signals 1602, 1604, 1606. FIG. For example, the delay or match logic 1662 may be configured to ensure that the latches, registers or flip-flops 1664 capture the signaling state of the differential signals 1602, 1604, 1606 when the differential signals 1602, 1604, 1606 are stable. It can be used to adjust the timing of the differential signals 1602 , 1604 , 1606 with respect to pulses on the RxCLK signal 1650 . Delay or match logic 1662 may provide relative delay or advance of edges in difference signals 1602 , 1604 , 1606 .

[0105] The maximum operating frequency of clock recovery circuit 1640 and corresponding minimum UI 1712 may be determined by timing constraints associated with clock recovery circuit 1640 and pulse generation and merging circuit 1600. FIG. The timing delays in pulse generation and merging circuit 1600 are outside the clock recovery circuit 1640 timing loop. Timing constraints can be stated as follows.

The clk_q1716, rst_dly1722 and fall_dly1720 parameters are quantifiable as a small number of gating switching delays, and the rise_dly1718 duration is selected based on the skew time under expected PVT conditions with small gating switching delays due to clk_q1716. can be

[0106] According to some aspects disclosed herein, rising edge delay circuit 1644 and delay circuits 1616, 1618 and 1620 may be configured during manufacturing, system configuration and/or system initialization. In some implementations, each of rising edge delay circuit 1644 and/or delay circuits 1616, 1618 and 1620 is programmable, eg, using initial line synchronization signaling sent over the C-PHY bus. , can be dynamically reconfigured and/or calibrated during bus operation. Delay circuits 1616, 1618 and 1620 may be calibrated based on measured, observed and/or expected operating conditions. A controller or processor may obtain a desired or required symbol transmission rate by optimizing the duration of rise_dly 1718 and/or the delays provided by delay circuits 1616, 1618 and 1620 for PVT conditions.

[0107] FIG. 18 illustrates delaying a rising edge by a configured or configurable delay duration while passing a falling edge without added delay, according to certain aspects disclosed herein. An example of a rising edge delay circuit 1800 that can be used for Other types of circuitry may be employed to delay rising edges while passing falling edges without added delay. The illustrated rising edge delay circuit 1800 may be implemented using a set of unit delay elements 1804, where different delay paths 1806 are different numbers of units concatenated to obtain selectable delay durations. A delay element 1804 is included. In some cases, different delay paths 1806 may be provided using a single multi-tap delay path. A signal received at an input 1802 of rising edge delay circuit 1800 is routed through one or more delay paths 1806 under the control of select circuit 1808, which selects a signal for driving output 1812 of select circuit 1808. A signal output by one of the delay paths 1806 is selected. In one example, selection circuit 1808 is implemented using a multiplexer. In another example, selection circuit 1808 is implemented using a set of switches that direct signals received at input 1802 to delay paths 1806, or use signals that traverse one of delay paths 1806. to drive the output 1812 of the selection circuit 1808 . Rising edge delay circuit 1800 may be configured by providing a select signal 1814 to select circuit 1808, where select signal 1814 determines which of delay paths 1806 drives output 1812 of select circuit 1808. do.

[0108] The output 1812 of the select circuit 1808 is gated by the input 1802 of the rising edge delay circuit 1800 using an AND gate 1810 . AND gate 1810 drives the output 1816 of rising edge delay circuit 1800 . A low logic level at input 1802 of rising edge delay circuit 1800 forces output 1816 of rising edge delay circuit 1800 to a low logic level. A rising edge at input 1802 of rising edge delay circuit 1800 occurs when input 1802 transitions from a low logic level to a high logic level. Output 1816 of rising edge delay circuit 1800 is controlled by output 1812 of select circuit 1808 when input 1802 is at a high logic level. Output 1812 of select circuit 1808 is initially at a low logic state, and a delayed version of the rising edge at input 1802 of rising edge delay circuit 1800 exits selected delay path 1806 and output 1812 of select circuit 1808 is It stays low until you cause it to transition high. A falling edge at input 1802 occurs when input 1802 transitions from a high logic level to a low logic level. A low logic level at input 1802 of rising edge delay circuit 1800, which is coupled to the input of AND gate 1810, forces output 1816 of rising edge delay circuit 1800 back to a low logic level.

[0109] Other implementations of rising edge delay circuit 1800 are contemplated. In some implementations, AND gate 1810 may be omitted when each of unit delay elements 1804 is implemented as a resettable delay element. In some implementations, each delay element in rising edge delay circuit 1800 may be reset by a low logic level on input 1802 of rising edge delay circuit 1800, so that a falling edge is delayed by (one or more is immediately propagated through the delay paths 1806 (with a small delay due to the switching time of the logic gates), and the rising edge is propagated through each delay element in each delay path 1806 . In another example, the type of selection circuit 1808 may be configured to obtain additional or minimal delay.
Examples of processing circuits and methods
[0110] Figure 19 shows an example of a hardware implementation for an apparatus 1900 employing processing circuitry 1902, which may be configured to perform one or more functions disclosed herein. According to various aspects of the disclosure, the elements disclosed herein, or any portion of the elements, or any combination of the elements, may be implemented using processing circuitry 1902 . Processing circuitry 1902 may include a number of devices, circuits, and/or logic that support the clock recovery techniques disclosed herein.

[0111] Processing circuitry 1902 may include one or more processors 1904 controlled by some combination of hardware and software modules. Examples of processor 1904 are microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gate logic, discrete hardware circuits, and the present disclosure. It includes other suitable hardware configured to perform various functions described throughout. One or more of processors 1904 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of software modules 1916 . The one or more processors 1904 are configured through a combination of software modules 1916 loaded during initialization, and may be further configured by loading or unloading one or more software modules 1916 during operation.

[0112] In the depicted example, the processing circuitry 1902 may be implemented using a bus architecture represented schematically by bus 1910. As shown in FIG. Bus 1910 may include any number of interconnecting buses and bridges, depending on the particular application and overall design constraints of processing circuitry 1902 . In one example, bus 1910 links various circuits including one or more processors 1904 and processor-readable storage media 1906 to each other. The processor-readable storage media 1906 can include memory devices and mass storage devices, and are sometimes referred to herein as computer-readable media and/or processor-readable media. Bus 1910 may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. Bus interface 1908 may provide an interface between bus 1910 and one or more transceivers 1912 . A transceiver 1912 may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceiver 1912 . Each transceiver 1912 provides means for communicating over a transmission medium with various other devices. Depending on the nature of device 1900 , a user interface 1918 (eg, keypad, display, speaker, microphone, joystick) may also be provided and communicatively coupled to bus 1910 either directly or through bus interface 1908 .

[0113] Processor 1904 may be responsible for managing bus 1910 and general processing, which may include executing software stored on computer-readable media, which may include processor-readable storage media 1906. In this regard, processing circuitry 1902, including processor 1904, can be used to implement any of the methods, functions and techniques disclosed herein. A processor-readable storage medium 1906 may be used to store data that is manipulated by the processor 1904 when executing software to implement any one of the methods disclosed herein. can be configured.

[0114] One or more processors 1904 in the processing circuitry 1902 may execute software. Software means instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software, whether called software, firmware, middleware, microcode, hardware description language, or otherwise. Should be construed broadly to mean packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, and the like. The software may reside in computer readable form in processor readable storage medium 1906 or in another external processor readable medium. Processor-readable storage media 1906 may include non-transitory computer-readable storage media and/or temporary processor-readable storage media. Non-transitory processor-readable storage media include, by way of example, magnetic storage devices (e.g. hard disks, floppy disks, magnetic strips), optical discs (e.g. compact discs (CDs) or digital versatile discs (DVDs)), Smart cards, flash memory devices (e.g., "flash drives", cards, sticks, or key drives), random access memory (RAM), ROM, PROM, erasable PROM (EPROM), EEPROM, registers, removable disks, and computers any other suitable medium for storing software and/or instructions that can be accessed and read by. Processor-readable storage media 1906 may also include, by way of example, carrier waves, transmission lines, and any other suitable medium for transmitting software and/or instructions that can be accessed and read by a computer. Processor-readable storage media 1906 may be resident within processing circuitry 1902 in processor 1904 , external to processing circuitry 1902 , or distributed across multiple entities including processing circuitry 1902 . Processor readable storage medium 1906 may be embodied in a computer program product. By way of example, a computer program product may include a computer readable medium in packaging materials. One skilled in the art will know how best to implement the described functionality presented throughout this disclosure, depending on the particular application and the overall design constraints imposed on the overall system. be recognized.

[0115] The processor-readable storage medium 1906 may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., sometimes referred to herein as software modules 1916. . Each of the software modules 1916 is installed or loaded on the processing circuitry 1902 and, when executed by the one or more processors 1904, contributes to a runtime image 1914 that controls the operation of the one or more processors 1904. Instructions and data. Some of the instructions, when executed, may cause processing circuitry 1902 to perform functions according to some of the methods, algorithms and processes described herein.

[0116] Some of the software modules 1916 may be loaded during initialization of the processing circuitry 1902, and these software modules 1916 are configured to enable performance of the various functions disclosed herein. Processing circuitry 1902 may be configured. For example, a number of software modules 1916 may configure internal devices and/or logic circuitry 1922 of processor 1904, access to external devices such as transceiver 1912, bus interface 1908, user interface 1918, timers, mathematical coprocessors, and the like. can manage Software modules 1916 may include control programs and/or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuitry 1902 . Resources may include memory, processing time, access to transceiver 1912, user interface 1918, and the like.

[0117] One or more of the processors 1904 of the processing circuitry 1902 may be multifunctional, whereby some of the software modules 1916 are loaded and configured to perform different functions or different instances of the same function. be done. The one or more processors 1904 may be further adapted to manage background tasks initiated in response to input from the user interface 1918, transceiver 1912, and device drivers, for example. In order to support the performance of multiple functions, one or more processors 1904 may be configured to provide a multitasking environment whereby each of the multiple functions can be performed by one processor as needed or desired. Implemented as a set of tasks serviced by one or more processors 1904 . In one example, a multitasking environment may be implemented using a time sharing program 1920 that passes control of the processor 1904 between different tasks such that each task receives an interrupt request upon completion of an outstanding operation and/or an interrupt request. , etc., control of the one or more processors 1904 is returned to the time sharing program 1920 . When a task has control of one or more processors 1904, processing circuitry is effectively dedicated to the purposes addressed by the functions associated with the control task. The time sharing program 1920 provides one or more functions to the operating system, a main loop that transfers control on a round-robin basis, functions that allocate control of one or more processors 1904 according to function prioritization, and/or processing functions. It may include an interrupt driven main loop that responds to external events by giving control of processor 1904 .

[0118] Apparatus 1900 may be adapted, configured, and/or operated in accordance with certain aspects of the present disclosure. In a first implementation, the resulting clock recovery apparatus comprises a plurality of pulse generation circuits 1628 (see FIG. 16), where each pulse generation circuit represents the differential signaling state of a pair of wires in a 3-wire bus. configured to generate transition pulses in response to transitions in the difference signal. In a first implementation, the clock recovery device includes a first logic circuit configured to provide a combined signal including pulses corresponding to transition pulses received from the plurality of pulse generation circuits 1628; a second logic circuit responsive to the pulses and configured to output clock signals used to decode information from transitions in the signaling states of the three-wire bus; , causing the clock signal to be driven to the first state. The second logic circuit may be implemented using flip-flops (such as delay flip-flops), latches, registers or other sequential logic circuits. In a first implementation, the clock recovery device comprises an asymmetric delay circuit configured to generate a reset signal from a clock signal, where the reset signal delays the transition to the first state and is added by passing the transition from the first state without delay, wherein the clock signal is driven from the first state after the transition of the clock signal to the first state is passed by the asymmetric delay circuit. can include

[0119] In a second implementation, each of the plurality of pulse generation circuits 1628 of the clock recovery apparatus of the first implementation receives as inputs an associated differential signal and a delayed version of the associated differential signal. It includes an exclusive OR gate configured as: In a third implementation, the first logic circuit of the second implementation is logic configured to provide a combined signal by combining output signals received from exclusive OR gates in each pulse generation circuit. Including gate. In a fourth implementation, each of the plurality of pulse generation circuits 1628 of the second or third implementation has a duration configured based on the minimum clock pulse duration defined for the second logic circuit. It is configured to generate a transition pulse with time. In a fifth implementation, the duration of the pulses generated by each of the plurality of pulse generation circuits 1628 of the second, third or fourth implementation is configurable.

[0120] In a sixth implementation, the transition to the first state includes the asymmetric of the first, second, third, fourth or fifth implementation. The duration of the delay applied by the delay circuit is configurable. In a seventh implementation, the asymmetric delay circuit of the first implementation, second implementation, third implementation, fourth implementation, fifth implementation or sixth implementation comprises a low logic a rising edge delay circuit configured to delay a transition from a state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without added delay; . In an eighth implementation, the clock of the first implementation, second implementation, third implementation, fourth implementation, fifth implementation, sixth implementation or seventh implementation The decompressor includes a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal.

[0121] Processing circuitry 1902 may be configured to implement at least some portion of the methods disclosed herein. In a first example, the clock recovery method includes generating a combined signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in signaling states of pairs of wires in a three-wire bus. and providing a combination signal to a logic circuit configured to provide the clock signal as its output, wherein a pulse in the combination signal causes the clock signal to be driven to the first state. providing a reset signal to the logic circuit, wherein the reset signal is derived from the clock signal by delaying the transition to the first state and passing the transition out of the first state without added delay; wherein the clock signal is driven from the first state after a transition of the clock signal to the first state is passed by the asymmetric delay circuit. Logic circuits may be implemented using flip-flops (such as delayed flip-flops), latches, registers or other sequential logic circuits.

[0122] In a second example, the clock recovery method of the first example includes the first clock recovery method by performing an exclusive OR gate function on the first difference signal and a delayed version of the first difference signal. generating a transition pulse for the difference signal of . In a third example, the clock recovery method of the first example or the second example includes at least one pulse to provide a corresponding transition pulse with a duration based on the minimum clock pulse duration defined for the logic circuit. Including configuring the generating circuit. In a fourth example, the clock recovery method of the first example, second example, or third example includes calibrating at least one pulse generation circuit based on operating conditions of the three-wire bus. In a fifth example, the clock recovery method of the first example, second example, third example or fourth example is to select the duration of the delay applied to the transition to the first state. includes constructing an asymmetric delay circuit in In a sixth example, the asymmetric delay circuit of the first example, second example, third example, fourth example, or fifth example is adapted to delay a transition from a low logic state to a high logic state. and further configured to pass a transition from a high logic state to a low logic state without added delay. In a seventh example, the clock recovery method of the first example, second example, third example, fourth example, fifth example or sixth example is based on timing information provided in the clock signal. clocking a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus.

[0123] Figure 20 is a flowchart 2000 of a clock recovery method that may be implemented in a receiving device coupled to a 3-wire C-PHY interface. At block 2002, a receiving device may generate a combination signal that includes pulses corresponding to transition pulses generated in response to transitions in a difference signal representing differences in signaling states of pairs of wires in the three-wire bus. At block 2004, the receiving device may provide the combination signal to a logic circuit, the logic circuit configured to provide the clock signal as its output. Logic circuits may be implemented using flip-flops (such as delayed flip-flops), latches, registers or other sequential logic circuits. A pulse in the combination signal causes the clock signal to be driven to the first state. At block 2006, the receiving device may provide a reset signal to the logic circuitry. The reset signal is derived from the clock signal by delaying the transition to the first state and passing the transition out of the first state without added delay. The clock signal is driven from the first state after passing the transition of the clock signal to the first state.

[0124] The receiving device may generate a transition pulse for the first difference signal by performing an exclusive OR gate function on the first difference signal and a delayed version of the first difference signal. The receiving device may configure at least one pulse generator circuit to provide corresponding transition pulses with durations based on the minimum clock pulse duration defined for the logic circuit. The receiving device may calibrate the at least one pulse generation circuit based on the operating conditions of the 3-wire bus. The receiving device may configure the asymmetric delay circuit to provide the desired duration of delay applied to the transition to the first state. In one example, an asymmetric delay circuit is implemented as a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state. The rising edge delay circuit may be further configured to pass transitions from a high logic state to a low logic state without added delay.

[0125] In various implementations, a clock signal may be provided to a wire state decoder configured to decode symbols from transitions in signaling states of a three-wire bus based on timing information provided in the clock signal.

[0126] FIG. 21 is a diagram illustrating an example of a hardware implementation for an apparatus 2100 employing processing circuitry 2102. As shown in FIG. Processing circuitry 2102 generally has at least one processor 2116 which may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer and state machine. Processing circuitry 2102 may be implemented using a bus architecture represented schematically by bus 2120 . Bus 2120 may include any number of interconnecting buses and bridges, depending on the particular application and overall design constraints of processing circuitry 2102 . Bus 2120 is coupled by processor 2116 , modules or circuits 2104 , 2106 and 2108 , differential receiver circuit 2112 that produces differential signals 2122 representing differences in signaling states between different pairs of connectors or wires 2114 , and processor readable storage medium 2118 . The various circuits represented, including one or more processors and/or hardware modules, are linked together. Bus 2120 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore not further described. not.

[0127] Processor 2116 is responsible for general processing, including execution of software stored in processor-readable storage medium 2118 . The software, when executed by processor 2116, causes processing circuitry 2102 to perform various functions described above for a particular device. Processor readable storage medium 2118 also stores data manipulated by processor 2116 when executing software, including data decoded from symbols transmitted over connector or wire 2114, which may be configured as a C-PHY bus. can be used to Processing circuitry 2102 further includes at least one of modules 2104 , 2106 and 2108 . Modules 2104, 2106 and 2108 are either software modules running in processor 2116, residing/stored in processor readable storage medium 2118, or one or more hardware modules coupled to processor 2116. or some combination thereof. Modules 2104, 2106 and/or 2108 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0128] In one configuration, apparatus 2100 may be configured for data communication according to the C-PHY interface protocol. Apparatus 2100 can be used to decode symbols from transitions in signaling states of a 3-wire bus with modules and/or circuitry 2108 configured to generate transition pulses in response to transitions in signaling states of differential signal 2122. and a configuration module and/or circuit 2104 for configuring the delay duration used in generating the transition pulse and/or receive clock. can include

[0129] In one example, the apparatus 2100 has a plurality of pulse generation circuits 1628 (see FIG. 16), one or more combinational logic circuits, and a clock recovery circuit. Each of the pulse generation circuits 1628 is configured to generate transition pulses in response to transitions in the difference signal 2122 representing the difference in signaling states of pairs of wires in the three-wire bus. One combinatorial logic circuit is configured to provide a combinatorial signal including pulses corresponding to the transition pulses received from the plurality of pulse generator circuits 1628 . In one example, three difference signals 2122 are combined using logic OR gates such that a high logic level of a transition pulse in any difference signal 2122 causes a high logic level in the combination signal, where The state returns to the low logic level when the three difference signals 2122 are at the low logic level. The clock recovery circuit may be implemented using flip-flops (such as delay flip-flops), latches, registers or other sequential logic circuits. A clock recovery circuit is responsive to pulses in the combination signal and is configured to output a clock signal used to decode information from transitions in the signaling states of the three-wire bus. A pulse in the combination signal causes the clock signal to be driven to the first state. A clock recovery circuit may include an asymmetric delay circuit configured to generate a reset signal from a clock signal. A reset signal is generated by delaying the transition to the first state and passing the transition out of the first state without added delay. The clock signal is driven from the first state after the transition of the clock signal to the first state is passed by the asymmetric delay circuit.

[0130] Each pulse generation circuit includes an exclusive OR gate configured to receive as inputs an associated differential signal and a delayed version of the associated differential signal. The combinational logic circuitry may include logic gates configured to provide a combination signal by combining the output signals received from the exclusive OR gates of each pulse generation circuit. Each pulse generation circuit is configured to generate a pulse having a duration configured based on the minimum clock pulse duration defined for the clock recovery circuit. The duration of the pulses generated by the delay circuits 1616, 1618, 1620 in each of the plurality of pulse generation circuits 1628 may be configurable. The duration of the delay applied by the asymmetric delay circuit to the transition to the first state may be configurable.

[0131] In one example, the asymmetric delay circuit is configured to delay a transition from a low logic state to a high logic state and passes a transition from a high logic state to a low logic state without added delay. implemented as a rising edge delay circuit, further configured as: In one example, apparatus 2100 includes a wire state decoder configured to decode symbols from transitions in signaling states of a 3-wire bus based on timing information provided in a clock signal.

[0132] The processor-readable storage medium 2118 may be a non-transitory storage medium and may store instructions and/or code that, when executed by the processor 2116, cause the processing circuitry 2102 to: generating a combined signal including one or more transition pulses, where each transition pulse is generated in response to a transition in a difference signal 2122 representing a difference in signaling states of pairs of wires in the three-wire bus; to do The instructions and/or code instruct the processing circuit 2102 to provide a combination signal to the logic circuit, the logic circuit being configured to provide a clock signal as its output, wherein the pulses in the combination signal correspond to the clock signal. is driven to the first state. Logic circuits may be implemented using flip-flops (such as delayed flip-flops), latches, registers or other sequential logic circuits. The instructions and/or code instruct processing circuitry 2102 to provide a reset signal to the logic circuitry, where the reset signal delays the transition to the first state and exits the first state without added delay. is derived from the clock signal by passing transitions of . The clock signal is driven from the first state after passing the transition of the clock signal to the first state.

[0133] The instructions and/or code instruct the processing circuitry 2102 to perform an exclusive OR gate function on the first difference signal and a delayed version of the first difference signal. to generate a transition pulse of . The instructions and/or code cause processing circuitry 2102 to configure at least one pulse generation circuitry to provide corresponding transition pulses having durations based on the minimum clock pulse duration defined for the logic circuitry. obtain. The instructions and/or code may cause processing circuitry 2102 to calibrate at least one pulse generator circuit based on operating conditions of the three-wire bus. The instructions and/or code may cause processing circuitry 2102 to configure an asymmetric delay circuit to provide a desired duration of delay applied to the transition to the first state. The asymmetric delay circuit is configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without added delay. , can be implemented using a rising edge delay circuit. The instructions and/or code cause processing circuitry 2102 to provide clock signals to a wire state decoder configured to decode symbols from transitions in signaling states of the 3-wire bus based on timing information provided in the clock signals. can let

[0134] It is understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Additionally, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to implement the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the claims are not to be limited to the embodiments shown herein, but are to be accorded the fullest scope consistent with claim language, where references to elements in the singular are , unless so specified, does not mean "one and only", but rather "one or more". Unless otherwise specified, the term "some" refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known, or later become known, to those skilled in the art are expressly incorporated herein by reference. , is encompassed by the claims. Moreover, nothing disclosed herein is made available to the public, whether or not such disclosure is explicitly recited in the claims. No claim element should be construed as means-plus-function unless that element is specifically recited using the phrase "means for."

Claims (29)

A clock recovery device,
a plurality of pulse generator circuits, wherein each pulse generator circuit is configured to generate a transition pulse in response to a transition in a differential signal representing a difference in signaling states of a pair of wires in the three-wire bus;
a first logic circuit configured to provide a combined signal including pulses corresponding to transition pulses received from the plurality of pulse generation circuits;
a second logic circuit responsive to pulses in said combination signal and configured to output a clock signal used to decode information from said three-wire bus; the pulse causes the clock signal to be driven to a first state;
an asymmetric delay circuit configured to generate a reset signal from said clock signal, wherein said reset signal delays a transition to said first state and enters said first state without added delay; wherein the clock signal is driven from the first state after a transition of the clock signal to the first state is passed by the asymmetric delay circuit;
a clock recovery device. each of the plurality of pulse generation circuits,
an exclusive OR gate configured to receive as inputs an associated differential signal and a delayed version of the associated differential signal;
The clock recovery device according to claim 1, comprising: The first logic circuit is
a logic gate configured to provide said combined signal by combining output signals received from said exclusive OR gates in each pulse generation circuit;
3. The clock recovery device according to claim 2, comprising: 3. The method of claim 2, wherein each of said plurality of pulse generating circuits is configured to generate a transition pulse having a duration configured based on a minimum clock pulse duration defined for said second logic circuit. A clock recovery device as described. 3. The clock recovery apparatus of claim 2, wherein the duration of pulses generated by each of said plurality of pulse generating circuits is configurable. 2. The clock recovery apparatus of claim 1, wherein the duration of the delay applied by said asymmetric delay circuit to transition to said first state is configurable. The asymmetric delay circuit is configured to delay a transition from a low logic state to a high logic state, and further to pass a transition from the high logic state to the low logic state without added delay. 2. The clock recovery apparatus of claim 1, comprising a configured rising edge delay circuit. a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal;
The clock recovery device of claim 1, further comprising: A clock recovery method comprising:
generating a combined signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in signaling states of pairs of wires in the three-wire bus;
providing said combination signal to a logic circuit configured to provide a clock signal as an output, wherein a pulse in said combination signal causes said clock signal to be driven to a first state;
providing a reset signal to the logic circuit, wherein the reset signal delays a transition to the first state and passes a transition out of the first state without added delay; derived from the clock signal, the clock signal being driven from the first state after passing a transition of the clock signal to the first state;
A clock recovery method comprising: Generating a transition pulse for the first difference signal by performing an exclusive OR gate function on the first difference signal and a delayed version of the first difference signal;
10. The clock recovery method of claim 9, further comprising: configuring at least one pulse generation circuit to provide corresponding transition pulses having durations based on the minimum clock pulse duration defined for the logic circuit;
10. The clock recovery method of claim 9, further comprising: calibrating at least one pulse generation circuit based on operating conditions of the three-wire bus;
10. The clock recovery method of claim 9, further comprising: configuring an asymmetric delay circuit to select the duration of the delay applied to transition to the first state;
10. The clock recovery method of claim 9, further comprising: The asymmetric delay circuit is configured to delay a transition from a low logic state to a high logic state, and further to pass a transition from the high logic state to the low logic state without added delay. 14. The clock recovery method of claim 13, comprising a configured rising edge delay circuit. providing the clock signal to a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal;
10. The clock recovery method of claim 9, further comprising: A non-transitory processor-readable storage medium having one or more instructions that, when executed by at least one processor of processing circuitry in a receiver, cause the at least one processor to:
generating a combined signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in signaling states of pairs of wires in the three-wire bus;
providing the combination signal to a logic circuit, the logic circuit being configured to provide a clock signal as its output, wherein a pulse in the combination signal causes the clock signal to be driven to a first state; cause
providing a reset signal to the logic circuit, wherein the reset signal delays a transition to the first state and passes a transition out of the first state without added delay; derived from the clock signal, the clock signal being driven from the first state after passing a transition of the clock signal to the first state;
A non-transitory processor-readable storage medium that causes to the at least one processor;
Generating a transition pulse for the first difference signal by performing an exclusive OR gate function on the first difference signal and a delayed version of the first difference signal;
17. The storage medium of claim 16, further comprising instructions for causing: to the at least one processor;
configuring at least one pulse generation circuit to provide corresponding transition pulses having durations based on the minimum clock pulse duration defined for the logic circuit;
17. The storage medium of claim 16, further comprising instructions for causing: to the at least one processor;
calibrating at least one pulse generation circuit based on operating conditions of the three-wire bus;
17. The storage medium of claim 16, further comprising instructions for causing: to the at least one processor;
configuring an asymmetric delay circuit to select the duration of the delay applied to transition to the first state;
17. The storage medium of claim 16, further comprising instructions for causing: The asymmetric delay circuit is configured to delay a transition from a low logic state to a high logic state, and further to pass a transition from the high logic state to the low logic state without added delay. 21. The storage medium of claim 20, comprising a configured rising edge delay circuit. to the at least one processor;
providing the clock signal to a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal;
17. The storage medium of claim 16, further comprising instructions for causing: A clock recovery device,
means for generating a combined signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in signaling states of pairs of wires in a three-wire bus;
means for providing a clock signal including logic circuitry responsive to pulses in said combination signal, wherein said pulses in said combination signal cause said clock signal to be driven to a first state; ,
means for providing a reset signal to said logic circuit, wherein said reset signal delays transitions to said first state and passes transitions out of said first state without added delay. derived from the clock signal by, wherein the clock signal is driven from the first state after passing a transition of the clock signal to the first state;
a clock recovery device. 24. The method of claim 23, further comprising means for generating said one or more transition pulses, each transition pulse being generated using a corresponding differential signal and a delayed version of said corresponding differential signal. A clock recovery device as described. 24. The clock recovery apparatus of claim 23, wherein at least one pulse generator circuit is configured to provide corresponding transition pulses having durations based on a defined minimum clock pulse duration for the logic circuit. 24. The clock recovery apparatus of claim 23, wherein one or more pulse generation circuits are calibrated based on operating conditions of said 3-wire bus. 24. The clock recovery apparatus of claim 23, wherein said means for providing said reset signal is configurable to select the duration of a delay applied to transition to said first state. said means for providing said reset signal is configured to delay a transition from a low logic state to a high logic state; 28. The clock recovery apparatus of claim 27, comprising a rising edge delay circuit further configured to pass. 24. The clock recovery of claim 23, wherein the clock signal is provided to a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal. Device.

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