200825590 九、發明說明： 【發明所屬之技術領域】 本發明提供一種液晶顯示器，特別是一種具有網狀結構之共 通線之液晶顯示器，以降低電阻、電容所造成的訊號延遲效應。 【先前技術】200825590 IX. Description of the Invention: [Technical Field] The present invention provides a liquid crystal display, and more particularly to a liquid crystal display having a common structure of a mesh structure to reduce signal delay effects caused by resistance and capacitance. [Prior Art]
一般而s，液晶顯示器（Liquid Crystal Display，LCD )可以藉 由分別地提供對應於畫面資料之資料訊號至液晶盒(Liquid Cell)，調整液晶盒的光穿透率以顯示畫面資料。液晶顯示器則包 含·具有矩陣排列液晶盒之液晶面板，以及驅動用之積體電路 (Integrated Circuit，1C ) 〇 、 液晶面板逛包括：一彩色濾光片基板、一薄膜電晶體陣列基 板，j對應於該彩色濾光片基板、以及一夾於該彩色濾光片基板 與该薄膜電晶體陣列基板間之液晶層。薄膜電晶體陣列基板包 含·用以傳輸由資料驅動積體電路所提供之資料訊號至液晶各之 資料線，以及用以傳輸由閘極驅動積體電路所提供之掃瞄訊^之 閘極線，其情晶錢由彼此交錯之賊線與閉極線狀義广間 極驅動積體電路，依序地提供掃瞄訊號至閘極線，以一個 個地依序選擇液晶盒。另外，·鶴積體電 提供至所選閘極線之液晶盒。 ^ + 請參閱第1目，其為習知畫素結構之佈局示意圖，此種晝素 結構又被稱為儲存電容在舰線或共通餘上（Cs仙。麵 =結構，其配，於-基板上，並至少包含：1極線ω、一資^ 線1卜以及-溥膜電晶體12。晝素區域係由延閘極_資料峻所 =二該第ΐίΐ，於該第—方向。_電晶體12包括：一 閘極120、-通運層⑵、-源極122與一汲極123，閘極12〇電 5 200825590 透過接觸$==2紐連接至資料線η，沒極123則 免注運接晝素電極13 〇 晝素的儲存雷交〗a a . 一夾於該下電極15盥却·下電極15、一上電極17、以及 在晝素區域内之a、禹=笔極17間之介電層。下電極15是配置 閘極線ίο、閘極的一部分，其約略平行於閘極線10，且與 蝕刻等製程所形成。卜目♦同，皆係由一第一金屬層經曝光、顯影、 性連接，鱼資毛極17透過接觸窗口 18與晝素電極13電 金屬層經曝、及極123相同，皆係由一第二 第二金屬層間配4衣程所形成。另外’第—金屬層與 間則配置有一純化^護3極絕緣層’而第二金屬層與晝素電極13 知的畫素結構之矩陣伟局示意圖，在習 結。因此，在習知第一方向配置’且彼此之間電性連 訊=遲效應相^顯，|電阻、f容所造成的 過特喰ίί要Ϊ出一種液晶顯示器與其製造方法，其透 _叫供社會大眾具有高度晝面品質之液晶顯示器。 【發明内容】 以降3日ίίΓ的，係提供一種液晶顯示器與其製造方法， 牛低/、通、、泉之电阻一電容訊號延遲效應。 -資供液晶顯示器，包含：—閘極線配置於—基板上； -ί 目交，·一第一共通線平行於該閘極線；以及 弟一共通線横越該閘極線。 其較佳者，包含·· 一閘極絕緣層，位於該第一I 以及-鈍化保制，位於該第—共猶與該第二 6 200825590 中，該鈍化保護層具有一第一通孔與一第二通孔。 對應觀聽韻第—共魏，且該第二通孔 $，ίΐΐ者’ 5含：—導電元件’透過該第一通孔與該第二通 孔，包性連接該第一共通線與該第二共通線。 、 導電ί=ί白3電f件伽一透明導電材料所製成，該透明 化辞摻轉、氧化鱗、紐娜_以及氧 ❿ -丘ΐίϊί ’該閘極線包含了—第—部分與—第二部分。該第 了，、通、、泉杈越且位於該第一部分與該第二部分之間。嗲丘 於該第—通孔與該第二通孔，。該第-Ϊ孔ϊϋ 該弟-部分，且該第二通孔對應於該第二部分。、⑽應於 $交佳者’包含··-導電元件’透過 孔，電性連接該第一部分與該第二部分。 、札…亥弟一通 其較佳者，該導電元件係由一透明導電材料所奥点，贫、t aa 導電材料係選自於由氧化銦錫、氧化銦鋅、氧^ = · 化辞摻雜鎵所域瞬組。 祕机德以及氧 料本提ΐ—種液晶顯示器之製造方法’包含下列步驟： =Iff基板上；形成—資料線與該閘極線相交； “Γ 該閘極線；以及形成—第二共通線橫越 iL、ii較佳者’包含下列步驟：形成—閘極絕緣層，位於該第一 /、通、、泉之上，形成一鈍化保護層，位於該第二共通 蝕刻該鈍化保護層，形成一第一通孔與一第二通孔、。 ， 別盘佳者，包含下列步驟：形成—導電元件，透職第一通 孔與该弟二通孔’電性連接該第—共通線與該第二共通線。 7 ,200825590 、其較佳者，該導電元件係由_ ，導電材料係選自於由氧化銦錫卜=材料所製成，且該透 氧化鋅摻雜鎵所組成的群纟 二銦鋅、氧化鋅摻雜鋁以及 二部分。 μ销板線包含了-第—部分與一第 其較佳者，包含下列步驟： 孔與該第二通孔，電性連接 f 兀件，透過該第一通 植補知-部分與該第二部分。 八孝父佳者，該導電元件係由一 帝 明導電材料係選自於由氧化銦錫、材，所製成’且該透 氧化鋅摻雜鎵所組成的群組。軋化銦鋅、氧化鋅摻雜鋁以及 為讓本發明之上述和其他目的、 /文特舉較佳實施例，並配合所更明顯易懂， 得在此顯示器技術領域中，且有通^ 1細说明如下，以使 發明之技術内容與特徵。通吊之知識者，能理解與認知本 【實施方式】 第3圖為本發明之一實施例，i金 圖則為其赚H，之剖齡意:^ ^素結構之佈局示意圖，第4 睛，第3圖，晝素電極結構包含：—閘極線Μ、一資料線 極線30 /口者一弟一方向配置，而資料線31貝.I沿著-第二方向配 置，且該第^方向約略與該第一方向垂直。第一共通線&平行於 閘極線30,第二共通線33則與該閘極線3〇相交。薄膜電晶體34 包含：一閘極340、一通道層34卜一源極342以及—汲極祕。 閘極340與閘極線30電性連接，源極342與資料線31電性連接， 汲極343則透過接觸孔36與晝素電極35電性連接。 閘極線30、第一共通線32與閘極340，皆經曝光、顯影、餘 刻一第一金屬層而形成，而資料線31、第二共通線33、源極342 8 .200825590 光、顯影、賴—第二金屬層而形成。閘極絕 ί弟厂金屬層與第f金屬層之間。第一共通線32與 伟由錫πΐ透過^導電①件37電性連接，該導電元件37 ^ 〇娜，ΙΤ〇)、氧化姻辞㈤“— 氧化鋅料雜（施而隱^网祝⑼涵）以及 ===u=p=；^e)咖帽料所製 盘一第一』,3 共通線之上，且具有一第一通孔381 二1弟一通孔381對應於第一共通線32，而第二 -通孔381· 弟二共通線33。因此’導電元件37係透過該第 通線33。 一以弟一通孔382 ’電性連接第一共通線32與第二共 提供= = 此可知，本發明所 丑ί ί ，其次形成一閉極340、一閘極線30與一第一 f則約略與閘極線30平行。閘極340、_線顧 層 =目同之第—金屬層，即皆由曝光、顯影、姓 閘極ίίο在ίί 4i"t’f形成一閉極絕緣層42’以覆蓋閘極340、 續層一=形成再 上，第—共通線33，緊接著形成在閘極絕緣層42之 3卜第極343恰好位於通道層341之上方。資料線 層，即λ汲極343則屬於相同之第二金屬 性連接於資“终3广、5、1虫刻该第二金屬層所形成，源極342電 、、〜泉1。閘極340、通道層341、源極342與汲極343 9 200825590 構成缚膜電晶體34。 於其料線3卜第二共通線33、源極342與没極343之後， ^基板4G上再形成—鈍化保護層44，以覆蓋上述 蝕刻的結構。接著，再蝕刻該鈍化保護層科盡極 = 對應於該第一共通線32之第一通孔 保\層44，以形成一對應於該第二共通線33之第二通孔π]。苴 二;7在m保護層44上’形成一由透明導電材料所製之導電； 通沒第一通孔381與第二通孔382，電性連接第一共 二共通線33。其中’導電元件37係由氧化銦錫、氧 化銦鋅、乳化鋅摻雜铭以及氧化鋅摻雜鎵等透明導電材料所製成。 請f閱，5圖’其為本發明之—畫素結構，其矩陣佈局之示 。弟一共通線32與第二共通線33，彼此透過導電元 1連接，並共同構成一網狀結構，以降低共通 — 號延遲效應。 心 电谷甙 第7 本發明之另一實關，其晝素結構之佈局示意圖， 弟7圖則為其剖線K-K，之剖面示意示圖。 -第= 6圖’晝素結構包含：—閘極線6G、—資料線6卜 6〇 ”二、通:線62、一第二共通線63與一薄膜電晶體64。閘極線 者—第一方向配置，而資料線61則沿著一第二方向配1，且 ^弟=方向約略與該第一方向垂直。第—共通線62平行於間 弟二共通線63則與該閘極線60相交。薄膜電晶體64包入". 二，，640、一通道層64卜一源極642以及一沒極6奶。閘 人閘極線60電性連接，源極642與資料線61電性連接 則透過接觸孔66與晝素電極65電性連接。 43 在本實施例中，閘極線60係由一第一部分6〇1與—立八 Ζ戶?構成。第二共通線63橫越該閘極線6。’亦即橫第匕 =與第/部分602之間，或橫越第一部分6〇1與^^刀 之間。弟-部分6〇1與第二部分602，係透過一導電元件67電^ 200825590 連接，其係由氧化銦錫、氧化銦鋅、氧化^ ^ 雜鎵等透縣電㈣所黏。_線鋅摻 通線63與閘極640，係由曝光、顯影、 1全^ ^^共 而資料線6卜源極642與汲極643，則f ^旦屬層二斤形成， 二金屬層·成。鈍娜 74崎一第 圖所示，且具有-第-通孔681與一第t如第7 極線60之第一部分601與第二部分6〇 導^^^於閘 :;通孔⑻與一一^ 弟-金屬層之結構。，次，在閘極絕緣層72上弟；^泉63^ 64i ’而在通道層641之表面上，再形成 :通道請與接下來形成的源極642與上 == 貧料線61緊接著形成在閘極絕緣層72之上， 汲極643恰好位於通道層641之上方極642與 極⑷則屬於相同之第二金屬層，^皆貝由 f =2與沒 逼層64卜祕642與没極⑷構成一薄膜電晶體40通 tV/S?!^643 ^ ^ ^ 70 接著，再蝕刻該鈍化保護二二 的結構。 之第二通孔682。其次，在兮a ^應亥弟—邛刀602 電材料所製之導電元護層上’形成一由透明導 係由氧化銦餛、苟仏力A /、弟―邛刀602。其中，導電元件67 、 …1化轉、氧化鋅雜㈣及A化鋅摻雜鎵等透 π 200825590 明導電材料所製成。 „8圖，其為本發明之另一書 ’其矩陣佈局之 63，彼此透過導電元件67 =意圖H通線62與第二共通線 電性連接’並朗構成—網狀結構，以降低共通線之電阻—電容 訊號延遲效應 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本 發明’任何熟習此技藝者，在不脫離本發明之精神和範圍内，當 可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請 專利範圍所界定者為準。Generally, a liquid crystal display (LCD) can adjust the light transmittance of the liquid crystal cell to display the image data by separately providing a data signal corresponding to the image data to the liquid crystal cell (Liquid Cell). The liquid crystal display comprises a liquid crystal panel with a matrix array of liquid crystal cells, and an integrated circuit for driving (1C). The liquid crystal panel includes: a color filter substrate, a thin film transistor array substrate, j corresponding The color filter substrate and a liquid crystal layer sandwiched between the color filter substrate and the thin film transistor array substrate. The thin film transistor array substrate comprises: a data line for transmitting the data signal provided by the data driving integrated circuit to the liquid crystal, and a gate line for transmitting the scan signal provided by the gate driving integrated circuit The emotional crystal money is composed of a thief line and a closed-circuit line-shaped inter-polar drive integrated circuit, which sequentially provide a scanning signal to the gate line, and sequentially selects the liquid crystal cells one by one. In addition, the company provides a liquid crystal cell to the selected gate line. ^ + Please refer to the first item, which is a schematic diagram of the layout of the conventional pixel structure. This kind of halogen structure is also called storage capacitor on the ship line or common (Cs Xian. Surface = structure, its distribution, in - On the substrate, and at least: a 1-pole line ω, a ^ 线 1 1 and a 溥 电 电 电 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域. The transistor 12 includes a gate 120, a transport layer (2), a source 122 and a drain 123, and a gate 12 5 5 200825590 connected to the data line η through contact $==2, and 123 without the pole No-loading of the halogen electrode 13 storage of the halogen. Aa. A clip to the lower electrode 15 but the lower electrode 15, an upper electrode 17, and a, 禹 = pen pole in the halogen region 17 dielectric layers. The lower electrode 15 is a gate electrode ίο, a part of the gate, which is approximately parallel to the gate line 10, and is formed by etching and other processes. The metal layer is exposed, developed, and sexually connected, and the fish hair pole 17 is exposed through the contact window 18 and the electric metal layer of the halogen electrode 13 is exposed, and the pole 123 is the same, and is connected by a second The second metal layer is formed by 4 coats. In addition, a schematic diagram of the matrix structure of the pixel structure of the second metal layer and the halogen electrode 13 is disposed between the first metal layer and the third metal layer. In the process of learning. Therefore, in the first direction of the configuration 'and the electrical connection between each other = late effect, the resistance, f capacity caused by the special characteristics of the liquid crystal display and its manufacturing method It is a liquid crystal display that is highly praised by the public. [Invention content] To provide a liquid crystal display and its manufacturing method, the resistance of a cow low /, pass, and spring is delayed by a capacitor signal. Effect - The liquid crystal display includes: - the gate line is disposed on the substrate; - ί eye, a first common line is parallel to the gate line; and the common line crosses the gate line. Preferably, a gate insulating layer is disposed in the first I and the passivation protection, and the passivation protective layer has a first via hole and a first pass and a passivation protection layer. The second through hole. And the second through hole $, ΐΐ ' '5 includes: - the conductive element 'through the first through hole and the second through hole, the first common line and the second common line are connected in a baggage manner. ί ί 3 3 3 3 3 3 3 3 3 3 3 3 3 3 该 该 该 该 该 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 该 该 该In the second part, the first, the through, and the spring are located between the first portion and the second portion. The dome is in the first through hole and the second through hole, the first hole And a second portion, wherein the second through hole corresponds to the second portion. (10) The first portion and the second portion are electrically connected to the through hole of the $including the conductive member. 1. The singer is better than the one. The conductive element is made of a transparent conductive material. The lean, t aa conductive material is selected from the group consisting of indium tin oxide, indium zinc oxide, and oxygen. The instant group of the hybrid gallium. The secret machine and the oxygen material--the manufacturing method of the liquid crystal display' include the following steps: =Iff on the substrate; forming - the data line intersects the gate line; "Γ the gate line; and forming - the second common The line traversing iL, ii preferably includes the following steps: forming a gate insulating layer over the first/, pass, and spring to form a passivation protective layer, the second common etched passivation protective layer Forming a first through hole and a second through hole, and the other is a good one, comprising the steps of: forming a conductive component, and the first through hole of the through hole is electrically connected to the second through hole. a line and the second common line. 7, 200825590. Preferably, the conductive element is made of _, the conductive material is selected from the group consisting of indium tin oxide material, and the zinc oxide is doped with gallium. The group consists of two groups of indium zinc, zinc oxide doped aluminum and two parts. The μ pin plate line comprises a - part and a preferred one, comprising the following steps: the hole and the second through hole are electrically connected f 兀, through the first nucleus - part and the second part. The filial piety is characterized in that the conductive element is selected from a group consisting of indium tin oxide and a material, and the zinc oxide is doped with gallium. Zinc-doped aluminum and the above-mentioned and other objects, and the preferred embodiments of the present invention are more apparent and easy to understand, and are in the field of display technology, and are described in detail below. The technical content and characteristics of the invention can be understood and understood by the knowledge of the invention. [Embodiment] FIG. 3 is an embodiment of the present invention, and the i-gold diagram earns H for its age: ^^ Schematic diagram of the structure of the prime structure, the fourth eye, the third figure, the structure of the halogen electrode includes: - gate line Μ, a data line line 30 / mouth one brother one direction configuration, and the data line 31 baht. I along a second direction configuration, and the second direction is approximately perpendicular to the first direction. The first common line & is parallel to the gate line 30, and the second common line 33 intersects the gate line 3A. 34 includes: a gate 340, a channel layer 34, a source 342, and a gate electrode. The gate 340 and the gate line 30 are electrically The source 342 is electrically connected to the data line 31, and the drain 343 is electrically connected to the pixel electrode 35 through the contact hole 36. The gate line 30, the first common line 32 and the gate 340 are exposed and developed. And a first metal layer is formed, and the data line 31, the second common line 33, the source 342 8 .200825590 light, the development, the Lai-second metal layer are formed. Between the fth metal layers, the first common line 32 is electrically connected to the conductive layer 37 by the tin π ,, the conductive element 37 ^ 〇 ΙΤ〇, 氧化), oxidized (5) "- zinc oxide miscellaneous ( Shi and the hidden ^ net wish (9) culvert) and ===u=p=; ^e) coffee cap material made a first 』, 3 common line above, and has a first through hole 381 two 1 brother one pass The hole 381 corresponds to the first common line 32, and the second-through hole 381·the second common line 33. Therefore, the conductive member 37 is transmitted through the first through line 33. One of the first through holes 382' is electrically connected to the first common line 32 and the second common supply == This is known to be ugly, and secondly, a closed pole 340, a gate line 30 and a first f are formed. It is approximately parallel to the gate line 30. Gate 340, _ line layer = the same as the first - metal layer, that is, by exposure, development, last name gate ίίο ίί 4i " t'f form a closed-pole insulation layer 42' to cover the gate 340, continued The layer one = formation again, the first common line 33, and the third electrode 343 formed next to the gate insulating layer 42 is located just above the channel layer 341. The data line layer, that is, the λ bungee 343 belongs to the same second metallic connection, which is formed by the second metal layer of the end 3, 5, 1 insect, the source 342 electric, and the ~ spring 1. 340, the channel layer 341, the source 342 and the drain 343 9 200825590 constitute the bonding film transistor 34. After the material line 3, the second common line 33, the source 342 and the gate 343, the substrate 4G is formed again - The protective layer 44 is passivated to cover the etched structure. Then, the passivation protective layer is further etched to the first via hole layer 44 corresponding to the first common line 32 to form a corresponding one. The second through hole π] of the common line 33 is 苴2; 7 is formed on the m protective layer 44 to form a conductive material made of a transparent conductive material; the first through hole 381 and the second through hole 382 are electrically connected. The first common common line 33. The conductive element 37 is made of a transparent conductive material such as indium tin oxide, indium zinc oxide, emulsified zinc doping, and zinc oxide doped gallium. Please read, 5 For the pixel structure of the present invention, the matrix layout is shown. The common line 32 and the second common line 33 are connected to each other through the conductive element 1. And together form a network structure to reduce the common-number delay effect. ECG Valley 7th, another reality of the invention, the schematic diagram of the layout of the elementary structure, the brother 7 is its line KK, Schematic diagram of the cross section - Figure 6 shows that the structure of the halogen includes: - gate line 6G, - data line 6 - 6 〇", pass: line 62, a second common line 63 and a thin film transistor 64. The gate line is arranged in the first direction, and the data line 61 is assigned 1 along a second direction, and the direction of the brother = is approximately perpendicular to the first direction. The first common line 62 is parallel to the second common line 63 and intersects the gate line 60. The thin film transistor 64 is enclosed in ". 2, 640, a channel layer 64, a source 642, and a immersed 6 milk. The gate electrode line 60 is electrically connected, and the source electrode 642 is electrically connected to the data line 61, and is electrically connected to the pixel electrode 65 through the contact hole 66. In the present embodiment, the gate line 60 is composed of a first portion 6〇1 and a 立八Ζ household. The second common line 63 traverses the gate line 6. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The brother-part 6〇1 and the second part 602 are connected by a conductive element 67, 200825590, which is adhered by indium tin oxide, indium zinc oxide, oxidized gallium, etc. _Zinc-doped wire 63 and gate 640 are formed by exposure, development, 1 total ^ ^ ^ and data line 6 source 642 and drain 643, then f ^ denier layer is formed by two pounds, two metal layers ·to make. The first portion 601 and the second portion 6 of the first through-hole 681 and a t-th as the seventh-pole line 60 are shown in the figure: the through-hole (8) and One by one ^ brother - the structure of the metal layer. And, on the gate insulating layer 72, ^泉63^64i' and on the surface of the channel layer 641, re-formed: the channel should be followed by the source 642 formed next and the upper == lean line 61 Formed on the gate insulating layer 72, the drain 643 is located just above the channel layer 641. The pole 642 and the pole (4) belong to the same second metal layer, and the gates are composed of f=2 and the unforced layer 64. The immersion (4) constitutes a thin film transistor 40 through tV/S?!^643^^^70 Next, the passivation protection structure is etched again. The second through hole 682. Next, a transparent guide is formed by a transparent guide from ITO a 应 弟 弟 邛 602 602 602 602 602 602 602 602 602 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. Among them, the conductive elements 67, ... 1 turn, zinc oxide (tetra) and A zinc-doped gallium are made of π 200825590 bright conductive material. „8, which is another book of the present invention' 63 of its matrix layout, through the conductive element 67 = the H-wire 62 is electrically connected to the second common line and is formed into a mesh structure to reduce commonality. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> < Desc/Clms Page number>> The scope of protection of the present invention is defined by the scope of the appended claims.
12 200825590 【圖式簡單說明】 第1圖為習知畫素結構之俯視示意圖； 第2圖為習知晝素結構矩陣之俯視示意圖； 第3圖為本發明之一實施例，其晝素結構之俯視示意圖； 第4圖為第3圖剖線i-r之剖面示意圖； 第5圖為第3圖之矩陣俯視示意圖； 第6圖為本發明之另一實施例，其晝素結構之俯視示意圖； •第7圖為第6圖剖線K-K，之剖面示意圖； 第8圖為第6圖之矩陣俯視示意圖。 雜 § 【主要元件符號說明】 10, 30, 60 閘極線 17 上電極 11，31，61資料線 32, 62 第一共通線 12, 34, 64薄膜電晶體 33, 63 第二共通線 120, 340, 640 閘極 37, 67 導電元件 121，341，641 通道看 381，681 第一通孔 122, 342, 642 源極 382, 682 第二通孔 123, 343, 643 汲極 40, 70 基板 13, 35, 65 晝素電極 42, 72 閘極絕緣層 14, 18, 36, 66 接觸窗口 44, 74 鈍化保護層 15 下電極 601 第一部分 16 儲存電容 602 第二部分 1312 200825590 [Simplified description of the drawings] Fig. 1 is a schematic plan view of a conventional pixel structure; Fig. 2 is a schematic plan view of a conventional matrix structure matrix; Fig. 3 is an embodiment of the present invention, and a pixel structure thereof 4 is a schematic cross-sectional view of a line ir of FIG. 3; FIG. 5 is a schematic plan view of a matrix of FIG. 3; FIG. 6 is a schematic plan view of a cell structure of another embodiment of the present invention; • Fig. 7 is a cross-sectional view taken along line KK of Fig. 6, and Fig. 8 is a schematic plan view of the matrix of Fig. 6. § [Major component symbol description] 10, 30, 60 gate line 17 upper electrode 11, 31, 61 data line 32, 62 first common line 12, 34, 64 thin film transistor 33, 63 second common line 120, 340, 640 gate 37, 67 conductive element 121, 341, 641 channel view 381, 681 first through hole 122, 342, 642 source 382, 682 second through hole 123, 343, 643 bungee 40, 70 substrate 13 , 35, 65 halogen electrode 42, 72 gate insulating layer 14, 18, 36, 66 contact window 44, 74 passivation protective layer 15 lower electrode 601 first part 16 storage capacitor 602 second part 13