200825589 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種顯示裝置，特別關於一種平面顯示 裝置。 【先前技術】 顯示技術的發展使得人們能夠輕易地由顯示裝置接 收各種不同的資訊，也因此豐富了人們的生活，亦加速了 資訊的傳遞速度。 請參照圖1所示，習知的一種平面顯示裝置；，例如液 晶顯示裝置，其係具有一液晶顯示面板1。液晶顯示面板 1主要係包括一晝素陣列11、一掃瞄線驅動迴路12以及 一資料線驅動迴路13。晝素陣列11係具有一玻璃基板Gw 及複數個設置於玻璃基板Gtn上之薄膜電晶體TFT^ ;掃 瞄線驅動迴路12係與薄膜電晶體TFT01之閘極電性連接； φ 資料線驅動迴路13係與薄膜電晶·體TFT01之源極電性連 接，以控制由薄膜電晶體TFT01所負責之晝素的透光率， 再配合紅綠藍三原色的搭配，以構成一影像圖框。其中， 掃瞄線驅動迴路12及資料線驅動迴路13係分別藉由複數 條掃目苗線（scan line)及複數條資料線（data line)而與晝 素陣列11電性連接。因此，該等掃瞄線及該等資料線需 要佈線於玻璃基板GG1上，然而，為了避免該等掃瞄線及 該等資料線影響液晶顯示面板1顯示影像的品質，故會利 用例如遮光陣列（black matrix )以作適當的遮蔽。因此， 6 200825589 遮光陣列將會降低部分的透光率，導致液晶顯示面板i的 開口率（aperture ratio)降低，而無法顯示最佳的影像效 果。 承上所述，因此，如何提供一種能夠增加開口率以提 高顯示影像之解析度的平面顯示裝置，實屬當前重要課題 之一0 【發明内容】 有鑑於上述課題，本發明之目的為提供一種具有較高 開口率的平面顯示裝置。 緣是，為達上述目的，依據本發明之一種平面顯示裝 置包含一基板、一像素電極陣列、一圖案化導電層、一輔 助圖案化金屬層以及一半導體電路單元。基板具有一第一 表面及與第一表面相對而設之一第二表面；像素電極陣列 及圖案化導電層係分別設置於基板之第一表面；輔助圖案 化導電層設置於第一表面與第二表面之間，並分別與像素 電極陣列及圖案化導電層電性連接；半導體電路單元具有 至少一輸入端及至少一輸出端’且輸出端係與圖案化導電 層電性連接。 為達上述目的，依據本發明之另一種平面顯示裝置包 含一基板、一像素電極陣列、一圖案化導電層、一輔助圖 案化導電層以及一半導體電路單元。基板係具有一第一表 面及與第一表面相對而設之一第二表面；像素電極陣列及 圖案化導電層係設置於基板之第一表面；辅助圖案化導電 7 200825589 廣設置於第二表面’並分別與像素電極_及 層電性連接；半導體電路單元具有至少—輸人端及 輸出端，且輸出端係與圖案化導電層電性連接。 ) 承上所述，因依據本發明之一種平面顯示裝置，盆 助圖案化導電層係設置於基板之第一表面鱼補 /、卑一^表面之 間，或係设置於基板的弟一表面，而像素電極陣列係透、尚 輔助圖案化導電層及圖案化導電層而與半導辦 " 一 ’歷電路單元 而200825589 IX. Description of the Invention: [Technical Field] The present invention relates to a display device, and more particularly to a flat display device. [Prior Art] The development of display technology has enabled people to easily receive various kinds of information from display devices, thereby enriching people's lives and speeding up the transmission of information. Referring to Fig. 1, a conventional flat display device; for example, a liquid crystal display device having a liquid crystal display panel 1. The liquid crystal display panel 1 mainly includes a pixel array 11, a scan line driving circuit 12, and a data line driving circuit 13. The halogen array 11 has a glass substrate Gw and a plurality of thin film transistor TFTs disposed on the glass substrate Gtn; the scan line driving circuit 12 is electrically connected to the gate of the thin film transistor TFT01; φ data line driving circuit The 13 series is electrically connected to the source of the thin film electro-crystal TFT 01 to control the transmittance of the halogen element which is responsible for the thin film transistor TFT01, and is matched with the red, green and blue primary colors to form an image frame. The scan line driving circuit 12 and the data line driving circuit 13 are electrically connected to the pixel array 11 by a plurality of scan lines and a plurality of data lines, respectively. Therefore, the scan lines and the data lines need to be wired on the glass substrate GG1. However, in order to prevent the scan lines and the data lines from affecting the quality of the image displayed on the liquid crystal display panel 1, for example, a light-shielding array is utilized. (black matrix) for proper shading. Therefore, the 6 200825589 shading array will reduce the partial transmittance, resulting in a lower aperture ratio of the liquid crystal display panel i, which does not show the best image effect. In view of the above, it is an object of the present invention to provide a flat display device capable of increasing the aperture ratio to improve the resolution of a display image. [Invention] In view of the above problems, an object of the present invention is to provide a A flat display device having a higher aperture ratio. To achieve the above object, a flat display device according to the present invention comprises a substrate, a pixel electrode array, a patterned conductive layer, an auxiliary patterned metal layer, and a semiconductor circuit unit. The substrate has a first surface and a second surface opposite to the first surface; the pixel electrode array and the patterned conductive layer are respectively disposed on the first surface of the substrate; the auxiliary patterned conductive layer is disposed on the first surface and the first surface Between the two surfaces, and electrically connected to the pixel electrode array and the patterned conductive layer respectively; the semiconductor circuit unit has at least one input end and at least one output end ′ and the output end is electrically connected to the patterned conductive layer. To achieve the above object, another flat display device according to the present invention comprises a substrate, a pixel electrode array, a patterned conductive layer, an auxiliary patterned conductive layer, and a semiconductor circuit unit. The substrate has a first surface and a second surface opposite to the first surface; the pixel electrode array and the patterned conductive layer are disposed on the first surface of the substrate; the auxiliary patterned conductive layer 7 200825589 is disposed on the second surface And electrically connected to the pixel electrode _ and the layer respectively; the semiconductor circuit unit has at least an input end and an output end, and the output end is electrically connected to the patterned conductive layer. According to the above, according to a flat display device according to the present invention, the pot-assisted patterned conductive layer is disposed between the surface of the first surface of the substrate, or between the surface of the substrate, or is disposed on the surface of the substrate. And the pixel electrode array is transparent, and the auxiliary patterned conductive layer and the patterned conductive layer are combined with the semiconductor device
電性連接。因此像素電極陣列可完全作為顯示面之用 不會損失開口率。 【實施方式】 以下將參照相關圖式’說明依據本發明較佳實施例之 一種平面顯示裝置。 ' 請參照圖2所示，依據本發明第一實施例之一種平面 顯示裝置2係包括一基板21、一像素電極陣列22、一圖 案化導電層23、一輔助圖案化導電層24以及一半導體電 路單元25。其中平面顯示裝置2例如但不限於電泳 (electrophoresis )顯不裝置、電濕（electrowetting )顯示 裝置或戶外顯示看板。 基板21具有一第一表面211及一第二表面212,其中 第一表面211係與第二表面212相對而設。於本實施例 中，基板21係可為一印刷電路板（printed circuit board, PCB)，其係可馬雙面板或多層板，於此並不加以限定。當 然，基板21亦可為一軟性電路板（flexible printed circuit， 200825589 FPC) 〇 #像素電極陣列22及圖案化導電層23似置於基板21 之第表面211。其中’像素電極陣列22係由複數個電極 以陣列排列設置於基板21之第一表面211。於本實施例 中’像素電極陣列221質係為 導電材料，其可為金屬 _如為_氧化物的透明導電材，於此並不加以限制。 另，圖案化導f層23之材質亦係可為金屬或例如為姻 • 錫氧化物的透明導電材，於此亦不加以限制。值得一提的 疋’於本貫施例中’各電極係可電性連接至一薄膜電晶體 (圖中未顯示）。 辅助圖案化導電層24係設置於基板21之第一表面 211與第二表面212之間，並至少與像素電極陣列22及圖 案化導電層23之一部分電性連接。於本實施例中，無論 基板21係為雙層板或多層板，設置於基板21之第一表面 211及第二表面212.之間用以電性連接像素電極陣列22及 φ 圖案化導電層23之導電線皆可稱之為輔助圖案化導電層 24 〇 半導體電路單元25係設置於基板21之第一表面211 _ 之上，並具有至少一輸入端251及至少一輸出端252，其 中，輸出端252係與至少一部份之圖案化導電層23電性 連接，當然輸入端251亦可與至少一部份圖案化導電層23 電性連接。於本實施例中，半導體電路單元25例如係為 夕工^§ ( MUX ) ’其係可為一晶片（chip )。當然，半導 體電路單元25亦可由一例如為玻璃基板之透明基板及一 200825589 集積迴路（integrated circuit)所構成。复由 &…、 ’、τ茱積迴路係直 接形成於透明基板之-表面上，且集積迴路係 電層23相對設置並與其電性連接。 ’、 2參照圖3所示’於本實施例中，平面顯以置^ 匕括一對向電極單兀26、一光電顯示單元 電路板28。 从及-軟性 對向電極單元26係與像素電極陣列22相對而哎。於 本實施例中，對向電極單元26係可為—電極層^電極 板’意即，對向電極單元26可直接形成於光電顯示單元 27上或是預先形成後再與光電顯示單元27結合。另外， 由於對向電極單元26須為透明，因此其㈣可為姻錫氧 化物、鋁鋅氧化物、銦鋅氧化物或鎘錫氧化物。 光電顯示單元27係設置於對向電極單元26盘像素電 ，車列22之間。其中、，光電顯示單元27可以依照設計需 ，而以光電顯示元件或光電顯示薄膜的形式呈 與 施财，光電齡單元27依財_設計所 包括一電泳性材料或一電濕性材料。 軟性電路板28係與半導體電路單元乃之輪入p 電性連接。於本實施射，軟性電路板28係透過而八1 圖案化導電層23而與半導體電路單元25之輸人端^之 性連接。於此，軟性電路板28德至少訊號^ 至例如為多工ϋ之半導體電路單元25，再由铸體電^ 元25將驅動訊號分別經由部分之圖案化導電層2 = 至像素電極陣列22。 輪 200825589 值得注意的是，半導體電路單元25亦可以些微位移 之方式設置於基板21上之圖案化導電層23上（圖中未 示），換言之，半導體電路單元25係有部分突出於基板21， 如此一來，軟性電路板28係可直接電性連接於半導體電 路單元25之輸入端251。 請參照圖4所示，依據本發明第二實施例之一種平面 顯示裝置3係包括一基板31、一像素電極陣列32、一圖 案化導電層33、一輔助圖案化導電層34、一半導體電路 單元35。 與第一實施例不同的是，辅助圖案化導電層34係設 置於基板31之一第二表面312，並穿過基板31而分別與 設置於基板31之一弟一表面311的像素電極陣列3 2及圖 案化導電層33電性連接。於本實施例中，辅助圖案化導 電層34係經由設置於基板31之至少一貫孔而與像素電極 陣列32及圖案化導電層33電性連接。與上述實施例相同 的，無論基板31係為雙層板或多層板，設置於基板31之 第一表面311及第二表面312之間用以電性連接像素電極 陣列32及圖案化導電層33之導電線皆可稱之為輔助圖案 化導電層34。 另外，請參照圖5所示，於本實施例中，平面顯示裝 置3亦可包括一對向電極單元36、一光電顯示單元37以 及一軟性電路板38 ’其與第一實施例之對向電極單元26、 光電顯示單元27以及軟性電路板28具有相同結構及連結 關係，故於此不再多加贅述。 11 200825589 以下請參照圖6A與圖6B所示，以說明第一實施例及 第二實施例之另一態樣的平面顯示裝置。 如圖6A所示，平面顯示裝置2’係包括一基板21’、一 像素電極陣列22’、一圖案化導電層23’、一辅助圖案化導 電層24’、一半導體電路單元25’、一對向電極單元26,以 及一光電顯示單元27’。其中，與第一實施例不同的是， 半導體電路單元25’係包括一薄膜F01及一晶片C01，其 係以晶粒軟膜技術（chip on film，COF)將晶片C01設置 於薄膜F01上，且晶片C01係藉由薄膜f〇1而與至少一部 份之圖案化導電層23’電性連接。於本實施例中，晶片c〇i 之態樣亦可為由一例如為玻璃基板之透明基板及一集積 迴路所構成。其中集積迴路係直接形成於透明基板之一表 面上，再藉由薄膜F01而與圖案化導電層23,電性連接。 請參照圖6B所示，平面顯示裝置3,係包括一基板 31’、一像素電極陣列32’、一圖案化導電層33,、一辅助 圖案化導電層34’、一半導體電路單元％，、一對向電極單 元36,及-光電顯示單元37，。其中’與第二實施例不同 的是，半導體電路單元35’係純—該m及一 C11。與上述相同’其係以晶粒軟膜技術（chip 此 COP)將晶片⑶設置於薄膜Fu±，且晶片c 由 薄膜m而與至少一部份之圖案化導電層33，電性= 於本貫施例中’晶片C11之態揭 板之透明基板及-集積迴.路所構^ 壯為破璃基 形成於透明基板之-表面上，再藉由薄膜F11而與== 12 200825589 導電層33’電性連接。 综上所述，因依據本發明之一種平面顯示裝置，其輔 助圖案化導電層係設置於基板之第一表面與第二表面之 — 間，或係設置於基板的第二表面，而像素電極陣列係透過 • 輔助圖案化導電層及圖案化導電層而與半導體電路單元 電性連接。因此像素電極陣列所對應的光電顯示單元可完 全作為顯示面之用，而不會損失開口率。 以上所述僅為舉例性，而非為限制性者。任何未脫離’ ⑩ 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】. 圖1為顯示習知之一種平面顯示面板之一示意圖； 圖2為顯示依據本發明第一實施例之一種平面顯示裝 置之一示意圖； I 圖3為顯示依據本發明第一實施例之一種平面顯示裝 置之另一示意圖； * 圖4為顯示依據本發明第二實施例之一種平面顯示裝 ’ 置之一示意圖； 圖5為顯示依據本發明第二實施例之一種平面顯示裝 置之另一示意圖； 圖6A為顯示依據本發明第一實施例之另一種平面顯 示裝置之一示意圖；以及 圖6B為顯示依據本發明第二實施例之另一種平面顯 13 200825589 示裝置之一示意圖。 元件符號說明： I :平面顯示面板 II :晝素陣列 12 :掃瞄線驅動迴路 13 :資料線驅動迴路 2、2’、3、3’ ：平面顯示裝置 21、 21’、31、31’ ：基板 211、 311 :第一表面 212、 312 :第二表面 22、 22’、32、32’ ：像素電極陣列 23、 23’、33、33’ ：圖案化導電層 24、 24’、34、34’ ：辅助圖案化導電層 25、 25’、35、35’ ：半導體電路單元 251、 351 :輸入端 252、 352 :輸出端 26、 26,、36、36’ ··對向電極單元 27、 27’、37、37’ ··光電顯示單元 28、 38 :軟性電路板 C01、C11 :晶片 F01、F11 :薄膜 G〇i :玻璃基板 TFT01 :薄膜電晶體Electrical connection. Therefore, the pixel electrode array can be used completely as a display surface without losing the aperture ratio. [Embodiment] Hereinafter, a flat display device according to a preferred embodiment of the present invention will be described with reference to the related drawings. Referring to FIG. 2, a flat display device 2 according to a first embodiment of the present invention includes a substrate 21, a pixel electrode array 22, a patterned conductive layer 23, an auxiliary patterned conductive layer 24, and a semiconductor. Circuit unit 25. The flat display device 2 is, for example but not limited to, an electrophoresis display device, an electrowetting display device, or an outdoor display kanban. The substrate 21 has a first surface 211 and a second surface 212, wherein the first surface 211 is opposite to the second surface 212. In this embodiment, the substrate 21 can be a printed circuit board (PCB), which is a double-panel or multi-layer board, which is not limited herein. Of course, the substrate 21 can also be a flexible printed circuit (200825589 FPC). The pixel electrode array 22 and the patterned conductive layer 23 are disposed on the first surface 211 of the substrate 21. The 'pixel electrode array 22' is disposed on the first surface 211 of the substrate 21 in an array by a plurality of electrodes. In the present embodiment, the pixel electrode array 221 is made of a conductive material, which may be a metal-based transparent conductive material, which is not limited herein. Further, the material of the patterned conductive layer 23 may be a metal or a transparent conductive material such as a tin oxide, and is not limited thereto. It is worth mentioning that in each of the embodiments, the electrodes are electrically connected to a thin film transistor (not shown). The auxiliary patterned conductive layer 24 is disposed between the first surface 211 and the second surface 212 of the substrate 21 and electrically connected to at least one of the pixel electrode array 22 and the patterned conductive layer 23. In this embodiment, the substrate 21 is a double-layered or multi-layered board, and is disposed between the first surface 211 and the second surface 212 of the substrate 21 for electrically connecting the pixel electrode array 22 and the φ patterned conductive layer. The conductive line of the second embodiment can be referred to as an auxiliary patterned conductive layer 24. The semiconductor circuit unit 25 is disposed on the first surface 211 _ of the substrate 21 and has at least one input end 251 and at least one output end 252. The output end 252 is electrically connected to at least a portion of the patterned conductive layer 23 . Of course, the input end 251 can also be electrically connected to at least a portion of the patterned conductive layer 23 . In the present embodiment, the semiconductor circuit unit 25 is, for example, a semiconductor device (MUX), which may be a chip. Of course, the semiconductor circuit unit 25 can also be composed of a transparent substrate such as a glass substrate and a 200825589 integrated circuit. The complex &..., ', τ accumulation circuit is formed directly on the surface of the transparent substrate, and the accumulation circuit electrical layer 23 is oppositely disposed and electrically connected thereto. Referring to Fig. 3, in the present embodiment, a planar display unit includes a pair of electrode units 26 and an optoelectronic display unit circuit board 28. The AND-soft opposite electrode unit 26 is opposed to the pixel electrode array 22. In the present embodiment, the opposite electrode unit 26 can be an electrode layer or an electrode plate. That is, the opposite electrode unit 26 can be directly formed on the photoelectric display unit 27 or can be combined with the photoelectric display unit 27 after being formed in advance. . Further, since the counter electrode unit 26 is required to be transparent, the (4) may be an agglomerated tin oxide, an aluminum zinc oxide, an indium zinc oxide or a cadmium tin oxide. The photoelectric display unit 27 is disposed between the counter electrode unit 26 and the pixel row 22 between the trains. Wherein, the photoelectric display unit 27 can be in the form of a photoelectric display element or a photoelectric display film according to design requirements, and the photoelectric age unit 27 includes an electrophoretic material or an electrowetting material. The flexible circuit board 28 is electrically connected to the semiconductor circuit unit. In the present embodiment, the flexible circuit board 28 is transparently connected to the input end of the semiconductor circuit unit 25 by the eight-patterned conductive layer 23. Here, the flexible circuit board 28 is at least signaled to, for example, the multiplexed semiconductor circuit unit 25, and the driving circuit 25 then drives the driving signals through the partially patterned conductive layer 2 = to the pixel electrode array 22, respectively. It is to be noted that the semiconductor circuit unit 25 can also be disposed on the patterned conductive layer 23 on the substrate 21 (not shown) in a slight displacement manner. In other words, the semiconductor circuit unit 25 partially protrudes from the substrate 21, In this way, the flexible circuit board 28 can be directly electrically connected to the input end 251 of the semiconductor circuit unit 25. Referring to FIG. 4, a flat display device 3 according to a second embodiment of the present invention includes a substrate 31, a pixel electrode array 32, a patterned conductive layer 33, an auxiliary patterned conductive layer 34, and a semiconductor circuit. Unit 35. Different from the first embodiment, the auxiliary patterned conductive layer 34 is disposed on one of the second surfaces 312 of the substrate 31 and passes through the substrate 31 and respectively disposed on the pixel electrode array 3 disposed on the surface 311 of the substrate 31. 2 and the patterned conductive layer 33 is electrically connected. In the present embodiment, the auxiliary patterned conductive layer 34 is electrically connected to the pixel electrode array 32 and the patterned conductive layer 33 via at least a uniform hole provided in the substrate 31. The substrate 31 is disposed between the first surface 311 and the second surface 312 of the substrate 31 for electrically connecting the pixel electrode array 32 and the patterned conductive layer 33, which is the same as the above embodiment. The conductive lines may be referred to as auxiliary patterned conductive layers 34. In addition, as shown in FIG. 5, in the embodiment, the flat display device 3 may further include a pair of electrode units 36, a photoelectric display unit 37, and a flexible circuit board 38' which are opposite to the first embodiment. The electrode unit 26, the optoelectronic display unit 27, and the flexible circuit board 28 have the same structure and connection relationship, and thus will not be further described herein. 11 200825589 Hereinafter, a flat display device according to another embodiment of the first embodiment and the second embodiment will be described with reference to Figs. 6A and 6B. As shown in FIG. 6A, the flat display device 2' includes a substrate 21', a pixel electrode array 22', a patterned conductive layer 23', an auxiliary patterned conductive layer 24', a semiconductor circuit unit 25', and a The opposite electrode unit 26, and an optoelectronic display unit 27'. The difference between the first embodiment and the first embodiment is that the semiconductor circuit unit 25 ′ includes a film F01 and a wafer C01, and the chip C01 is disposed on the film F01 by chip on film (COF). The wafer C01 is electrically connected to at least a portion of the patterned conductive layer 23' by the film f〇1. In this embodiment, the wafer c〇i may be formed of a transparent substrate such as a glass substrate and an accumulation circuit. The accumulation circuit is formed directly on one surface of the transparent substrate, and is electrically connected to the patterned conductive layer 23 by the film F01. Referring to FIG. 6B, the flat display device 3 includes a substrate 31', a pixel electrode array 32', a patterned conductive layer 33, an auxiliary patterned conductive layer 34', a semiconductor circuit unit%, A pair of electrode units 36, and - a photoelectric display unit 37. Wherein 'different from the second embodiment, the semiconductor circuit unit 35' is pure - the m and a C11. Same as above', the wafer (3) is placed on the film Fu± by the chip soft film technology (chip COP), and the wafer c is formed by the film m and at least a portion of the patterned conductive layer 33, and the electrical property is normal. In the example, the transparent substrate of the wafer C11 is uncovered, and the accumulation of the substrate is formed on the surface of the transparent substrate, and then by the film F11 and == 12 200825589 conductive layer 33 'Electrical connection. In summary, according to the flat display device of the present invention, the auxiliary patterned conductive layer is disposed between the first surface and the second surface of the substrate, or is disposed on the second surface of the substrate, and the pixel electrode The array is electrically connected to the semiconductor circuit unit through the auxiliary patterned conductive layer and the patterned conductive layer. Therefore, the photoelectric display unit corresponding to the pixel electrode array can be used as the display surface completely without losing the aperture ratio. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional flat display panel; FIG. 2 is a schematic view showing a flat display device according to a first embodiment of the present invention; FIG. 4 is a schematic view showing a flat display device according to a second embodiment of the present invention; FIG. 5 is a plan view showing a flat display device according to a second embodiment of the present invention; FIG. 6A is a schematic view showing another flat display device according to a first embodiment of the present invention; and FIG. 6B is a view showing another flat display 13 200825589 device according to the second embodiment of the present invention. A schematic diagram. Description of component symbols: I: Flat display panel II: Alizarin array 12: Scanning line drive circuit 13: Data line drive circuit 2, 2', 3, 3': Flat display devices 21, 21', 31, 31': Substrate 211, 311: first surface 212, 312: second surface 22, 22', 32, 32': pixel electrode array 23, 23', 33, 33': patterned conductive layer 24, 24', 34, 34 ' : Auxiliary patterned conductive layer 25, 25', 35, 35': semiconductor circuit unit 251, 351: input terminals 252, 352: output terminals 26, 26, 36, 36' · counter electrode unit 27, 27 ', 37, 37' ··Photoelectric display unit 28, 38: flexible circuit board C01, C11: wafer F01, F11: film G〇i: glass substrate TFT01: thin film transistor