TW200824058A - Semiconductor element mounting member, semiconductor device, imaging device, light emitting diode constituting member, and light emitting diode - Google Patents

Semiconductor element mounting member, semiconductor device, imaging device, light emitting diode constituting member, and light emitting diode Download PDF

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Publication number
TW200824058A
TW200824058A TW096143369A TW96143369A TW200824058A TW 200824058 A TW200824058 A TW 200824058A TW 096143369 A TW096143369 A TW 096143369A TW 96143369 A TW96143369 A TW 96143369A TW 200824058 A TW200824058 A TW 200824058A
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TW
Taiwan
Prior art keywords
semiconductor element
hole
semiconductor
light
layer
Prior art date
Application number
TW096143369A
Other languages
Chinese (zh)
Other versions
TWI326483B (en
Inventor
Kenjiro Higaki
Daisuke Takagi
Sadamu Ishidu
Yasushi Tsuzuki
Original Assignee
Almt Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Almt Corp filed Critical Almt Corp
Publication of TW200824058A publication Critical patent/TW200824058A/en
Application granted granted Critical
Publication of TWI326483B publication Critical patent/TWI326483B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Led Device Packages (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A collective substrate (1) is produced by firing a ceramic green sheet and forming through-holes (11) in the resulting substrate. The through-holes (11) each have an interior surface including taper surfaces (11b, 11c) which are tapered as having an opening size progressively decreasing from a main surface (21) and an external connection surface (22) toward a minimum size hole portion (11a). The taper surfaces (11b, 11c) respectively form obtuse angles θ1, &thgr2 with the main surface (21) and the external connection surface (22). A semiconductor element mount (BL) includes an insulative member (2) cut out of the collective substrate (1). An imaging device (PE2) includes an imaging element (PE1) mounted in a region surrounded by a frame (4) which is bonded to the main surface (21) of the insulative member (2) and closed by a cover (FL). A light emitting diode component (LE2) includes a light emitting element (LE1) mounted on the main surface (21) of the insulative member (2) with the minimum size hole portion (11a) of the through-hole being filled with an electrically conductive material (33a), the light emitting element being sealed with a fluorescent material and/or a protective resin (FR). A light emitting diode (LE3) includes the light emitting diode component (LE2) mounted in a package (7).

Description

200824058 九、發明說明: 【發明所屬之技術領域】 本發明係關於將複數板狀絕緣構件在同姊200824058 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to the simultaneous application of a plurality of plate-shaped insulating members

V 莞製集合基板;由分割上述集合基板: 3的構件所形成的半導體元件搭載構件;由上述 載構件所形成的攝像裝置、發光二極體構成 以及由上述發光二極體構成構件所形 戚的發光二極體。 【先前技術】 近年,隨數位相機、照相手機的普 等攝像元件的需求正急遽擴=為因 的傾向,特元:之像素數 大料令尸 平口目械的曰及,亦朝攝像元件的 旦日展。此外,近年在發光元件方面,因為已可大光 =先且可組合榮光體等而發出白色光,因而上述照相手 2閃先燈等,便廣泛·採用發光元件的發光 出以為:=Γ元件、發光元件等半導體元件的高輸 古散埶1 充分發揮,對使用具有由例如副等 2熱'__構成平板狀料構件的 ==隨之增加。上述半導體元件搭载構件』 面單面’設定為供半導體元件搭載用的主 L而將背面狀為供連接於其他構件用的外部連接面, 隸ΐ面上形成半導體元件搭載用的複數電極層,在外部 連接面上形成與其他構件間之連接用的複數電極層,更將 326\總檔\94\94145509VTF968049 200824058 極層,藉由在貫通絕緣構件的複數貫通孔内a V-made collective substrate; a semiconductor element mounting member formed by dividing the member of the collective substrate 3; an imaging device formed of the carrier member, a light-emitting diode, and a member formed of the light-emitting diode. Light-emitting diode. [Prior Art] In recent years, the demand for video components such as digital cameras and camera phones is rapidly expanding. The trend is that the number of pixels is large, and the number of pixels is the same as that of the camera. Day exhibition. In addition, in recent years, in terms of a light-emitting element, since white light can be emitted by a large light=first and a combination of a glare body or the like, the above-mentioned camera 2 flashing lamp or the like is widely used, and the light-emitting element is widely used as follows: The high-transmission and dispersion of the semiconductor element such as a light-emitting element is fully exerted, and the use of == which constitutes a flat material member by, for example, a secondary heat 2__ increases. In the semiconductor element mounting member, the surface of one surface is set to the main L for mounting the semiconductor element, and the back surface is connected to the external connection surface for the other member, and the plurality of electrode layers for mounting the semiconductor element are formed on the surface. A plurality of electrode layers for connection to other members are formed on the external connection surface, and the 326\total file\94\94145509VTF968049 200824058 pole layer is formed in a plurality of through holes penetrating the insulating member

VV

卜、f主道-|曰孔¥體專,形成個別連接的構造。 上述+¥體元件搭载構件習知—般使I 體的陶瓷胚片,再利用所神Μ 稱仵則駆 參照專彳9 共燒(⑽re)法製造(例如 缘構件外开/的;。換…將陶瓷胚片形成對應於絕 f構件㈣的平面形狀,且在其既定位置處形成貫通 日士馇έ士品氺人 ductor),將與陶瓷胚片同 ‘而成"層孔導體料電性膏,填充於貫通孔中後 將陶瓷胚片與導電性膏同時 載構件。 了π風便了衣侍+導體元件搭 再者,例如在已形成既定平面形狀的陶竟胚片 1 ^緣構件主面、及將成為外部連接面之—面上,將導電性 :印刷或塗佈成對應電極層形狀的既定平面形狀,並陶 究胚片燒成之同時亦燒結㈣成基底金屬層之後,再於 述基底金屬層上利用鍍金屬層的積層,而形成上述主面盥 外部連接面的電極層。 /、 專利文獻1:日本專利特開平u_1359〇6號公報 專利文獻2:曰本專利特開2002-232017號公報 【發明内容】 (發明所欲解決之問題) ♦ 但是,為利用共燒法一個個製造半導體元件搭载構件, V有生產性降低且製造成本提高的問題。所以,便有探討 複數板狀絕緣構件在同一平面上一體形成排列形狀的陶 瓷製集合基板,依照上述共燒法形成之後,再利用切^ 326\總檔\94\94145509\TF968049 , 200824058 二D:c:ng)等方式为蚵上述集合基板成各個區域 =、!緣構件等技術。但是,包含複數絕緣構件之區: =陶成時的收縮量較大,且整體無法 出】:ί二ί 的問題。例如矩形狀陶究胚片 二近較矩形角落大幅朝内側收縮的現象。 形成絕緣構件的複數個區域整赢=排=各^的貫通孔 成時的收縮而造成貫通孔二正二態:仍因燒 而出現難以從所形成的隼Υ 夕之^兄’因 Λ J木口基扳,利用切割等方3公剑夂 題::斤以,、為使各區域未呈整齊排列之狀態下, 收縮而發二態:有考慮事先預估因 較寬,但是 ==;== 成的區域數減少,而有材料浪費較多的問題。 片有探討將包含複數絕緣構件之區域的大陶兗胚 、、先成,而形成一片集合基板,並在上 =絕緣構件的複數區域,對各區‘ +、貝l孔之後,再依各區域分割而製造絕緣構件。在上 ΓϋΓ於絕緣構件的主面侧及外部連接面侧,分別利 匕:讀、電解電鍍等施行形成電極層的步驟之同時 電:)導:形成的貫通孔内面金屬化’俾形成連接二 ,^利用雷射加工所形成的貫通孔,因為形成從雷射 、貝1起朝射出側,直徑逐漸變小的推拔狀,因而在雷射 326\|ii|\94\94145509\TF968049 ? 200824058 射出側之面,上述面與貫通孔内面以銳角相交,又因為 叙角相父的角落部分,利用物理蒸鑛、印刷、電鑛等方式 所形成的金屬化密接性較弱,且膜厚容易呈不均勾狀態, 口而在、.巴緣構件上形成電極層、導電層之際,出現電極声 與導電層間之連接不良等問題。 θ 本么明之目的在於提供—種集合基板,在陶莞胚片燒成 之後再ι由形成貫通孔的步驟而製造,可將上述貫 =所形成的導電層、與主面或外部連接面上所形成的電極 “’在不致發生連接+良等情況下確實連接。㈣,本發 明^的在於提供-種㈣分割上述集合基板成各區域天 而件之絕緣構件,所形成的半導體元件搭載構件,以及使 2述半導體元件搭載構件所形成的攝像裝置、發光二極 f構成構件等半導體褒置,暨使用上述發光二極體構成構 件所开> 成的發光二極體。 (解決問題之手段) 件^達成ϋ目的,本發明之#合基板將複數板狀絕緣構 八早面,又疋為半導體元件搭載用主面,而背面則設定 為與其他構件間連接用的外部連接面),利用陶莞在同一 ㈣成整齊排列形狀’並至少在各個成為絕緣構 件之區域内的既定位置、或於揣 邊界線的位置等二者之外侧區域之 =貫通孔’且將各貫通孔的内面形成從上述== 錢接面側開口,朝向絕緣構件厚度方向之一處所設置 最小孔部’分別形成開口尺寸逐漸變小的推拔狀。此外, 326\總槍\94\94145509卿968049 8 200824058 上述本發明的集合基板之熱導率最好為雨/mK以上 熱膨脹係數最好在10><10-7。〇以下。另外,上述本發 集合基板最好在將其母材的板狀前驅體燒成之後, v 貫通孔而製造。另外,本發明的集合基板最好具備有〔 導體元件搭載用電極層(其形成於成為絕緣構件之區域的 主面側)、連接用電極層(其形成於外部連接面侧且供鱼並 他構件間連接用)、以及導電層(其形成於貫通孔内,且連 ^接主面側電極層與外部連接面側電極層)。 ^發明的半導體元件搭載構件係將具備有上述電極層 及導電層的本發明集合基板,依各區域分割而製得。上^ 導Γ件搭載構件,最好其外部連接面之電極 層取表面至少其中部分由Au所形成。 再者’上述本發明的半導體元件搭载構件最好主面具備 有:设定有半導體元件搭載用區域的絕緣構件,以及在上 =面上依包圍上述區域之方式積層的框體;上述絕緣構 =框體的熱膨脹係數均在10χ1〇_6/ΐ以下,且框體的熱 知脹係數與絕緣構件的熱膨脹係數之差最好在㈣6厂◦ Ζ °此外,上述本發明的半導體元件搭載構件,絕緣構 上由框體所包圍供半導體元件搭載用區域的面積 内的^上’取好由至少包含半導體元件搭載用電極層在 内的金屬層所覆蓋。 哉明的攝像裝置具備有:上述本發明的半導體元件搭 r緩;^生攝像70件(其搭載於上述半導體元件搭載構件之 構件主面上,且由框體所包圍的區域中)、以及蓋體 326\總槍\94\94145509VTF968049 〇 200824058 (其在上述框體上面 材所構成)。 為密閉框體而接合,且由透光性板 ‘再者,本發明的半導體裝置具備有··上述本發明的半導 、體元件搭载構件、及半導體元件(其搭載於上述半導體元 件ί載構件中之絕緣構件主面上),且上述半導體元件利 用密封材密封。 再者’本發明的半導體裝置具備上述電極層及導電層, 同時將貫通孔的最小孔部利用形成導電層的導電材料填 -滿,亚在將上述貫通孔朝厚度方向封閉的集合基板中,成 為各個絕緣構件的區域主面上,搭载有半導體元件,Α 次三將上述集合基板搭載有半導體元件的主面側整面,利 用山封材在封之後,再將上述集合基板與密封材一起依各 區域分割而製得,並使分割後的貫通孔之至少其中一部 分,與絕緣構件之主面及外部連接面相交叉之側面呈開放 _ 士本發明的發光二極體構成構件係上述本發明的半導體 衣置中纟半$體元件為發光元件,且密封材至少為勞光 體或保護樹脂中之-者。此外,上述本發明的發光二極體 構成構件,取好其絕緣構件主面的電極層最表面至少其中 一部分’由Ag、Α1或A1合金所形成。此夕卜本發明㈣ 光二極體具備有:封裝(其具有凹部)、上述本發明的發光 一 2體構成構件(其搭載於上述封裝的凹部之底面上)、以 及密封覆蓋或透鏡(其在凹部開口中,為密閉上述凹部而 接口且由可使來自發光二極體構成構件的光穿透過的材 326\||^\94\94145509\TF968049 10 200824058 料所構成)。 (發明效果) 本發明的集合基板中’因為形成貫通孔的内面,從絕緣 構件主面侧及外部連接面側的開口起,朝向在絕緣構件厚 度方向1個地方所設置最小孔部,分別形成開口尺寸逐漸 艾小的推拔狀,因而形成上述主面及外部連接面、與貫通 孔内面,任一面側均以鈍角相交。故,依照本發明的集合 f板,當利用物理蒸鍍、印刷、電鍍等方式形成電極層、 導電層之際,可大幅降低角部的金屬化剝落、膜厚不均勺 狀=、,俾使電極層與導電層不致發生連接不良等狀況,可 確貫連接,較目前更加提升半導體裝置的可靠度。 再者,將上述本發明集合基板的熱導率設定在丨⑽/祕 2 m半導體元件搭載構件的散熱性,俾可因應半 V月豆元件的高輸出化。此外,將华合板 μ 基板的熱膨脹係數設 疋在10x10 /C以下,可確實防止當因 * ^ ^ ^ ^ ne 70仟驅動日守的熱效 =夺而,“脹、收縮之際,對半導體元件施加過大應 接人m 次與包極層間的接合移位而發生 接合不良狀況等等情形。 ※王 义再者,上述本發明集合基板將其母材的陶 别驅體燒成之後,再形成貫通孔而製造 、片 二均寻收縮,而發生貫通孔位置偏移 …、需事先預估因收縮所產生的位 ' =冓件的區域之形成間隔設定為較寬,:二 基板上形成的區域數,且可減少材料浪# /加早片集合 326\||it\94\94145509\TF968049 π 200824058 再者,在本發明集合基板的絕緣構件主面與外部連接面 上,形成電極層,且在貫通孔内面形成導電層,可將上述 .电極層與導電層在不致發生連接不良n兄下,確實連 、·接。故,依照對上述本發明集合基板依各區域分割而製得 的本發明半導體元件搭載構件,可將主面上所搭载的^導 體元件,透過上述二電極層與導電層,在不致發生連接不 良等情況下’確實與其他構件連接。此外,上述本發 ⑩^體元件搭載構件的外部連接面,其電極層最表面至少其 ,-部分形成’可將上述電極層利用焊料接合、 焊接搭線等習知周知各種連接方法,在與其他構件所:置 的電極層之間更確實導電連接。 在上述本發明半導體元件搭載構件的絕緣構件主面 上,設定供半導體元件搭載用的區域,且依包圍上述區先 =方式:在絕緣構件主面上積層有框體,並在上述區域」 搭載半導體元件之後,再於上述框體上接合蓋體,可將戶, ^載,半㈣元件密封。㈣當半導體元件為攝像元件 時’藉由使用由透光性材料所構成的蓋體,在攝像元件上 依可透過蓋體曝光的狀態,將上述攝像元件密封。 藉由將上述本發明半導體元件搭载構件的絕緣構件與 匡體之熱膨脹係數均設定在丨0xl〇-6/<3c以下,且 熱膨脹係數之差設定在3><1。-6/。。以下,可使框體的埶膨 脹係數接近絕緣構件’能防止二者的接合發生龜曲狀況: 且可防止因熱效應而發生接合不良等狀況。 彳 將上述本發明半導體元件搭载構件的絕緣構件主面 326聰檔 \94\94145509VIT968049 12 200824058 上,由框體所包圍出供半導體元件搭载用區域的面積8〇% 以上:利用至少包含半導體元件搭載用電極層在内的金屬 層後盘,例如當半導體元件為攝像元件時,可使上述金屬 層產生遮光層功能,將通過絕緣構件從攝像元件背後所入 射的光阻斷,可提升攝像元件感度。此外,當半導體元件 為發光元件時,可使上述金屬層產生反射層功能,俾可提 升發光二極體的發光效率。Bu, f main road - | 曰 hole ¥ body special, forming the structure of individual connections. In the above-mentioned +¥ body element mounting member, it is conventionally known that the ceramic body piece of the I body is used for the purpose of re-use the 胚 仵 駆 駆 駆 駆 共 共 共 共 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ...the ceramic green sheet is formed to correspond to the planar shape of the extinct member (four), and at the predetermined position thereof, a pendulum conductor is formed, which will be the same as the ceramic embryonic sheet. The electric paste is filled in the through hole, and the ceramic green sheet and the conductive paste are simultaneously loaded on the member. The π wind has the convenience of the clothing and the conductor element, for example, on the surface of the ceramic element 1 which is formed into a predetermined planar shape, and the surface which will become the external connection surface, the conductivity: printing or The main surface is formed by coating a predetermined planar shape corresponding to the shape of the electrode layer, and sintering the green sheet while sintering (4) to form the base metal layer, and then using the layer of the metal plating layer on the base metal layer. The electrode layer of the external connection surface. [Patent Document 1: Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. 2002-232017 [Patent Document] [Problems to be Solved by the Invention] ♦ However, in order to utilize the co-firing method When a semiconductor element mounting member is manufactured, V has a problem that productivity is lowered and manufacturing cost is improved. Therefore, there is a ceramic collective substrate in which a plurality of plate-shaped insulating members are integrally formed on the same plane, and formed according to the above-mentioned co-firing method, and then used to cut 326\total file\94\94145509\TF968049, 200824058 2D :c: ng) or the like is a technique in which the above-mentioned collective substrate is formed into respective regions =, ! However, the area containing a plurality of insulating members: = the amount of shrinkage when the ceramic is large, and the whole cannot be out]: ί 二ί. For example, the rectangular ceramic tile is nearly shrinking toward the inner side of the rectangular corner. The plurality of areas forming the insulating member are win-win = row = each hole of the through hole is contracted to cause the through hole to be two-normal two-state: still due to burning, it is difficult to form from the 夕 之 ^ ' ' The base plate, using the cutting and other side of the 3 male sword ::: 斤,, in order to make the areas are not neatly arranged, shrinking and sending two states: consider the prior estimate because of the wider, but ==; = The number of areas is reduced, and there is a problem of more material waste. The film has a large pottery embryo that will cover the area of the plurality of insulating members, and is formed into a collective substrate, and in the plural region of the upper = insulating member, after each region '+, the shell, the hole, and then The insulating member is manufactured by dividing the area. On the main surface side and the external connection surface side of the insulating member, respectively, the steps of forming the electrode layer by reading, electrolytic plating, etc. are simultaneously performed:): the inner surface of the through-hole formed is metallized to form a connection , ^ Through the through hole formed by the laser processing, because the formation of the laser from the laser, the shell 1 toward the exit side, the diameter gradually becomes smaller, so in the laser 326 \ | ii | \ 94 \ 94145509 \ TF968049 ? 200824058 The surface of the exit side, the above surface intersects the inner surface of the through hole at an acute angle, and because of the corner portion of the father of the corner, the metallization formed by physical distillation, printing, electric ore, etc. is weak, and the film thickness is weak. It is easy to be in an uneven state, and when the electrode layer and the conductive layer are formed on the edge of the bar member, problems such as poor connection between the electrode sound and the conductive layer occur. θ The purpose of the present invention is to provide a collective substrate, which is manufactured by the step of forming a through hole after firing the ceramic green sheet, and the conductive layer formed on the surface of the conductive layer and the main surface or the external connecting surface can be formed. The formed electrode "' is surely connected without causing connection + good or the like. (4) The present invention provides a semiconductor element mounting member which is formed by dividing the above-mentioned collective substrate into insulating members of the respective regions. And a semiconductor device such as an imaging device formed by the semiconductor element mounting member and a light-emitting diode f-constituting member, and a light-emitting diode formed by using the light-emitting diode constituent member. In view of the above, the #合板板 of the present invention has a plurality of plate-shaped insulating structures in the early morning, and is also used as a main surface for mounting semiconductor elements, and the back surface is set as an external connection surface for connection with other members. , using the side of the ceramics in the same (four) neatly arranged shape 'and at least in the area of each of the insulating members, or the position of the boundary line of the 揣, etc. In addition, the inner surface of each of the through holes is formed to open from the side of the above-mentioned == money junction side, and the minimum hole portion ' provided at one of the thickness directions of the insulating member is formed in a push-out shape in which the opening size is gradually reduced. 326\总枪\94\94145509卿 968049 8 200824058 The thermal conductivity of the collective substrate of the present invention is preferably rain/mK or higher, preferably 10/<10-7. 〇 or less. It is preferable that the collective substrate is produced by firing a plate-shaped precursor of the base material and then through-holes. The collective substrate of the present invention preferably includes an electrode layer for mounting a conductor element (which is formed as an insulating member). a main surface side of the region, a connection electrode layer (which is formed on the external connection surface side and used for connecting the fish and the member), and a conductive layer (which is formed in the through hole and connected to the main surface side electrode layer) The semiconductor element mounting member of the invention is obtained by dividing the semiconductor substrate mounting member of the present invention including the electrode layer and the conductive layer, and dividing the respective regions into regions. In the semiconductor element mounting member of the present invention, it is preferable that the surface of the electrode layer of the external connection surface is provided with an insulating member in which the semiconductor element mounting region is set, and on the upper surface. The frame is laminated on the surface so as to surround the above-mentioned area; the thermal expansion coefficient of the above-mentioned insulation = frame is less than 10χ1〇_6/ΐ, and the difference between the thermal expansion coefficient of the frame and the thermal expansion coefficient of the insulating member is best. In the semiconductor device mounting member of the present invention, the semiconductor element mounting member of the present invention is surrounded by the housing and is provided in the area for mounting the semiconductor element mounting region. The imaging device of the present invention is provided with the semiconductor device of the present invention described above, and the semiconductor device 70 is mounted on the main surface of the member of the semiconductor element mounting member, and is provided by the housing. In the enclosed area), and the cover 326\total gun\94\94145509VTF968049 〇200824058 (which is composed of the above-mentioned frame top material). In the semiconductor device of the present invention, the semiconductor device of the present invention includes the semiconductor device of the present invention, the semiconductor device mounting member, and the semiconductor device (which is mounted on the semiconductor device) The main surface of the insulating member in the member, and the above semiconductor element is sealed with a sealing material. Further, the semiconductor device of the present invention includes the electrode layer and the conductive layer, and the smallest hole portion of the through hole is filled with a conductive material forming a conductive layer, and is formed in a collective substrate in which the through hole is closed in the thickness direction. A semiconductor element is mounted on the main surface of each of the insulating members, and the entire surface of the main surface of the semiconductor element is mounted on the collective substrate, and the package is sealed with the sealing material after sealing with a mountain sealing material. According to the division of each region, at least a part of the divided through-holes are open to the side of the main surface and the external connection surface of the insulating member. The light-emitting diode constituent member of the present invention is the present invention. The semiconductor device is a light-emitting element, and the sealing material is at least a light-emitting body or a protective resin. Further, in the above-described light-emitting diode constituent member of the present invention, at least a part of the outermost surface of the electrode layer on the main surface of the insulating member is formed of Ag, Α1 or Al alloy. Further, the present invention (4) includes a package (having a concave portion), the above-described light-emitting member 2 of the present invention (which is mounted on the bottom surface of the concave portion of the package), and a sealing cover or lens (which is The recessed opening is formed by sealing the recessed portion and is made of a material 326\||^\94\94145509\TF968049 10 200824058 which can penetrate the light from the light-emitting diode constituent member. (Effect of the invention) In the collective substrate of the present invention, the inner surface of the through hole is formed, and the minimum hole portion is formed in one place in the thickness direction of the insulating member from the opening on the main surface side of the insulating member and the outer connecting surface side. Since the opening size is gradually reduced, the main surface and the outer connecting surface are formed, and the inner surface of the through hole is formed, and any one side faces at an obtuse angle. Therefore, according to the assembly f plate of the present invention, when the electrode layer and the conductive layer are formed by physical vapor deposition, printing, plating, or the like, the metallization peeling of the corner portion and the uneven thickness of the film thickness can be greatly reduced. The electrode layer and the conductive layer are not connected to each other, and the connection can be ensured, and the reliability of the semiconductor device is further improved. Further, the thermal conductivity of the above-described collective substrate of the present invention is set to the heat dissipation property of the 丨(10)/sec 2 m semiconductor element-mounted member, and the output of the half-moon guar element can be increased. In addition, setting the thermal expansion coefficient of the Huahe board μ substrate below 10x10 /C can be surely prevented when the thermal efficiency of the solar cell is driven by *^^^^ ne 70仟, "expansion and contraction, the semiconductor If the component is applied too much, the joint displacement between the package and the cladding layer may occur, and the bonding failure may occur. ※Wang Yi, the assembly substrate of the present invention is fired after the ceramic substrate of the base material is fired. The through hole is formed and the film is shrunk, and the through hole position is shifted. It is necessary to estimate in advance that the interval formed by the shrinkage is set to be wider, and the interval between the regions is set to be wider: The number of regions, and can reduce the material wave # / add the early film collection 326\||it\94\94145509\TF968049 π 200824058 Furthermore, the electrode layer is formed on the main surface and the external connection surface of the insulating member of the collective substrate of the present invention And forming a conductive layer on the inner surface of the through-hole, the electrode layer and the conductive layer can be connected and connected without causing connection failure. Therefore, according to the division of the above-mentioned collective substrate of the present invention. Semiconductor of the invention The member-mounted member can transmit the conductor member mounted on the main surface through the two-electrode layer and the conductive layer, and can be surely connected to other members without causing connection failure. The external connection surface of the member, at least the surface of the electrode layer is formed at least, and the electrode layer can be soldered, soldered, or the like by various conventional connection methods, and between the electrode layers of other components. In the main surface of the insulating member of the semiconductor element mounting member of the present invention, a region for mounting the semiconductor element is set, and a frame is formed on the main surface of the insulating member by surrounding the region. After the semiconductor element is mounted in the above region, the lid body is joined to the frame body to seal the unit, the half load, and the half (four) element. (4) When the semiconductor element is an image pickup element, the image pickup element is sealed in a state in which the image pickup element is exposed to the cover by using a cover made of a light-transmitting material. The thermal expansion coefficients of the insulating member and the crucible of the above-described semiconductor element mounting member of the present invention are both set to 丨0xl -6 / < 3c or less, and the difference in thermal expansion coefficient is set to 3 <1. -6/. . Hereinafter, the 埶 expansion coefficient of the frame can be made close to the insulating member ′ to prevent the joint of the two from being in a tortuous state: and it is possible to prevent a joint failure or the like from occurring due to a thermal effect. In the insulating member main surface 326 of the above-described semiconductor element mounting member of the present invention, the area of the semiconductor element mounting region is 〇% or more surrounded by the housing: at least the semiconductor element is mounted on the surface of the insulating member main surface 326 聪 \ 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 94 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 When the semiconductor element is an image pickup element, for example, when the semiconductor element is an image pickup element, the metal layer can be made to function as a light shielding layer, and the light incident from the back of the image pickup element by the insulating member can be blocked, thereby improving the sensitivity of the image pickup element. . Further, when the semiconductor element is a light-emitting element, the above-mentioned metal layer can be made to function as a reflective layer, and the light-emitting efficiency of the light-emitting diode can be improved.

因為本發明之攝像元件藉由在具備上述框體的半導體 元件搭載構件,於絕緣構件主面中由框體所包圍出區域 内,搭載半導體元件的攝像元件之後,再於上述框體上接 口由透光ϋ板材所構成之蓋體而構成’因而可在攝像元件 中依可通過蓋體曝光的狀態,將上述攝像元件密封。 本發明的半導體裝置在將集合基板依各區域分割而繁 得的半導體元件搭載構件主面上,搭載半導體元件,並具 ,利用密封材密封的構造,可施行如同f知半導體元件晶 的相同處置’搭载於配線基板等其他構件的搭載部中。 ,外’在搭餘搭载部之前’亦可事先檢查有無不良等情 半導ΐ : I/請搭載作業等之際’因為亦可不直接接觸到 ⑽亦可極力抑制因靜電等情形而發生元件 破損的狀況。 X干 導ίΐ料^明半㈣裝置制將貫通孔的最小孔部利用 而0〃、、二滿,而朝厚度方向封閉的集合基板,並在其主 板盘i = 件,利用密封材密封之後,再將集合基 板“封材-起依各區域分割而製得,可在施行上述密封 326\ 總檔 \94\94145509VTF968049 13 200824058 時,防止密封材通過貫通孔而洩漏於背面側的狀況發生。 所以,例如可省略對集合基板搭載半導體元件之單面侧的 考寸疋£域限疋式雄、封的麻煩,而可整面均利用密封材保 、 護’可促進半導體裝置更加小型化。 再者’將從集合基板分割後的貫通孔至少其中一部分, 設定為在絕緣構件側面呈開放狀態,可使在裸露之貫通孔 内面上所形成的導電層,產生填錫(solder fiUet)形成 鲁部的功能。因而,將半導體裝置利用焊接搭載於其他構件 〜的搭載部之際,可藉由所形成的填錫辅助外部連接用電極 層,俾提升安裝可靠度。 口為本务明的發光二極體構成構件係上述本發明的半 導體裝置中,半導體元件為使用發光元件,且密封材為至 夕使用备光體或保護樹脂中之一者而構成,因而可如同習 知發光元件晶片的相同處置,搭載於發光二極體封裝的搭 載部、或面發光體(其將多數發光元件排列成面狀而構成) _的基板格載部等之上。此外,在搭載於該等搭載部之前, 亦可事先執行發光元件的良否判定及發光色調的調查。 且,當施行搭載作業等之際,因為可不直接接觸到發光元 件’因而可極力抑制因靜電等情況而發生元件破損的狀 況。 、將上述本發明的發光二極體構成構件中,絕緣構件主面 -的電極層最表面中至少其中一部份,利用Ag、A1或Ai合 金等形成,可儘可能將來自發光元件的光(特別為組合螢 光體而發出白色光的較佳波長6〇〇ηιη以下之光),以高效 326\|§^\94\94145509\TF968049 14 200824058 率朝發光二極體構成構件前方侧反射,俾可提升發光效 率。此外,因為本發明的發光二極體使用上述本發明發光 • 一極體構成構件,因而不致浪費高單價的發光二極體封裝 . 等,可以高效率製造。 【實施方式】 圖1所不係本發明集合基板1之實施形態一例,以攝像 元件搭載用絕緣構件2為基礎的集合基板丨部分放大俯視 圖此外,圖2所示係上述集合基板1中,貫通孔11的 部分放大剖視圖,圖3所示係分割集合基板1而成的絕緣 構件2中,貫通孔n之部分放大剖視圖。另外,圖*所 不係絕緣構件2的主面21侧之俯視圖,目5所示係主面 21上接合有框體4而形成的半導體元件搭載構件虬俯視 圖,圖6_所示係絕緣構件2的外部連接面22側之仰視圖。 圖7所不係在半導體元件搭載構件BL的絕緣構件2主面 21上之元件搭載區域21a中,搭載半導體元件的攝像元 並在框體4上接合透光性蓋體FL而形成的攝像 1置PE2之剖視圖。 參照圖卜此例子的集合基板丨整體湘陶絲成平板 狀,且包含有:複數區域la、及一定寬度的區域。該區 域la具有形成板狀絕緣構件2之既定平面形狀(圖中為矩 形狀);該區域lb用於區隔上述複數區们3,在各 la之間設置縱橫矩陣狀,供切割時去除之用。圖中的單 點虛線所示係供區隔區域la、lb的邊界線l。此外 各區域la對應於相互平行之2長邊的位置處,分別跨越 326聰檔\94\94145509\TF968049 15 200824058 等)燒^3形;㈣㈣(陶竟肚片 形成貫通孔u。 〇/、粍法頗難達到之南位置精度 參照圖2,形成夂♦、s ” , 等2個推拔面爪二二的:面分別由第1與第2 從絕緣構件2的主面21侧‘。的二二推 絕緣構件2的厚产方而上面側)起,权置於於 最小孔部11a,开Γ成門°古方’朝向平面形狀為圓形的 在主面2! 徑逐漸變小的圓錐推拔狀,且 在主面21處形成圓形開口。此外, 緣構件2的外部連接面 < 向上述最小孔部lla開口吉二:的下面側)起,形成朝 在外部_22處_=^變小_推拔狀’並 =中所示形狀的貫通孔u的形成方 板狀的集合基板丨,利用後加 : =換2«,__(SandBlast)法的形成方法為 面22側°之^^ 1與圖2 ’使集合基板1的外部連接 J之貝通孔11開口所對應的 穿二开H所稞露出的區域選擇性的朝厚度方向施行 牙孔而形成弟2推拔面llc。在此之同時,針對主面21 則亦同k使貝通孔U開口所對應的圓形區域裸露出,再 將除此以外的區域於利用光阻膜保護狀態下,採取喷砂 326\|I^\94\94145509\TF968049 16 200824058 對集合基板Μ裸露出的區域選擇性朝厚 穿孔而形成第1推拔面llb。 也订 依此,利用切法施行穿孔的特徵係隨穿孔的推進,立 ^尺寸逐漸變小,因此二推拔面形成圓錐推 拔狀/二推拔面llb、llc的連結部形成最小 推 =1貫通孔11。上述方法中,藉由調整 的穿孔深度、穿孔直徑,可任意控制最^ 11 a的開口直徑、以另卜、+、田 丨 1 小孔部11&在絕緣構件2厚 度方向上的形成位置。 延貫通孔n,其第1推拔面llb、與其所 主:21依鈍角的角度^相交,而第2推拔面llc、 因所::卜部連接面22亦是依鈍角的角度Θ 。 ύ尸/r不包極層31、32、導雷μ μ令斷 1推拔面m與主面二電角層部33二際;可大幅降低在第 部連接面22的角部處,發生金屬化:推拔:llc與外 狀況,可在不致發生連接 兄,下备、:土不均勻等 31、犯與導電層33連接。因;寻1^下,確實將電極層 可靠度。 口而,可棱升攝像裝置PE2的 另外,在上述貫通孔u中, 角相交,二者角部的最右;推拔/Ub、llc依銳 或全屬化膜严呈:二 小孔部…的部分處中斷、 =化…不均句狀態。為形成厚度均 的上下部分呈良好連接的導電層1最好二推拔= 326\總檔\94\94145509VTF968049 17 200824058 m、nc亦依鈍角的角度ι相交。為能將二推拔面。卜 lie的夾角Θ 3形成鈍角,只要調整噴砂法等的穿孔條件, '而調整上述二推拔面lib、lie的推拔角度便可。八 、 集合基板1最好熱導率在lOW/mK以上。熱導率達1〇w/mK 以上’可提高半導體元件搭載構件BL的散熱性,因應攝 像兀件PE1的高輸出化。此外’集合基板i最好熱膨服係 數在10x10 V C以下。熱膨脹係數在1 〇χι以下, 防止因元件驅動時的熱效應等而發生膨脹、收縮之萨,Z 攝像元件PE1施加過大應力,導致上述元件ρΕι破 合脫落情況。 ' 能形成滿足該等條件之集合基板丨的材料,有如AW、 AUSiC'SilBeO'M等絕緣性陶兗,就成本的觀 點而言,最好為Ah〇3。但是,若在考慮散熱性的前提下, 集合基板1的熱導率在上述範圍内,最好設定為8〇w/mK 以上,尤以150W/mK以上為佳,為能達較高的熱導率,最 •好採用A1N或SiC。此外,若考慮將與攝像元件pE1間之 熱膨脹係數之差縮小的前提下,最好使用A1N或。 =所以,若將政熱功此專设定為最優先要件,上述材料中 最好採用A1N形成集合基板1,但是當未高度要求散熱功 能時,則最好使用Ah〇3形成集合基板丨。其中,若考^兼 顧機械強度等集合基板1的其他物性、或製造成本等前提 •下,集合基板1的熱導率在上述範圍内,最好設定在 300W/mK以下,而熱膨脹係數在上述範圍内最好設定為 4xl〇-6〜7xl〇‘V〇C 〇 326\總檔 \94\94145509\TF968049 18 200824058 80%以上。藉此’可使電極層31與金屬層5發揮足夠的遮 光層功能。但是,複數電極層31必需相互隔開,且金屬 層5亦必須與各電極層31相互隔開。因此,在電極層 金屬層5間必須設置間隙g,不可將㈣他面積的 觀(即區域21a整面)均利用電極層31、金屬層5覆蓋。 在電極層31與金屬層5之間,若考慮確保能防止複數電 極層31間發生短路岐夠間隙§之前提下,則電極層w 與金屬層5最好形成覆蓋區域仏面積的㈣以下。另外, 極層31擴大形成覆蓋著區域⑴面積的⑽〜晴 恶,便可省略金屬層5。 _ 電極層3卜32、及導電層33均可利用習知周知 ==的金屬材料等形成。此外,上述各層可利用諸如· 又法、真空蒸鍍法、鮮又法等物理蒸鑛法等各種全 2法:形成單層構造、或雙層以上的多層構造。濕^ 為可利用i次的處理形成具有足夠厚度的金屬 :=二31、32、導電層33亦可形成單, ;疋!可在由CU、Ni所構成之單層或雙層的底声 ,知層由Ag、AU等導電性優越的金 ;9 0.H0㈣表面層的多層構造。 屬所構成之厚度 另方面,物理蒸鍍法最好將電極層31、 嘴 33形成積層有功能性分離之複數層的 構造的例子’可舉例如從靠近集合基板k構:起=層 層有: 、側起依序積 (I)由Ti、Cr、NiCr、Ta、及續装么厪几人 及料金屬化合物等所構成, 326V總權:\94\94145509\TF968049 2〇 200824058 基板1間之密接性優越的密接層; )由卜以、(:1^卜1{〇、咖等所構成 止形成下述表面層的金屬發生擴散’且具有防 層;以及 力犯的擴散防止 (I⑴由Ag、A卜Auf所構成 等而形成3層構叙越的表面層 uk— …厚度最好設定為 左右二散厂防止層厚度最好設定為 右。〃左右表面層厚度最好設定為^〜…j 再者,亦可組合使用物理蒸鑛法 層3卜%、導電層33形成多層構造。例H,將電極 鑛法形成密接層與擴散防止層的前提下,3利用物理蒸 鑛法形成由Cu、Ni所構成的底層之後,2濕式電 的表面層。 ’斤構成導電性優越 载= 子31表面上,例 之際的可靠度置焊接搭㈣等連接 在外部連接面22二 位相機等的基板上所設置f在數 面安裝之際的可靠度,亦可机 f接4%仃表 對接合層。 °又由Au#所構成的焊料配 但是,如上述,當導電材料使用如 的電極層3卜32,或配置於多 ?成早層構造 於夕層構以電極層31、32最表 326\^^\94\94145509\TF968049 21 200824058 電集:基二1的主面21上形成半導體元件搭载用 用帝=展夕1卩連接面22上形成與其他構件間的連接 門二:2 ’在貫通孔U内面上形成將二電極層3卜32 間連接的導電層33(圖1〜圖6)。 立二匕主面21側的電極層31係對應各貫通孔蜀 成從成為絕緣構件2的I: : 個電極層31係形 邊的位置處所形成之貫通孔11起, 面22二的長邊方向延設的矩形狀。另-方面,外部連接 扪側的電極層32亦對應各貫通孔η獨立形成複數 個,且各個電極層32形成從成為絕緣構件2的區域la 二=應二矩形之相互平行的2長邊中之1邊的位置處 :=貝=?起’朝另1邊的長邊方向延設的矩形 ,隹導電層33形成覆蓋於貫通孔η内面整面,且 在木δ基板i的主面21側連接於電極層31,在外部連接 面22侧連接於電極層32的狀態。 再者,主面21上在為不接觸到各電極層^ g的狀態下’形成金屬層5。金屬層5與電極層”一:、 成將區域2ia(其係在上述主面21中由框體4·繞出, 供搭載+導體π件用的區域)覆蓋的遮光層功能。換今 ,,金屬層5使用於阻斷通過絕緣構件2,並從上述區^ 21 a上所格載攝像元件ρε 1昔接 件PE1的感度。 1月後入射的光’俾提升攝像元 電極層31與金屬層5最好形成覆蓋於區域2la面積的 326\|I®\94\94145509\TF968049 19 200824058 層的情況時,亦可省略焊墊、焊料配對接合層。此外,因 為金屬層5與電極層31形成於相同面上,因此只要在形 成電極層31之同時,形成具有相同層之構造便可。但是, ,因為金屬層5只要具有遮光層功能便可,因此例如即便電 極層31係形成如上述多層構造時,金屬層5亦可形成具 有足夠厚度之僅1層的單層構造。 f對電極層3卜32、金屬層5施行圖案形成方面,例 如,、要使用金屬遮罩、或微影法的光罩等, •罩所覆蓋並裸露出的集合基板丨表面,利用== 法或物理条鑛法等選擇性施行金屬化便可。此外,為將電 才°运31 32形成多層構造,只要在集合基板}所裸露出 的表面上,重複利用不同金屬施行金屬化便可。另外,導 電層33在主面21上形成電極層31、金屬層5之際,戋 在外部連接Φ 22上形成電極層32之際,或當施行上述: 項作業之際,藉由設定成貫通孔n開口未被光罩所覆蓋 ❿而裸露出的狀態,在形成二電極層31、32之同時,形成 連接於上述二電極層31、32的狀態便可。 為使用已形成有上述電極層3卜32、導電層33、及金 屬層5的集合基板卜製造出供搭載半導體元件之攝像元 件PE1、用的半導體元件搭載構件此,將上述集合基板工 中,由邊界線L所區隔出的區域1 b,利用切割等方式去 除。依此,殘留的區域la各自分離,形成複數個絕緣構 件2。然後,在所形成的各個絕緣構件2主面21上,利 用由如樹脂、低融點玻璃等所構成的接合層B卜而將框 326\總檔 \94\94145509\TF968049 200824058 體4接合,再將主面21上透過框體4之通孔41而裸露出 的區域21a,設定為供搭載半導體元件之攝像元件pE1用 的元件搭載部’便製得半導體元件搭載構件bl(圖4~圖 7)。 合基板,將其利用接合層B1接合於已形成上述電極層 31、32、導電層33及金屬層5的集合基板丨主面以側: 再者,製作内含成為複數框體4(其係配合集合基板的 區域la形成間隔,排列著複數通孔41)之區域在内的集In the image sensor of the present invention, the semiconductor element mounting member including the above-described housing is mounted on the main surface of the insulating member in a region surrounded by the housing, and the imaging element mounted on the semiconductor element is then placed on the housing. The cover body formed of the light-transmissive enamel plate is configured to be 'closed to the image pickup element in a state in which it can be exposed through the cover body. In the semiconductor device of the present invention, the semiconductor element is mounted on the main surface of the semiconductor element mounting member which is divided by the respective regions, and the structure is sealed by the sealing material, so that the same treatment as the semiconductor element crystal can be performed. 'Installed in a mounting part of another member such as a wiring board. In addition, it is also possible to check whether there is any defect or not in the front of the spare part: I/Please carry out the work, etc. 'Because it is not directly in contact with (10), it is possible to suppress component damage due to static electricity and the like. The situation. X dry guide ^ ^ ^ 明 ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四Then, the assembly substrate "sealing material" is obtained by dividing the respective regions, and when the sealing 326\main gear \94\94145509 VTF968049 13 200824058 is applied, the sealing material is prevented from leaking through the through hole and leaking on the back side. Therefore, for example, it is possible to omit the trouble of limiting the size of the single-sided side of the semiconductor element mounted on the collective substrate, and it is possible to use the sealing material to protect the entire surface of the semiconductor device. Further, at least a part of the through-holes divided from the collective substrate is set to be open on the side surface of the insulating member, and a conductive layer formed on the inner surface of the exposed through-hole can be formed to form a solder filu Therefore, when the semiconductor device is mounted on the mounting portion of the other member by soldering, the electrode layer for external connection can be assisted by the formed tin filling, and the electrode layer can be lifted. In the semiconductor device of the present invention, the semiconductor device is a light-emitting device, and the sealing material is one of a light-keeping body or a protective resin. With the configuration, the mounting portion of the light-emitting diode package or the surface light-emitting body (which is configured by arranging a plurality of light-emitting elements in a planar shape) can be mounted in the same manner as the conventional light-emitting device wafer. In addition, before the mounting of the mounting unit, the quality of the light-emitting device can be determined in advance, and the luminescent color can be checked. In addition, when the mounting operation or the like is performed, the light-emitting element can be prevented from being directly contacted. In the case of the above-described light-emitting diode constituent member of the present invention, at least a part of the outermost surface of the electrode layer of the insulating member is made of Ag, A1 or Ai alloy, or the like. Forming, as much as possible, light from the light-emitting element (especially light having a preferred wavelength of 6 〇〇ηηη emitting white light in combination with the phosphor) 326\|§^\94\94145509\TF968049 14 200824058 The rate is reflected toward the front side of the light-emitting diode constituent member, and the light-emitting efficiency can be improved. Further, since the light-emitting diode of the present invention uses the above-described light-emitting body of the present invention In addition, it is possible to manufacture a high-yield light-emitting diode package, and it can be manufactured with high efficiency. [Embodiment] FIG. 1 is an example of an embodiment of the collective substrate 1 of the present invention, and the insulating member 2 for imaging element mounting is used. FIG. 2 is a partially enlarged cross-sectional view of the through-hole 11 in the collective substrate 1 shown in FIG. 2, and the through-hole n is formed in the insulating member 2 in which the collective substrate 1 is divided as shown in FIG. FIG. 6 is a plan view of the semiconductor element mounting member 接合 formed by bonding the frame body 4 to the main surface 21, as shown in FIG. A bottom view of the outer connecting surface 22 side of the insulating member 2 is shown. In the element mounting region 21a on the main surface 21 of the insulating member 2 of the semiconductor element mounting member BL, the imaging element in which the imaging element of the semiconductor element is mounted and the translucent cover FL is bonded to the housing 4 is shown in FIG. Set the cross-sectional view of PE2. Referring to the collective substrate of this example, the entire Xiangtao silk is in the form of a flat plate, and includes a plurality of regions la and a region of a certain width. The region la has a predetermined planar shape (a rectangular shape in the drawing) forming the plate-shaped insulating member 2; the region lb is for partitioning the plurality of regions 3, and a vertical and horizontal matrix is provided between each la for removal during cutting. use. The dotted line in the figure indicates the boundary line l for the partition areas la and lb. In addition, each area la corresponds to the position of the two long sides parallel to each other, respectively, spanning 326 聪 files \94\94145509\TF968049 15 200824058, etc.) burning ^ 3 shape; (4) (four) (Tao Jing belly pieces forming through holes u. 〇 /, Referring to Fig. 2, the accuracy of the south position which is difficult to reach is formed by 2 ♦, s ′′, and the like, and the two faces of the push and pull claws are two: the faces are the side of the main surface 21 of the first and second slave insulating members 2, respectively. The second and second pushes of the insulating member 2 are thicker and the upper side is lifted, and the weight is placed on the smallest hole portion 11a, and the opening is made into a door. The ancient square is circular toward the main surface 2! The conical shape is pushed out and a circular opening is formed at the main surface 21. Further, the outer connecting surface of the edge member 2 is formed toward the outer portion _22 toward the lower side of the opening of the minimum hole portion 11a _=^ becomes smaller _ push-pull' and the shape of the through hole u shown in the shape of the through-hole u is formed by the use of the following: = 2:, __ (SandBlast) method is formed as face 22 The side of the ^^ 1 and FIG. 2 'the outer surface of the collective substrate 1 is connected to the opening of the passhole hole 11 of the J. The tooth hole is formed in the thickness direction to form the 2nd push-out surface llc. At the same time, the main surface 21 is also exposed to the circular area corresponding to the opening of the Beton-hole U, and the other areas are In the state of protection by the photoresist film, sandblasting 326\|I^\94\94145509\TF968049 16 200824058 is used to selectively expose the exposed region of the collective substrate to the first push-out surface 11b. The feature of the perforation by the cutting method is gradually smaller as the perforation advances, so that the two push-out faces form a conical push-out/two push-pull surface llb, and the connection portion of the llc forms a minimum push=1 through-hole 11 In the above method, by adjusting the depth of the perforation and the diameter of the perforation, the diameter of the opening of the most 11 a can be arbitrarily controlled, and the position of the small hole portion 11 & 1 in the thickness direction of the insulating member 2 can be selected. The through hole n is intersected by the first push-out surface 11b, and the angle 2 of the main push surface 21 is at an obtuse angle, and the second push-out surface 11c is also an angle of the obtuse angle Θ. The corpse/r does not include the pole layer 31, 32, the mine guide μ μ, the break 1 pushes the face m and the main face two The corner layer portion 33 is two-way; the metallization can be greatly reduced at the corner portion of the first connecting surface 22: push-out: llc and the external condition, which can be prevented from being connected, and the earth is not uniform. It is connected to the conductive layer 33. Because of the search, the reliability of the electrode layer is surely obtained. In addition, in the through-hole u, the corners intersect, and the rightmost corners of the two corners Pushing / Ub, llc is sharp or all of the film is strictly: the part of the two small holes is interrupted, = ... the state of the uneven sentence. The conductive layer 1 which is well connected to form the upper and lower portions of the thickness is preferably pushed twice = 326\total file\94\94145509VTF968049 17 200824058 m, nc also intersects at an obtuse angle ι. In order to be able to push the two sides. The angle Θ 3 of the lie forms an obtuse angle. As long as the perforation conditions such as the blasting method are adjusted, 'the angle of pushing and pushing the two plucking faces lib and lie can be adjusted. 8. The collector substrate 1 preferably has a thermal conductivity of above lOW/mK. When the thermal conductivity is 1 〇 w/mK or more, the heat dissipation of the semiconductor element mounting member BL can be improved, and the output of the image pickup element PE1 can be increased. Further, the collective substrate i preferably has a thermal expansion coefficient of 10 x 10 V C or less. The thermal expansion coefficient is less than 1 〇χι, and it is prevented from being expanded or contracted due to thermal effects during driving of the element, and the Z imaging element PE1 is subjected to excessive stress, which causes the above-mentioned element ρΕι to break off. The material which can form the aggregate substrate 满足 which satisfies these conditions is, for example, AW, AUSiC'SilBeO'M or the like, and is preferably Ah 〇 3 in terms of cost. However, in consideration of the heat dissipation property, the thermal conductivity of the collective substrate 1 is in the above range, preferably set to 8 〇 w/mK or more, particularly preferably 150 W/mK or more, in order to achieve higher heat. Conductivity, the best use of A1N or SiC. Further, in consideration of narrowing the difference between the thermal expansion coefficients and the imaging element pE1, it is preferable to use A1N or . = Therefore, if the thermal power is specifically set as the most important component, it is preferable to form the collective substrate 1 using A1N. However, when the heat dissipation function is not highly required, it is preferable to form the collective substrate by using Ah3. In addition, the thermal conductivity of the collective substrate 1 is preferably within 300 W/mK, and the thermal expansion coefficient is as described above, taking into consideration the other physical properties of the collective substrate 1 such as mechanical strength, or the manufacturing cost. The best setting in the range is 4xl〇-6~7xl〇'V〇C 〇326\total file\94\94145509\TF968049 18 200824058 80% or more. Thereby, the electrode layer 31 and the metal layer 5 can be made to have a sufficient function as a light shielding layer. However, the plurality of electrode layers 31 must be spaced apart from each other, and the metal layer 5 must also be spaced apart from each electrode layer 31. Therefore, a gap g must be provided between the electrode layer metal layers 5, and the (4) other area (i.e., the entire surface of the region 21a) cannot be covered by the electrode layer 31 and the metal layer 5. Between the electrode layer 31 and the metal layer 5, it is preferable to prevent the occurrence of short-circuiting between the plurality of electrode layers 31, and the electrode layer w and the metal layer 5 are preferably formed to have a coverage area (four) or less. Further, the electrode layer 31 is enlarged to form a (10) to a clear area covering the area of the region (1), and the metal layer 5 can be omitted. The electrode layer 3b and the conductive layer 33 can be formed by a metal material or the like which is known by known ==. Further, each of the above layers may be formed by a single method such as a single layer structure or a multilayer structure of two or more layers, such as a physical vapor deposition method such as a vacuum method or a vacuum method. Wet ^ can be used to form a metal with a sufficient thickness: i = 31, 32, the conductive layer 33 can also form a single, 疋! The bottom layer sound of a single layer or a double layer composed of CU and Ni can be known, and the layer is composed of a gold having excellent conductivity such as Ag and AU, and a multilayer structure of a surface layer of 90.H0 (four). In addition to the thickness of the genus, the physical vapor deposition method preferably forms an example in which the electrode layer 31 and the nozzle 33 are formed by laminating a plurality of functionally separated plural layers, for example, from the vicinity of the collective substrate k: : The side-by-sequence product (I) consists of Ti, Cr, NiCr, Ta, and continuation of several people and metal compounds, 326V total weight: \94\94145509\TF968049 2〇200824058 1 The adhesion layer with excellent adhesion; ) is formed by Bu Yi, (: 1 ^ Bu 1 {〇, coffee, etc., which forms a metal layer that forms the following surface layer, and has a barrier layer); and diffusion prevention of the force (I(1) The thickness of the surface layer uk formed by the composition of Ag, Abu Auf, etc., is preferably set to be the thickness of the prevention layer of the left and right scattering factories. The thickness of the left and right surface layers is preferably set to ^ ~...j Furthermore, it is also possible to use a combination of the physical vapor deposition method layer 3 and the conductive layer 33 to form a multilayer structure. Example H, under the premise that the electrode ore method forms the adhesion layer and the diffusion prevention layer, 3 uses the physical vapor deposition method. After forming a bottom layer composed of Cu and Ni, 2 wet electric surface layers. The conductivity is excellent on the surface of the sub-31, and the reliability of the solder joint (4) is connected to the external connection surface 22, and the reliability of the f is mounted on the substrate of the two-position camera or the like. The machine f is connected to the bonding layer by 4%. The solder is composed of Au#. However, as described above, when the conductive material is used, for example, the electrode layer 3 is 32, or is disposed in a multi-layered early layer structure. The electrode layer 31, 32 is formed on the surface of the main surface 21 of the base 2, and the semiconductor element is mounted on the connecting surface 22 of the semiconductor element. Connection door 2 between other members: 2' A conductive layer 33 (Fig. 1 to Fig. 6) for connecting the two electrode layers 3 and 32 is formed on the inner surface of the through hole U. The electrode layer 31 on the side of the main surface 21 of the vertical surface Each of the through holes is formed in a rectangular shape extending from the through hole 11 formed at a position where the I: : electrode layer 31 of the insulating member 2 is formed, and the outer surface of the surface 22 is extended in the longitudinal direction. The electrode layer 32 on the side also forms a plurality of independent through-holes η, and each electrode layer 32 is formed. The area la of the edge member 2 = the position of one of the two long sides parallel to each other: the rectangle which is extended toward the long side of the other side, and the conductive layer 33 is formed. It covers the entire inner surface of the through hole η and is connected to the electrode layer 31 on the main surface 21 side of the wood δ substrate i, and is connected to the electrode layer 32 on the side of the external connection surface 22. Further, the main surface 21 is not In a state in which the respective electrode layers are contacted, the metal layer 5 is formed. The metal layer 5 and the electrode layer are formed in a state in which the region 2ia is formed in the main surface 21 and is surrounded by the frame 4· for mounting + The area of the conductor π piece) covers the function of the light shielding layer. In other words, the metal layer 5 is used to block the sensitivity of passing through the insulating member 2 and carrying the image pickup element pε 1 from the above-mentioned region 21a. When the light incident after 1 month is increased, the image electrode layer 31 and the metal layer 5 preferably form a layer of 326\|I®\94\94145509\TF968049 19 200824058 covering the area of the area 2la, and the pad may be omitted. , solder mating bonding layer. Further, since the metal layer 5 and the electrode layer 31 are formed on the same surface, it is only necessary to form the structure having the same layer while forming the electrode layer 31. However, since the metal layer 5 has a function as a light shielding layer, for example, even when the electrode layer 31 is formed in the above-described multilayer structure, the metal layer 5 can have a single layer structure having only one layer having a sufficient thickness. f. For pattern formation of the electrode layer 3 and the metal layer 5, for example, a metal mask or a lithography mask or the like is used, and the surface of the collective substrate covered and exposed by the cover is used by == Selective metallization can be carried out by law or physical mineralization. Further, in order to form the multilayer structure by the electric power transfer 31 32, metallization by using different metals may be repeated on the exposed surface of the collective substrate}. Further, when the conductive layer 33 forms the electrode layer 31 and the metal layer 5 on the main surface 21, when the electrode layer 32 is formed on the external connection Φ 22, or when the above-mentioned operation is performed, it is set to be continuous. In a state in which the opening of the hole n is not covered by the mask, the two electrode layers 31 and 32 are formed, and the two electrode layers 31 and 32 are connected to each other. In order to manufacture the imaging element PE1 for mounting the semiconductor element and the semiconductor element mounting member for mounting the semiconductor element, the semiconductor substrate mounting member, in which the electrode layer 3, the conductive layer 33, and the metal layer 5 are formed, the assembly substrate is used. The area 1 b partitioned by the boundary line L is removed by cutting or the like. Accordingly, the remaining regions la are separated to form a plurality of insulating members 2. Then, on the main surface 21 of each of the formed insulating members 2, the frame 326\total file\94\94145509\TF968049 200824058 body 4 is joined by a bonding layer B composed of, for example, a resin, a low-melting glass, or the like. The region 21a exposed on the main surface 21 through the through hole 41 of the casing 4 is set to the element mounting portion 'for the imaging element pE1 on which the semiconductor element is mounted', and the semiconductor element mounting member bl is obtained (FIG. 4 to FIG. 7). The bonding substrate is bonded to the side of the main surface of the collective substrate on which the electrode layers 31 and 32, the conductive layer 33, and the metal layer 5 have been formed by the bonding layer B1. Further, the inclusion is made into a plurality of frames 4 (the system) The region la of the collective substrate is formed with a space, and the set of the plurality of through holes 41) is arranged.

後,再將集合基板1中的區域lb,和成為框體4的集合 基板中重疊於上述區域lb的區域,利用切割等方式去 除,亦可製得複數個絕緣構件2與框體4積層的半導體 件搭載構件BL。 框體4在考慮防止於與絕緣構件2積層的狀態下發生龜 料變形、或為縮小與半導體元件間之熱膨脹係數之差= 财提下,最好利用熱膨脹係數在1〇xl〇_6/t^ 4xl(T6〜7xl(T6/°c為佳),且盥维緣接处〇 ^ )且^、、、、巴緣構件2之熱膨脹係數間 的爰在3x10 /。〇以下(尤以]η-"” 成。更進一…上 c以下為佳)的材料形 H ’联好利用與絕緣構件2相同的材料步 成框體4,可完全消除埶膨眼你批、, tf ^ 、 ,、…、v脹係數是。例如當絕緣構件2 係由A1N形成時,框體4悬杯介士 Λ η L U 亦由Α1Ν形成,當絕緣構件 2係由A12〇3形成時,框濟4+丄 框η*主道触 亦由Ah〇3形成。此外, C體4 *半導體元件為攝傻 4 -l Λ .,, 卞,為此將通過上述框體 夫品要光予以阻斷,最好使用遮光性材料形成 參照圖7,本發明的攝像裂置PE2在上述半導體 326\總檔\94\94M5509\TF968049 23 200824058 載構件BL的區域21",搭载攝像元件pE 述攝像元件PE1的端子(未圖示)、與電極層31裸== 上逑區域21a内的前端部,透過焊接搭線wb連接 、 再於框體4上利用由樹脂、低融點玻璃等所構成的接人声 :像光性材料所構成的蓋體FL而構成。根“ 攝像裝置PE2,可對攝像元件pE1在通過蓋體fl曝光的 狀態下,將上述攝像元件PE1密封。攝像元件pEi的各# 子透過焊接搭線WB、電極層3卜導電層33及電極層^, 而連接於數位相機等的基板上所設置的電極層等。a 圖8所示係本發明集合基板1實施形態另-例,以發光 元件搭載用絕緣構件2為基礎的集合基板丨之部分放_ 視圖。圖9所示係上述集合基板i中,貫通孔n的部分 放大剖視圖,® H)所示係分割上述集合基板1而成的絕 緣構件2中,貫通孔u之部分放大剖視圖。圖u所示係 、”邑、’彖構件2的主面21側之俯視圖,目12所示係外部連接 面22侧的仰視圖。圖13所示係在半導體元件搭載構件 BL的絕緣構件2主面21上,搭載半導體元件的發光元件 LE1/同牯利用密封材的螢光體及/或保護樹脂抑密封的 發光二極體構成構件LE2之剖視圖,目14所示係將發光 二極體構成構件LE2搭載於封裝7上的發光二極體ίΕ3之 剖視圖。 筝照圖8,此例子的集合基板1仍是整體由陶瓷形成平 胙而構成板狀%緣構件2,且包含有··複數區域1 a、及 -定寬度的區士或lb。該區域la具有既定之平面形狀(圖 326\H^f\94\94145509\TF968049 24 200824058 中為矩形狀);該區域lb依區隔上述複數區域之方气 在各區域1 a之間設置縱橫矩陣狀,供利用切割而去☆ 用。圖中的單點虛線所示係供區隔區域la、lb的邊 L。此外,在各區域la對應於相互平行之2長邊的位 1處$ 分別於上述邊界線L·附近處形成複數個(圖中為3 孔11。 )貝逋 上述集合基板1最好如同前例,將其母材陶究的前驅體 (陶究胚片等)燒結而形成平板狀之後,再利用後加工 貫通孔11而製作。藉此,可依習知的共燒法頗難達到 鬲位置精度形成貫通孔u/此外,電極層31、32、導兩 層33亦最好形成於經燒成後的集合基板丨表面上。此p 況下,在光反射率優越之依照共燒法所形成的由m〇、^ 所構成底層上’亦可形成頗難利用電鍍法形成的Μ制之 層’並當作電極層31等。 衣·^ 翏照圖9,形成各貫通孔u的内面分別由帛工2 t::=llb、11C所構成。其中,第1推拔面爪 攸絶、緣構件2的主面21侧(圖中的上面侧)起,設置於p 的厚度方向之一處’朝向平面形狀為圓形的最: 形成開σ直徑逐漸變小的圓錐推拔狀,且在主 =的^成^形開口。此外,第2推拔面山從絕緣構 連接面22侧(圖中的下面側)起,形成朝向上 山且開口直徑逐漸變小的圓錐推拔狀,並在 外部連接面22處形成圓形開口。 在 藉此推拔面llb、與其所延續的主面21依純角 326、總檔\94\941455〇9\TF968〇49 25 200824058 的角度θ,相交,而第2推拔面llc、與其所延續的外部連 接面2 2亦依鈍角的角度0 2相交,因而,當利用例如物理 蒸鍍、印刷、電鍍等方法,形成電極層31、32、導電層 33之際’可大幅降低在第1推拔面lib與主面21的角部、 及第1推拔面11 c與外部連接面22的角部處,發生金屬 化剝落、膜厚不均勻等狀況。因而,可在不致發生連接 不良等情況下,確實將電極層31、32與導電層33連接, 可提升發光二極體構成構件LE2、及發光二極體lE3 靠度。 翏,圖ίο,上述貫通孔η在其内面形成導電層33之 際’取小孔部11a的部分利用形成導電層33的導電材料 33a沉^而填滿,並在分割前的狀態下朝集合基板ι的厚 ^方向壬封閉狀。藉此,如之前所説明,當利用接著的步 驟,將在上述集合基板1的各絕緣構件2主面21上所搭 載的、發光το件LE1,使用密封材的螢光體及/或保護樹脂 FR饴封之際,可防止上述螢光體及/或保護樹脂經由 貫通孔11洩漏於集合基板丨背面。 但疋,當形成導電層33之際,於貫通孔u中,二推拔 f 11卜11c角部的最小孔部Ua部分,若發生金屬化剝 落或膜厚不均勻情況,可能無法利用導電材料33&將最小 孔口P 11a良好地填滿。考慮將最小孔部利用導電材料 33a良好填滿的前提下,則二推拔® 11b、11c亦最好依 鈍角的角度0 3相交。為將二推拔面⑽、HC的夾角Θ 3 形成鈍角,/、要调整喷砂法等所施行穿孔的條件、或調整 326\ 總檔\94\94145509\TF968049 200824058 二推拔面lib、lie的推拔角度便可。 與圖9,上述貫通孔11中,第2推拔面… 述邊界線物於集合基板1中成為絕緣 f的區域la、與各區域la間的區域lb之間)的位置 地…、:後’利用切割等將區域i b去除而分割各區域^, ::上0:圖12所示’在構成半導體元件搭载構件BL的絕 緣構件2之側面23處,在上述第2推拔面Uc之内 形成的導電層33,利用開口 lld而裸露出。因此,使裸 露出的導電層33發揮填錫形成部的功能,當將發光二極 體構成構件LE2利用焊接而搭載於其他構件(例如圖心斤 ,光二極體LE3之封裂7等)上之際,藉由所形成的 填錫輔助外部連制電極層32,可提升絲可靠度。 對預先燒結而形成平板狀的集合基板i,利用後又加工形 成具有該形狀的貫通孔U的方法,最好採用如前所説明 的使用喷砂法之形成方法。上述方法藉由㈣二推拔面 lib、lie的穿孔深度、穿孔直徑,便可任意控制最小孔 部Ua開口直徑、上述最小孔部Ua在絕緣構件2厚度方 向上的形成位置。 參照圖9,依如上述所控制的最小孔部…在絕緣構件 2厚度方向上的形成位置’依主面21距最小孔部山的 距離h表示’最好在超過上述絕緣構件2厚度㈣〇倍, 且2/3倍以下的範圍内。藉此,可確保推拔面⑽、山 位於最小孔部;lla之上下,且可使第】推拔面m與主面 2卜依鈍角的角度〜相交,並可使第2推拔面Uc與外 326\|I^\94\94145509\TF968049 21 200824058 部連接面22亦是依鈍角的角度θ2相交,俾可 所形成的電極層3卜32、與導電層33確實連接。,、 相丨可確保從最小孔部&起延續於外部連接面22 面積,亦…1 在導電層33中的露出 口…、充分發揮填錫形成部的功能。此外,利用 处料 =所施行的形成方法,藉由將從集合基板!二側 =的第1與第2推拔面llb、Uc相連接,亦可在不 孔η發生變形等情況下確實形成。另外,考慮 、面1 1 c中,充分確保具填錫形成部 33露出面積之前提下,上述距離h最好為絕緣丄Ί 度㈣1/2倍以下。為利用上述形成方法確實的形成貫通 孔η ’上述距離h尤以設定在^瓜⑽“左右的範 為佳。 再者,參照圖9,最小孔部Ua的開口直徑d最好在1〇 // m以上。開口直徑d達1〇// m以上的最小孔部ua,當 籲利用上述噴砂法等普通加工方法形成貫通孔u時,可形 成精度較佳狀態。此外,亦可在各個貫通孔u的最小^ ^ 11a = 口直徑d統一的狀態下形成,因為為形成最小孔 部11a時並不需要其他的加工步驟等,因而可提升半導體 元件搭載構件BL的生產性,俾可達降低成本之效果。 再者,上述最小孔部11 a的開口直徑d最好在2 〇 〇 # m .以下。開口直徑4在2〇〇//m以下,當在貫通孔u内面形 成導電層33之際,可更有效率地利用導電材料33a將最 小孔部11a填滿,因而可更加確實地防止螢光體及/或保 326聰檔 \94\94145509\TF968049 28 200824058 護樹脂FR發生洩漏等狀況。 、另外’當對貫通孔11之最小孔部11a,則喷砂法等 .普通的加工方法而更確實地貫通,且在貫通孔11内面形 -成導電層33之際,考慮將最小孔部11a更效率佳地利用 導電f料33a填滿之前提下,上述最小孔部山的開口直 徑好為50〜150#m,尤以75〜125#m為佳。 集合基板1在考慮提高半導體元件搭載構件BL的散熱 性,而因應發光元件LE1高輸出化的前提下,最好將熱導 率設定在lOW/inK以上,尤以8〇w/mK以上為佳更以 150W/mK以上為佳。此外,在考慮兼顧機械強度等其他物 性、製造成本等前提下,則集合基板丨的熱導率最好設定 在300W/mK以下。 再者,集合基板1在考慮防止因元件驅動時的熱效應等 而發生膨脹、收縮之際,對發光元件LE1施加過大應力, 導致上述元件LE1破損、或接合脫落狀況的前提下,熱膨 #脹係數最好設定在10χ10-νι以下。此外,在考慮兼顧機 械強度等其他物性、製造成本等前提下、則集合基板j的 熱膨脹係數最好設定為4χ1(Γδ〜7xl(T6/°C。 形成此滿足该等條件之集合基板1的材料有如:A1 n、 Al2〇3、SiC、Si—、BeO、BN等絕緣性陶瓷。其中,特別 '為能達成高熱導率,最好使用AlN、SiC,而在縮小與發 . 光元件LE1間之熱膨脹係數之差的前提下,最好使用如 A1N、A12〇3。若將成本設定為最優先考慮因素,則最好使 用 A 1 2〇3 〇 326\i|^\94\94145509\TF968049 29 200824058 翏照上述各圖,在上述集合基板丨的主面21上形成半 導體元件搭載用電極層3卜在外部連接面22上形成鱼其 '他構件間的連接用電極層32,在貫通孔u内面形成將二 ’ 廷極層31、32間相連接的導電層33。 、 隨此’貫通孔11的最小孔部lla藉由形成導電層33的 2電材料3 3 a之沉積而被填滿,在將絕緣構件2分割前的 貝通孔11 ’王朝集合基板丨厚度方向封閉之狀態。藉此, 在電極層31上搭載發光元件LE1並密封之際,可防止發 光體及/或保護樹脂FR通過貫通孔u並洩漏於背面侧, 例如可省略對集合基板〗搭載發光元件LE1的主面21側 之特定區域,施以限定性密封的麻煩程序,而可整面均利 用上述螢光體及/或保護樹脂密封,因而可更加 光二極體構成構件1^2的小型化。 最小孔部lla利用導電材料33a填滿的集合基板}厚度 方向厚度t】,最好設定為集合基板丨厚度七的1/5〇〜I” _ 2。右厚度t為集合基板(厚度t<)的1/5〇以上,在密封 牯便可確貫防止因其本身重量等,導致已封閉的貫通孔 脫落,造成螢光體及/或保護樹脂FR洩漏於外部連接 面22側的情況發生。此外’若厚度ti為集合基板工厚度 t〇的1/2以下,便可確保利用最小孔部lla使外部連接二 22側之導電層33裸露出的露出面積,俾可充分發揮填錫 ,形成部的功能。 另外,在考慮更增加具填錫形成部功能的導電層露 出面積,且在密封時更確實的防止因其本身重量等,而造 326\$雇檔\94\94145509VTF968049 200824058 =:的貫通孔n脫落,導致榮光體及/或保護樹脂 / 6 '外部連接面22側之狀況發生的前提下,最小孔 f 11a利料電材料33a填滿的集合基板工厚度方向上的 =七,尤以設定為集合基板j厚度七。的倍為 更佳。 f貫通孔11内面所形成的導電層33厚度t2,最好設定 孔部11a開Π直徑d的Q. 2]· G倍。厚度t2達開口 Ϊ二可的上2倍以上,當在貫通孔11内面形成導電層33 、名,'门、取小孔部11&更效率佳地利料電材料33a填 漏等;1可更確貫地防止螢光體及/或保護樹脂FR發生洩 但疋,若厚度t2超過開口直徑d的1〇倍 得更佳的效果,尚需要多餘導 …、法名又 _ = mlla填滿時的效率降低。所以,厚度^最好 二的u倍以下。另外,在考慮將最小孔 二率佳地利用導電材料咖填滿之前提下,導電 二 2lt#t基板1中成為各個絕緣構件2的區域la之主面 面方^別形成每2個半導體元件搭載用電極層31各朝 1中成\=,且依絕緣狀態設置。此外,在上述集合基板 亦分財士…域U之外部連接面22側, 別形成母2個外部連接用電 開,且依絕緣狀態設置。所以,主/^各朝面方向隔 所以主面21側的2個電極層 326、總檔 \94\94145509VTF968049 3 】 200824058 11、與外部連接面22㈣2個電_ 32中, 基板1 雙面m透過在貫通孔在; D層3卜32中將成為絕緣構件2的區域Ia 一二 別,成於3個地方)内面的導電層犯而相連接°。、、’ ’ ’ /刀 ,言之’電極層31(其平面形狀形成略矩形 ^層3lb (其從上述電極層31之一側邊⑴ ^又 =1方,,並到達貫通孔n在主面21側二 及貝通孔11内面的導電層33,形成一體且相互 ^此外’電極層32(其平面形狀呈略矩形狀, =孔U在外部連接面22側開口呈部份重疊狀態)、 /、貝通孔11内面的導電層33,同樣形成一體並相互連接。 外部連接面22上所設置的電極層32面積合計,佔上述 外部連接面22面積的比例,最好設定為3〇%以上。藉此, 當將發光二極體構成構件LE2,在半導體元件搭載構0件乩 =外。卩連接面22側之電極層32、與發光二極體LE3的封 衣7(或在面發光體的基板上所設置的電極層)間,利用焊 接施行表面安裝之際,可充分確保半導體元件搭載構件 封衣7(或基板)間的散熱通路,因而可達成發光二 極體LE3的高輸出化。 另外,在考慮更加螻保散熱通路的前提下,電極層32 的。面積合計,佔外部連接面22的面積比例,最好設定在 5以上’尤以70%以上為佳。但是,在考慮將2個以上 2¾極層32’當如上述般形成相互朝面方向隔開之際, 月匕充刀確保二電極層32間的絕緣性之前提下,電極層32 3%\總檔\94\94145509\TF968049 200824058 r〇r;。計’佔外部連接面22的面積比例,最好設定在 電極層3卜32、及導電層33如同上 ::r:r等’且可形成單層構造、或雙^ 層31、32施行圖案形成的方法,亦“ Π上述的方法。在電極; A1或A1合金等所構成之:自、::置=竑、 …的短 ^ 寸別對450nm以下的短波長光且優越的反 射率’有助於提升當組合螢光”的反 發先元件LE1之發光效率 《出白色光時的短波長 :層=金置屬:Λ為t電材:’並形成單層構造 ;夕層構造的電極層31最表層時, 1 亦以略反射層。此外’在電極層32的表面上,亦可形 成如則所説明的由Au等所構成焊料配對接合層,藉由將 Au使用為導電材料,且形成單層構造的電極層犯,並配 ί = ΐ構造的電極層32最表層,可省略輝料配對接合 為在使用上述集合基板!,製造供半導體元件的發光元 件LE1搭載用之半導體元件搭載構件乩,同時製造發光 二極體構成構件LE2,可在集合基板!上所包含的各^域 la之電極層31上,分別搭載發光元件ui,且將集合基 板1整面利用密封材的螢光體及/或保護樹脂FR密封之 後,再利用切割等方法去除集合基板i的區域lb。依此, 326\||ig\94\94145509\TF968049 33 200824058 : = = 自分離而形成半導體元件搭载構件BL, 光元:「:/3戶 1示的發光二極體構成構件LE2。發 6、搭载可藉由將半導體元件搭载構件Μ + 極層31、盥發弁分丛τη 戮偁件肌的電 SL焊接而實:⑻之未圖示電極層’透過焊料層 中m牛^1搭載時所使用的焊料,在考慮後續步驟 焊料安,的it—極體構成構件LE2對封裝7或基板施行 /衣的剛棱下,最好使用融點較高的Au-sn系、Au_Ge :方::Sl而I,料。此外’發光元件LE1亦可不採取烊 μ 吏AU凸塊搭載於半導體元件搭载構件BIj 。另外’亦可在將發光元件LE1使用焊料或接 於半導體元件搭載構件BL之後,再將發光元件 電極層31利用焊接搭線方式連接。 /、 將么光元件LE1岔封的保護樹脂,可使用如 石夕氧系等自知周知的各種保護樹脂。特別在考慮耐敎性、 以及對紫外線的耐性等前提下,最好使用石夕氧系樹脂。此 外’螢光體尚有與放射出波長_四以下’特別係450nm 以下之短波長光的發光元件LE1組合’而發出白色光的習 知周知各種螢光體。當合併使用螢光體與保護樹脂時 好將電極層31上所搭載的發光元件⑻,先利用榮光體 密封後,再依覆蓋榮光體之方式利用保護樹脂密封。另 外,亦可利用螢光體與保護樹脂的混合物密封。 半導體元件搭载構件BL面積(換言之,在本例子中為絕 緣構件2的主面21與外部連接面22面積),最好為主面 326\總檔 \94\94145509\TF968049 34 200824058 21上所搭載發光元件LE1面積(在主面21 的1·1〜4倍。當半導體元件搭載構件 積赶又景=積) 件⑻面積的4倍時,可極力縮小其㈣光兀 :隨此現象,恐無法將在半導體元件搭载== 二:發光元…形成的發 狀於發先凡件的晶片視同1個構件處置般,组 衣、xS一極體LE3的封裝7中、或搭载於 ;上。此外,若半導體元件搭载構件BL過大:=: 先兀件LE1不良時所衍生的材料浪^ 情況幾乎無差異的現象。 μ知封裝的 二前所説明由熱導率較高之材料所構成的絕 可^Γ’因而其面積即使在上述範圍内亦最好儘 了此縮小。換言之,半導體元件搭載構件豇 3少材料浪費的前提下,在上述範圍内,特別!:設ί 2光几件LE1面積的3.5倍以下為佳’尤以3〇倍以下 ,者’若半導體元件搭載構件BL面積,小於發光元件 面積的1.1倍,恐難施行發光元件!^E1的搭載作業。 ί 1卜’ t別在發光元件L E1的侧面側恐無法利用保護樹脂 杏刀後封。另外,在考慮提升搭載的作業性,以及更確 貫將發光元件LE1利用保護樹脂等密封的前提下,半導體 凡件搭载構件BL的面積,在上述範圍内特別以設定為發 光=件LE1面積的丨.3倍以上為佳,尤以15倍以上為佳x。 絕緣構件2的厚度在考慮充分確保強度且可盡量縮小 326、總檔\94\94145509VTF968049 35 200824058 半導體元件搭載構件BL容積的前提下,最好設定為 〇·1〜1mm,尤以0.2〜0· 5mm為佳。 將上述發光二極體構成構件LE2複數個搭載於基板 上,可構成面發光體。此外,發光二極體構成構件LE I使用為發光二極體元件的最終形態。例如在印刷電路板 等電路基板、液晶的背光構成構件等等所需位置處,利用 迴焊等方法施行焊料安裝,亦可具有發光二極體的功能。Then, the region lb in the collective substrate 1 and the region of the assembly substrate which is the frame 4 are superimposed on the region of the region lb, and are removed by dicing or the like, and a plurality of insulating members 2 and the frame 4 can be laminated. The semiconductor device mounting member BL. The frame 4 is considered to prevent deformation of the tortoise in a state of being laminated with the insulating member 2, or to reduce the difference in thermal expansion coefficient between the semiconductor element and the semiconductor element. It is preferable to use a thermal expansion coefficient of 1〇xl〇_6/ t^ 4xl (T6~7xl (T6/°c is preferred), and the edge of the 盥 缘 〇 ^ ) and the thermal expansion coefficient of the edge member 2 of the ^, ,, and the edge member 2 is 3x10 /. 〇The following (especially) η-"". Further into the upper...c is better than the material shape H', and the same material as the insulating member 2 is used to form the frame 4, which can completely eliminate the swelling of the eye. Batch, tf ^ , , , ..., v expansion coefficient is. For example, when the insulating member 2 is formed of A1N, the frame 4 can be formed by Α1Ν, when the insulating member 2 is made of A12〇3 At the time of formation, the frame 44+丄 frame η* main road contact is also formed by Ah〇3. In addition, the C body 4* semiconductor element is a dull 4 -l Λ .,, 卞, for which the above-mentioned frame body will be passed To block light, it is preferable to use a light-shielding material. Referring to FIG. 7, the image-cracking PE2 of the present invention is provided with an image pickup device in the region 21" of the above-mentioned semiconductor 326\total file\94\94M5509\TF968049 23 200824058. pE The terminal (not shown) of the image sensor PE1 and the electrode layer 31 are bare == the tip end portion in the upper region 21a is connected to the welding wire wb, and the resin 4 and the low melting point glass are used on the frame 4. The connection sound composed of the like is composed of a cover body FL composed of a light material. The root "image pickup device PE2 can be used for the image pickup unit. pE1 in a state where the lid body fl by exposure, and the imaging element PE1 seal. Each of the image pickup device pEi is connected to an electrode layer or the like provided on a substrate of a digital camera or the like by the bonding wire WB, the electrode layer 3, the conductive layer 33, and the electrode layer. In the embodiment of the collective substrate 1 of the present invention, a partial view of the collective substrate based on the insulating member 2 for mounting the light-emitting element is shown in Fig. 8. Fig. 9 is an enlarged cross-sectional view showing a portion of the through-hole n in the collective substrate i, and Fig. 9 is a partially enlarged cross-sectional view showing the through-hole u in the insulating member 2 in which the collective substrate 1 is divided. Fig. u is a plan view showing the main surface 21 side of the "邑" member, and the bottom view of the outer connecting surface 22 side is shown in Fig. 12. The insulating member 2 of the semiconductor element mounting member BL is shown in Fig. 13. In the main surface 21, a light-emitting element LE1 on which a semiconductor element is mounted, a cross-sectional view of a light-emitting diode structure member LE2 sealed with a phosphor of a sealing material and/or a protective resin, and a light-emitting diode are shown in FIG. A cross-sectional view of the light-emitting diodes 3 mounted on the package 7 in the package member LE2. As shown in Fig. 8, the collective substrate 1 of this example is still formed entirely of ceramics to form a plate-shaped % edge member 2, and includes a plurality of regions 1 a, and a fixed width zone or lb. The region la has a predetermined planar shape (Fig. 326\H^f\94\94145509\TF968049 24 200824058 is rectangular); the region lb is separated by The square of the above-mentioned plural area is arranged in a vertical and horizontal matrix between the respective regions 1a, and is used for cutting by ☆. The dotted line in the figure indicates the side L of the partition areas la and lb. The area la corresponds to the two long sides of the two parallel sides at position 1 respectively. A plurality of dots are formed in the vicinity of the boundary line L (three holes 11 in the figure). The above-mentioned collective substrate 1 is preferably the same as the former example, and the precursor of the base material (the ceramic tile, etc.) is sintered to form a flat plate shape. It is produced by processing the through-holes 11 and then it is difficult to form the through-holes u by the conventional co-firing method. Further, the electrode layers 31 and 32 and the two layers 33 are preferably formed. On the surface of the assembled substrate after firing, in the case of p, the underlying layer composed of m〇 and ^ formed by the co-firing method can also form a crucible which is difficult to form by electroplating. The layer "made as the electrode layer 31" is used as the electrode layer 31. The inner surface of each of the through holes u is formed by the completion of 2 t::=llb and 11C, respectively. The side of the main surface 21 (the upper side in the drawing) of the edge member 2 is provided at one of the thickness directions of p, and is the most circular shape toward the plane shape: a cone push which gradually becomes smaller in diameter σ In addition, the second push-out surface is from the side of the insulating joint surface 22 (the lower side in the figure). Forming a conical push-out shape that is upward toward the mountain and gradually decreasing in diameter of the opening, and forming a circular opening at the outer connecting surface 22. The push surface 11b and the main surface 21 continuing therewith are at a pure angle 326, a total length \94\941455〇9\TF968〇49 25 The angle θ of 200824058 intersects, and the second push-out surface llc intersects with the continuation of the outer joint surface 2 2 at an angle 0 2 of the obtuse angle, thus, when utilizing, for example, physics When the electrode layers 31 and 32 and the conductive layer 33 are formed by methods such as vapor deposition, printing, plating, etc., the corners of the first push surface lib and the main surface 21, and the first push surface 11 c and the outside can be greatly reduced. At the corners of the joint surface 22, metallization peeling and uneven film thickness occur. Therefore, it is possible to reliably connect the electrode layers 31 and 32 to the conductive layer 33 without causing connection failure or the like, and it is possible to improve the reliability of the light-emitting diode constituent member LE2 and the light-emitting diode 1E3. In the case where the through hole η is formed with the conductive layer 33 on the inner surface thereof, the portion where the small hole portion 11a is taken is filled with the conductive material 33a forming the conductive layer 33, and is filled toward the set before the division. The thickness of the substrate ι is closed. Therefore, as described above, the phosphor illuminating member LE1 mounted on the main surface 21 of each insulating member 2 of the collective substrate 1 is irradiated with a phosphor and/or a protective resin of the sealing material. When the FR is sealed, the phosphor and/or the protective resin can be prevented from leaking through the through hole 11 to the back surface of the collective substrate. However, when the conductive layer 33 is formed, in the through hole u, the portion of the smallest hole Ua of the corner portion of the 11b 11c is pushed out, and if metallization peeling or uneven film thickness occurs, the conductive material may not be used. 33& fills the smallest orifice P 11a well. In the case where the minimum hole portion is well filled with the conductive material 33a, it is preferable that the two push pins 11b and 11c intersect at an angle 0 3 of the obtuse angle. In order to form an obtuse angle between the two extraction faces (10) and the angle HC 3 of the HC, /, adjust the conditions for the perforation performed by the sand blasting method, or adjust the 326\ total file\94\94145509\TF968049 200824058. The push angle can be. With reference to Fig. 9, in the through hole 11, the second push-out surface is a position where the boundary line object is between the region la which is the insulating f in the collective substrate 1 and the region lb between the regions la: 'The area ib is removed by dicing or the like to divide each area ^, ::Up 0: 'On the side surface 23 of the insulating member 2 constituting the semiconductor element mounting member BL, as shown in FIG. 12, within the second push surface Uc The formed conductive layer 33 is exposed by the opening 11d. Therefore, the exposed conductive layer 33 functions as a tin-filled portion, and the light-emitting diode constituent member LE2 is mounted on another member (for example, the core of the photodiode, the crack of the photodiode LE3, etc.) by soldering. At the same time, the reliability of the wire can be improved by the formation of the tin-filled auxiliary external electrode layer 32. A method of forming a flat-shaped collective substrate i by pre-sintering and forming a through-hole U having such a shape after use is preferably a method of forming a sandblasting method as described above. The above method can arbitrarily control the opening diameter of the minimum hole portion Ua and the formation position of the minimum hole portion Ua in the thickness direction of the insulating member 2 by (4) pushing the surface of the lib, lie, and the diameter of the hole. Referring to Fig. 9, the minimum hole portion controlled as described above is formed in the thickness direction of the insulating member 2 'in terms of the distance h from the main hole 21 to the smallest hole portion mountain', preferably exceeding the thickness of the above-mentioned insulating member 2 (four) Double, and within 2/3 times the range. Thereby, it is ensured that the push surface (10) and the mountain are located at the minimum hole portion; lla is above and below, and the first push surface m can be intersected with the angle ~ of the main surface 2 at an obtuse angle, and the second push surface Uc can be made. The outer joint surface 22 is also intersected by the angle θ2 of the obtuse angle, and the electrode layer 3 formed by the bismuth 32 is surely connected to the conductive layer 33. In contrast, it is possible to ensure the area from the smallest hole portion & the continuation of the outer connecting surface 22, and the opening of the conductive layer 33, and the function of filling the tin forming portion. In addition, use the material = the method of formation that is performed, by using the substrate from the collection! The first and second push surfaces 11b and Uc of the two sides are connected to each other, and can be formed without deformation of the hole η or the like. Further, it is considered that the surface 1 1 c is sufficiently removed before the exposed area of the tin-filled portion 33 is formed, and the distance h is preferably 1/2 or less times the insulating strength (four). In order to form the through-hole η ' by the above-described forming method, the above-mentioned distance h is preferably set to the left-and-right direction. Further, referring to Fig. 9, the opening diameter d of the smallest hole portion Ua is preferably 1 〇 / /m or more. The minimum hole portion ua having an opening diameter d of 1 〇//m or more, when the through hole u is formed by a general processing method such as the above-described sand blasting method, a state in which the precision is better can be formed. The minimum ^ ^ 11a = hole diameter d of the hole u is formed in a state in which the port diameter d is uniform, since no other processing steps or the like are required for forming the minimum hole portion 11a, so that the productivity of the semiconductor element mounting member BL can be improved, and the defect can be reduced. Further, the opening diameter d of the minimum hole portion 11a is preferably 2 〇〇# m or less. The opening diameter 4 is 2 〇〇//m or less, and the conductive layer 33 is formed on the inner surface of the through hole u. In the meantime, the minimum hole portion 11a can be filled more efficiently by using the conductive material 33a, so that it is possible to more reliably prevent leakage of the phosphor and/or the protective resin FR of the fluorescent body and/or the protective device FR \ 94 94 94 94 94 94 94 94 94 94 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Condition. In addition, when the pair of through holes 11 The small hole portion 11a is more reliably penetrated by a common processing method such as a sandblasting method, and when the through hole 11 is surface-formed into the conductive layer 33, it is considered that the minimum hole portion 11a is more efficiently utilized with the conductive material. It is preferable that the opening diameter of the smallest hole mountain is 50 to 150 #m, preferably 75 to 125 #m. The collective substrate 1 is considered to improve the heat dissipation of the semiconductor element mounting member BL, and the corresponding On the premise that the light-emitting element LE1 has a high output, it is preferable to set the thermal conductivity to be lOW/inK or more, preferably 8 〇w/mK or more, more preferably 150 W/mK or more, and consider both mechanical strength and the like. In the case of other physical properties, manufacturing costs, and the like, the thermal conductivity of the collective substrate 最好 is preferably set to be 300 W/mK or less. Further, the collective substrate 1 is considered to prevent expansion or contraction due to thermal effects such as driving of the element. When excessive stress is applied to the light-emitting element LE1, and the element LE1 is broken or the joint is detached, the thermal expansion coefficient is preferably set to 10 χ 10 - ν or less. In addition, other physical properties such as mechanical strength, manufacturing cost, and the like are considered. premise The thermal expansion coefficient of the collecting substrate j is preferably set to 4χ1 (Γδ~7xl (T6/°C.) The material of the collecting substrate 1 that satisfies these conditions is as follows: A1 n, Al2〇3, SiC, Si—, BeO Insulating ceramics such as BN. Among them, in particular, in order to achieve high thermal conductivity, it is preferable to use AlN and SiC, and it is preferable to use, for example, A1N, in order to reduce the difference in thermal expansion coefficient between the optical element and the light-emitting element LE1. A12〇3. If the cost is set as the top priority, it is best to use A 1 2〇3 〇326\i|^\94\94145509\TF968049 29 200824058 Referring to the above figures, the master of the above-mentioned collective substrate The semiconductor element mounting electrode layer 3 is formed on the surface 21, and the connection electrode layer 32 between the members of the fish is formed on the external connection surface 22, and the two 'Terminal layers 31 and 32 are connected to each other on the inner surface of the through hole u. Conductive layer 33. Then, the smallest hole portion 11a of the through hole 11 is filled by the deposition of the two electric materials 3 3 a forming the conductive layer 33, and the beacon hole 11 'the dynasty collective substrate thickness before the insulating member 2 is divided The state of the direction is closed. In this case, when the light-emitting element LE1 is mounted on the electrode layer 31 and sealed, the illuminant and/or the protective resin FR can be prevented from leaking through the through-hole u and leaking to the back side. For example, the main assembly of the light-emitting element LE1 on the collective substrate can be omitted. In the specific region on the side of the surface 21, a troublesome procedure for the limited sealing is applied, and the entire surface can be sealed by the above-mentioned phosphor and/or protective resin, so that the size of the photodiode constituting member 1-2 can be further reduced. The thickness of the collective substrate} in the thickness direction of the minimum hole portion 11a filled with the conductive material 33a is preferably set to 1/5 〇 to I" _ 2 of the thickness of the collective substrate 。 7. The right thickness t is the collective substrate (thickness t < When it is 1/5 inch or more, it is possible to prevent the closed through hole from falling off due to its own weight and the like, and the phosphor and/or the protective resin FR leak to the side of the external connection surface 22. In addition, if the thickness ti is 1/2 or less of the thickness t集合 of the collective substrate, the exposed area of the conductive layer 33 on the external connection 22 side can be ensured by the minimum hole portion 11a, and the tin can be sufficiently filled. In addition, it is considered to increase the exposed area of the conductive layer with the function of filling the tin-forming portion, and to prevent the weight of the tin-forming portion from being sealed, and to create a 326\$employee file\94\94145509VTF968049 200824058 = : The through hole n is detached, and the condition of the glory body and/or the protective resin / 6 'external connection surface 22 side occurs, and the minimum hole f 11a is filled with the material 31a. Seven, especially set as a collection base The thickness of the thickness of seven is better. The thickness t2 of the conductive layer 33 formed on the inner surface of the through hole 11 is preferably set to Q. 2]· G times of the opening diameter d of the hole portion 11a. The thickness t2 is up to the opening Ϊ2 2 times or more, when the inner surface of the through hole 11 is formed with a conductive layer 33, the name, the 'door, the small hole portion 11 & more efficiently, the material 31a is filled, etc.; 1 can more accurately prevent the phosphor And / or the protective resin FR is leaked, but if the thickness t2 exceeds the opening diameter d by 1 〇, the effect is better, and the excess conductivity is required, and the efficiency of the method name _ = mlla is reduced. Therefore, the thickness is reduced. ^ is preferably less than u times the size of the second. In addition, the main surface of the region la of the respective insulating members 2 in the conductive layer 2t#t substrate 1 is considered before considering that the minimum hole ratio is well filled with the conductive material. Each of the two semiconductor element mounting electrode layers 31 is formed in each of the two semiconductor element mounting layers, and is provided in an insulated state. Further, the collective substrate is also formed on the external connection surface 22 side of the domain U. The two external connections of the mother are powered on and set according to the insulation state. Therefore, the main / ^ faces in the direction of the face, so the main Two electrode layers 326 on the 21 side, the total file \94\94145509VTF968049 3 】 200824058 11, and the external connection surface 22 (four) two electric _ 32, the double-sided m of the substrate 1 is transmitted through the through hole; the D layer 3 32 will become The area Ia of the insulating member 2 is different from that of the inner surface of the insulating layer 2, and the conductive layer of the inner surface is connected to each other., ' ' ' / knife, say 'electrode layer 31 (the planar shape is formed into a slightly rectangular layer 3lb (From the side of the electrode layer 31 (1) ^1 = 1 square, and to the conductive layer 33 of the through hole n on the side of the main surface 21 and the inner surface of the beacon hole 11, forming an integral and mutually external 'electrode layer 32 (the planar shape is slightly rectangular, the hole U is partially overlapped on the side of the outer connecting surface 22), and the conductive layer 33 on the inner surface of the beacon hole 11 is also integrally formed and connected to each other. The total area of the electrode layers 32 provided on the external connection surface 22 is preferably set to be 3% or more in proportion to the area of the external connection surface 22. Thereby, the light-emitting diode constituting member LE2 is mounted on the semiconductor element. When the electrode layer 32 on the side of the connection surface 22 and the sealing layer 7 of the light-emitting diode LE3 (or the electrode layer provided on the substrate of the surface light-emitting body) are surface-mounted by soldering, the semiconductor element can be sufficiently ensured. Since the heat dissipation path between the component seals 7 (or the substrate) is mounted, the output of the light-emitting diode LE3 can be increased. In addition, the electrode layer 32 is considered on the premise that the heat dissipation path is further ensured. The total area is preferably 5 or more in terms of the area ratio of the outer connecting surface 22, and more preferably 70% or more. However, when it is considered that two or more of the 23⁄4 pole layers 32' are formed to face each other in the direction as described above, the moon-filled blade is lifted before the insulation between the two electrode layers 32 is ensured, and the electrode layer 32 is 3%. Total file\94\94145509\TF968049 200824058 r〇r;. The ratio of the area of the external connection surface 22 is preferably set to the electrode layer 3, and the conductive layer 33 is as follows: :r:r, etc. and may form a single layer structure, or a double layer 31, 32 may be patterned. The method of formation is also "the above method. In the electrode; A1 or A1 alloy, etc.: from::: set = 竑, ... short-length to short-wavelength light below 450nm and superior reflectivity' It helps to improve the luminous efficiency of the reverse-emitting element LE1 when combined with fluorescence. "Short wavelength when white light is emitted: layer = gold is placed: Λ is t-electric material: 'and forms a single-layer structure; When layer 31 is the outermost layer, 1 also has a slightly reflective layer. Further, on the surface of the electrode layer 32, a solder mating bonding layer composed of Au or the like as described above may be formed by using Au as a conductive material and forming an electrode layer of a single layer structure, and = The top layer of the electrode layer 32 of the ΐ structure can be omitted, and the pair of bonding materials can be omitted for use in the above-mentioned collective substrate! The semiconductor element mounting member 搭载 for mounting the light-emitting element LE1 for a semiconductor element is manufactured, and the light-emitting diode constituent member LE2 is manufactured at the same time, and the substrate can be assembled! The light-emitting element ui is mounted on each of the electrode layers 31 of the respective layers, and the entire surface of the collective substrate 1 is sealed with a phosphor and/or a protective resin FR of the sealing material, and then the assembly is removed by dicing or the like. The area lb of the substrate i. According to this, 326\||ig\94\94145509\TF968049 33 200824058 : = = The semiconductor element mounting member BL is formed by self-separation, and the light element: ": / 3 households 1 shows the light-emitting diode constituent member LE2. Mounted by the electric SL welding of the semiconductor element mounting member Μ + pole layer 31 and the 弁 弁 τ τ τ τ τ τ τ τ τ : : : : : : 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极When using the solder used in the subsequent step, it is preferable to use the Au-sn system and Au_Ge with a higher melting point under the rigid edge of the package body 7 or the substrate. In addition, the 'light-emitting element LE1 may be mounted on the semiconductor element mounting member BIj without using the 烊μ 吏 UB bump. Further, after the light-emitting element LE1 is soldered or connected to the semiconductor element mounting member BL, Further, the light-emitting element electrode layer 31 is connected by a soldering wire. / The protective resin for sealing the optical element LE1 can be used, for example, various protective resins known in the art, such as the diarrhea system. And the tolerance to ultraviolet light, etc., it is best to make In addition, the 'fluorescent body has a known fluorescent body that emits white light in combination with a light-emitting element LE1 that emits a wavelength of _four or less, particularly a short-wavelength light of 450 nm or less. When the phosphor and the protective resin are used, the light-emitting element (8) mounted on the electrode layer 31 is first sealed with a glare body, and then sealed with a protective resin so as to cover the glare body. In addition, a phosphor and a protective layer can also be used. The mixture of the resin is sealed. The area of the semiconductor element mounting member BL (in other words, the area of the main surface 21 and the outer connecting surface 22 of the insulating member 2 in this example) is preferably the main surface 326\total file\94\94145509\TF968049 34 In 200824058 21, the area of the light-emitting element LE1 mounted on the main surface 21 (1 to 1 to 4 times of the main surface 21. When the semiconductor element mounting member accumulates the scene = product) is four times larger than the area (8), the (4) aperture can be minimized: With this phenomenon, it is impossible to treat a wafer having a hair-emitting element formed by a semiconductor element mounting == two: illuminating element as a single component, and in a package 7 of an assembly or an xS one-pole LE3. Or mounted on; In addition, if the semiconductor element mounting member BL is too large: =: The material wave material generated when the element LE1 is defective is almost indistinguishable. The second part of the package is described by a material having a high thermal conductivity. It is preferable to reduce the area even if it is within the above range. In other words, under the premise that the semiconductor element mounting member 豇3 is less wasted, in the above range, special!: ί 2 light When the area of the LE1 is 3.5 times or less, it is preferably 3 times or less. If the area of the semiconductor element mounting member BL is smaller than 1.1 times the area of the light-emitting element, it is difficult to implement the light-emitting element! ^E1's carrying work. ί 1 卜 don't be able to use the protective resin apricot knife back seal on the side of the side of the light-emitting element L E1. In addition, in consideration of improving the workability of mounting, and more reliably sealing the light-emitting element LE1 with a protective resin or the like, the area of the semiconductor-mounting member BL is set to be the area of the light-emitting element LE1 in the above range.丨. 3 times or more is better, especially 15 times or more is better. The thickness of the insulating member 2 is preferably set to 〇·1 to 1 mm, especially 0.2 to 0, in consideration of sufficiently ensuring the strength and minimizing the volume of the semiconductor element mounting member BL of 326, the total file of the first file, and the volume of the semiconductor device mounting member BL. 5mm is preferred. A plurality of the above-described light-emitting diode constituent members LE2 are mounted on a substrate to form a surface light-emitting body. Further, the light-emitting diode constituent member LE I is used as the final form of the light-emitting diode element. For example, solder mounting may be performed by means of reflow or the like at a desired position on a circuit board such as a printed circuit board, a backlight constituent member of a liquid crystal, or the like, and may have a function as a light-emitting diode.

再者,參照圖14,將上述發光二極體構成構件搭 載於在具有凹部7a之封裝7的凹部7a底面所設置之2個 !極層72上’並將凹部7a的開口 7b利用密封覆蓋或透 鏡LS(其由可使從發光二極體構成構件LE2所發出的光穿 透過之材料所形成)密封,可獲得發光二極體LE3。Further, referring to Fig. 14, the light-emitting diode constituent member is mounted on the two electrode layers 72 provided on the bottom surface of the concave portion 7a of the package 7 having the concave portion 7a, and the opening 7b of the concave portion 7a is covered with a seal or The lens LS (which is formed of a material through which the light emitted from the light-emitting diode constituent member LE2 can pass) is sealed, and the light-emitting diode LE3 can be obtained.

發光二極體構成構件LE2的搭载係將半導體元件搭載 構件BL的電極層32、及封裝7的電極@ 72、透過焊料層 SL1焊接而實施。此時,部分的溶融悍料在貫通孔^中 形成於第2推拔面lle的内面上,並反折於在絕緣構件2 :3所裸露出的導電層33 ’而形成填錫SL2,因而提 升女裝的可靠度。 封衣7具備有:基板7Q(其在圖中的上面側形成電極層 72)、以及反射構件71(其積層於上述基板7()上,並且有 = 的通孔)。此外,反射構件71的通孔㈣從 氏面側朝開口 7b側向外面供士的& 4丄 J门外面擴大的盆狀,並將其内面設定 a所以’使從發光二極體構成構件LE2所發 出的光,利用上述反射面71a的表面朝開"b方向反射, 326聰檔\94\94145509VTF968049 36 200824058 並通過透鏡LS,更有效率地射出於封裝7外面。 基板70使用陶瓷基板、玻璃環氧基板等絕緣性且具耐 熱性的基板。此外,反射構件71為將從發光二極體構成 構件LE2所务出的光政率佳地反射,使用其整體或至少反 射面71a由金屬所形成者。 亦可將上述圖9之貫通孔u整體,形成於進入集合基 板1的區域la内之位置中。此情況下,因為推拔面llc 不致裸露出於絕緣構件2側面23,因而無需使在該推拔 f山上所形成的導電層33具有填錫形成部功能。故, 貝通孔11亦可由導電材料33a完全填滿。 -圖,i5戶!Γ係本發明半導體元件搭載構件B L實施形態另 歹| ’貫通孔n朝圖17中v箭頭方向的部分放大側視 :同I /,示係在貫通孔11内面形成導電層33之前, 導體的狀錢視圖。圖17所示係上述例子的半 t件域構件此主面2丨側之俯視圖;圖18所示係 的仰視圖。圖19所示係上述例子中,將 上分二ί構件此母材的絕緣構件2從集合基板1 19的=匕丨通孔11的部分放大俯視圖’·仙所示係圖 的β-β線剖視圖。 =該等圖式’本例子的半導體元件搭載構件扯除貫 的半導η ^ 之’參照圖17、圖18,本例子 2(直單面:定二t構件BL具傷有:矩形平板狀絕緣構件 早又疋為發光元件搭载用的主® 21,而背面則設 326\總檔\94\94145509VTF968049 200824058 _2^兵其他構件間連接用的外部連接面22)、發光元件祝 ., 層31(其在上述絕緣構件2的主面21上, 他5 = Γ方向隔開’且設定為絕緣狀態)、以及盘苴 互朝面方么個電極層32(其在外部連接面22上相 向隔開,且設定為絕緣狀態)。 4=的、2個電極層3卜與外部連接面22侧的2 而认θ 刀別透過貫通孔U(其在絕緣構件2表背雔 面的對應電極層間,分別舞:2表月雙 μ外周緣侧各形成於i個地方緣構件 構”内面所形成的導電層33:=度方向貝一 間::之1ΐ:面形狀呈略矩形狀,且除2個電極層31 31:ΧΤπΓΒ1^^^"" 21 此夕r 1 的導電層33形成—體並相互連接。 卜,/、平面形狀形成略矩形狀的電極層32、與延 極層32b(係從上述電極層32之相卜臭<D〇 ' 电 、电位層32之一側邊32a朝貫通孔u 圍)及貝通孔11内面的導電層33形成一體並相互連接。 構:^二^體凡件搭載構件BL、以及發光二極體構成 夢十^主面21上搭載發光元件LE1,且利用榮光 體及/或保護樹脂密封)的製作方面,可如前所舉例子般, 準備具有包含複數個絕緣構件2之大小的集合基板卜將 ^集合基板1利用邊界線L區隔出成為絕緣構件2的複 數個區域la,而於既定位置處形成貫通孔η,且單面形 成電極層31並在背面形成電極層32,更在貫通孔η内 326\總檔\94\94145509\TF968049 38 200824058 面形成f電層33 ’經在電極層31上搭載發光元件LE1, 且利用岔封材的螢光體及/或保護樹脂 後 割各區域la。 4之後,再分 蒼照圖15、圖16、圖19及圖2〇,形成各貫通孔心 内面’分別由第1與第2等2個推拔面Ub、n 其中,第"•拔面m從絕緣構件2的主面21側(:中成的 上面側)起’朝向最小孔部lla(其設置於絕緣構 产The mounting of the light-emitting diode constituent member LE2 is performed by soldering the electrode layer 32 of the semiconductor element mounting member BL and the electrode @72 of the package 7 through the solder layer SL1. At this time, part of the molten material is formed on the inner surface of the second push-out surface lle in the through hole ^, and is folded back to the conductive layer 33' exposed in the insulating member 2:3 to form the filled tin strip SL2. Improve the reliability of women's wear. The seal 7 is provided with a substrate 7Q (which forms the electrode layer 72 on the upper side in the drawing), and a reflection member 71 (which is laminated on the substrate 7 () and has a through hole of =). Further, the through hole (four) of the reflecting member 71 is formed from the side of the surface toward the side of the opening 7b toward the outside of the basin of the outside of the door, and the inner surface thereof is set to a so that the member is formed from the light emitting diode. The light emitted by the LE2 is reflected by the surface of the reflecting surface 71a toward the open "b direction, and 326 is visibly\94\94145509VTF968049 36 200824058 and passes through the lens LS to be more efficiently emitted outside the package 7. As the substrate 70, an insulating and heat-resistant substrate such as a ceramic substrate or a glass epoxy substrate is used. Further, the reflecting member 71 is preferably reflected by the light-receiving rate which is obtained from the light-emitting diode-constituting member LE2, and is formed of metal by using the entire or at least the reflecting surface 71a. The through hole u of the above-mentioned Fig. 9 may be entirely formed in a position into the region la of the collective substrate 1. In this case, since the push-out surface llc is not exposed to the side surface 23 of the insulating member 2, it is not necessary to have the function of filling the tin-forming portion of the conductive layer 33 formed on the push-out mountain. Therefore, the beacon hole 11 can also be completely filled with the conductive material 33a. - Figure, i5 household! Γ 半导体 半导体 半导体 半导体 半导体 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Shaped money view. Fig. 17 is a plan view showing the side of the main surface 2 of the half-piece member of the above example; and Fig. 18 is a bottom view of the system. In the above-described example, the insulating member 2 of the base material is enlarged from the portion of the 基板 through hole 11 of the collective substrate 1 19 by the portion of the 匕丨 through hole 11 of the collective substrate 1 19 . Cutaway view. = "The semiconductor element mounting member of the present example is detached from the semiconductor guide η ^" with reference to Figs. 17 and 18, and the present example 2 (straight single-sided: fixed two-t member BL has a rectangular plate shape The insulating member is turned into the main ® 21 for the light-emitting element, and the back is 326\the total file\94\94145509VTF968049 200824058 _2^The external connection surface for connecting other components of the soldier 22), the light-emitting element, layer 31 (on the main surface 21 of the above-mentioned insulating member 2, he 5 = Γ direction is spaced apart and set to an insulating state), and the electrode layers 32 facing each other (which are opposite each other on the outer connecting surface 22) On, and set to insulation state). 4=, 2 electrode layers 3 and 2 on the outer connecting surface 22 side, and the θ knife passes through the through hole U (which is respectively danced between the corresponding electrode layers on the back surface of the insulating member 2: 2 watch month double μ The outer peripheral side is formed on the inner surface of the i-side member structure "conductive layer 33: = degree direction of a room:: 1 ΐ: the surface shape is slightly rectangular, and except 2 electrode layers 31 31: ΧΤ π ΓΒ 1 ^ ^^"" 21 The conductive layer 33 of the eve r 1 is formed into a body and connected to each other. 卜, /, the planar shape forms a slightly rectangular electrode layer 32, and the extension layer 32b (from the electrode layer 32) The conductive layer 33 is formed integrally with the conductive layer 33 on the inner surface of the beacon hole 11 and is connected to each other. BL and the light-emitting diodes constitute a dream device, and the light-emitting element LE1 is mounted on the main surface 21, and is sealed by a glazing body and/or a protective resin. As in the previous example, it is prepared to have a plurality of insulating members. The collective substrate of the size of 2 is divided into a plurality of regions of the insulating member 2 by the boundary line L. La, and a through hole η is formed at a predetermined position, and the electrode layer 31 is formed on one side and the electrode layer 32 is formed on the back surface, and an electric layer is formed on the surface of the through hole η 326 \ total file \94\94145509\TF968049 38 200824058 33' After the light-emitting element LE1 is mounted on the electrode layer 31, the phosphor and/or the protective resin of the enamel sealing material are used, and then the respective regions la are cut. After that, the image is further divided into Fig. 15, Fig. 16, Fig. 19 and Fig. 2〇, the inner surface of each of the through-holes is formed by the first and second two push-out surfaces Ub and n, respectively, and the first "• facet m is from the main surface 21 side of the insulating member 2 (: the upper surface of the middle Side) from the smallest hole portion 11a (which is disposed in the insulating structure)

方向的1個地方,並將開口寬度d設定為較小於貫通子: 11的其他部分’且平面形狀呈長圓形),且開 漸變小狀態形成推拔狀,並在主面21處形成長圓又形^ 口。此外’弟2推拔面llc從絕緣構件2的外部連接面 2 2侧(圖中的下面側)起,朝向上述最小孔冑i i &,並依開 口寬度逐漸變小狀態形成推拔狀’且在外部連接面2 形成長圓形開口。 再者上述貝通孔11形成跨越區域ia(其係利用集合 基板1上的邊界線L所區隔出的2個成為半導體元箨 構件BL的區域)、與區域lb(其係在該二個區域1&間利 用切割等去除的區域)的狀態。所以,當在貫通孔u内面 形成導電層33之際,最小孔部Ua的部分利用形成導電 層33的導電材料33a之沉積而填滿,且上述貫通孔n在 圖19、圖20所不分割丽的狀態下,朝集合基板i厚度方 向呈封閉狀態。 所以,當在電極層31上安裝發光元件LE1並密封之際, 可防止螢光體及/或保護樹脂FR經由貫通孔丨1洩漏於背 326\總檔 \94\94145509\TF968049 39 200824058 面侧的情況發生,例如 LE1的主面21側之=略對巿&基板1搭载發光元件 开斂 彳寸疋區域限定性密封的麻焴葙床 可整面均利用上述 了的麻煩転序’而 * , ^ 先肪及/或保護樹脂FR密封,Και 更加促進發光二極 κ山封因而可 構成構#LE2的小型化。 丹者’利用切割箄f t 一圖15〜圖二T 去除而分割各區域 的絕緣構件2之侧面2丁3, +導體元件搭載構件乩 形成的導電層33,由門 述弟2推拔面llc内面所 出的導電層33且有埴L口 1Η裸露出。因此,可使裸露 …有"錫形成部的功能,告一 構成構件LE2利用烊接而拨# 田、X —極體 體m的縣3上之^载於其他構件(例如發光二極 部連接用電㈣32二 利用所形成的填錫辅助外 I逆接用电極層32,可提升安裝可靠度。 具有圖示形狀的貫通孔n 換古之,/隹入亦取好利用喷砂法形成。 脸术板1成為外部連接面22的單面側上 將對應於貫通孔n開口且未被 , F m 尤且娱所保濩而稞露出的 £域形狀設定為長圓形,再利时砂法對集合 裸露出的區域施行選擇性的厚度 : 斤 品11 门+ 沒万向牙孔,形成第2推拔 ’在成為主面21的背面側’亦同樣地,將對 μ於貝通孔11開口且未被光阻膜所保 形狀設定為長圓形’再利用喷砂法對集合基:二:= ^區域施行選擇性的厚度方向穿孔,形成第!推I面 b。而利用喷砂法施行穿孔的特徵係隨穿孔的推進,其 開口尺寸逐漸變小,因而可形成圖〗 ㈣n。 成_、圖2〇所示形狀的 326\|Ιί|\94\94145509\TF968049 200824058 貝通孔11的各部位尺寸如同上述例子的相同理由,最 好設定在同樣的範圍内。換言之,參照目15、16,最小 =部Ua在絕緣構件2厚度方向的形成位置依主面21距 -最小孔部11 a的距離h表示,最好在超過上述絕緣構件2 厚度to的〇倍,且2/3倍以下的範圍a,尤以絕緣構件2 厚度^的1/2倍以下為佳。此外,5#m〜5〇#m左右更佳。 另外,最小孔部Ua的開口寬度d最好設定為1〇〜200 尤以^〜15〇/Zm為佳,更以75〜125㈣為更佳。另外,此 炎所:開口覓度d」指在矩形狀中央部二端,相當於分 別將半圓連接之形狀的長圓中,連結二端半圓中心點之中 心線正交方向的寬度。 最小孔部11a中利用導電材料33a填滿的絕緣構件2厚 度方向的厚度tl,最好設定為絕緣構件2厚度t。的 1/50〜1/2倍,尤以1/2〇〜1/5倍為佳。此外,在貫通孔u 内面所=成的導電層33厚度最好設定為最小孔部ila 馨之,口寬度d的〇·2〜1·〇倍,尤以〇·3〜〇·5倍為佳。 貝通孔11以外的各部位尺寸,亦如前所舉例子的相同 理由,最好設定於相同範圍内。換言之,絕緣構件2的主 ,21與外部連接面22之面積,最好設定為主面21上所 =載鲞光兀件LE1面積(在主面21上的投影面積)之丨·卜4 尤以h 3〜3· 5倍為佳,更以1· 5〜3.0倍為更佳。此外, 、、、巴、、彖構件2的厚度最好設定為〇· ι〜ι_,尤以〇 2〜〇 5_ 為佳。 · 在外邛連接面22上所設置電極層32的面積合計,佔上 326\$i^f\94\94145509\TF968049 200824058 =外部連接面22之面積的比例,最好設定 尤以50%以上為佳,更以7卟μ盔处 上 -最好在m以下。_上為佳。此外,上述比例 -電極層3卜32及導電層33均可使用f知周知 電性優越金屬材料等,採用諸泰 ' ' 法、濺鐘法等物理基斧、去等箄鑛法、或真空蒸鍍 造、或雙層以上的屬化法’形成單層構 由Ag、Α1赤Α1入人美。層31最好至少其表面 # &孟等所形成,而電極層32最好至少苴 響表面由Au所形成。 八 絕緣構件2最好利用熱導率_κ以上、 數10x10—6/。〇以下的陶瓷所來点 人 9 . , v 7門瓦所形成,而含有陶瓷製絕緣構件 έ :例子之半導體元件搭載構件BL的製作,最好係將 、、、巴緣構件2母材的陶兗前驅體(陶竟胚 板狀集合基板1之後,再經由對上述集合基板“灸::成 -32 缘=7=體構成構件LE2如上述’將具有涵蓋複數個絕 緣,件2大小的集合基板1,區隔出複數個區域la,並在 既疋位置處形成貫通不I】1 在背面上㈣ΐ 早面上形成電極層3卜 在月面上形成電極層32,在貫通孔u内面形成導 33 1時^將上述貫通孔11的最小孔部11a,利用^ 二積:填滿的狀態下’於電極層31上搭载發光 個別分割出各區域la,可在形成半導趙元件二之二: 326\|lit\94\941455O9\TF968049 42 200824058 之同時製得。 再者’將上述發光二極體構成構件LE2複數個 ^上,可構成面發光體。此外,發光二極體構成構件;^ ’、可使用為發光二極體70件的最終形態。例如在 基板等電路基板、液晶的背光構成構件等所需位电 ^焊等方法崎焊料絲,亦可具有發光二極體㈣ ,者,將上述發光二極體構成構件⑽,利用焊·如 干接格載於在圖14所示封裝7的凹部以底面^ 個電極層72上’並將凹部7a的開口 7b ; : 2 ,(其由可使從發光二極體構成構件L心 牙士透過之材料所形成)密封,可獲得發光二極體如。' 吩为的熔融焊料在貫通孔u中形成於 内面上,並反折於在絕緣構件2側 面llc 層33,而形成填錫SL2,因而提升安裝的可靠产、包 如圖21、圖22所示,貫通孔u内面亦可米=同 10所不之圓錐推拔狀、與圖19、圖20所示之推J 圖 合形狀。換言之,圖式貫通孔u内面之2 = llb(其分別設置於成為半導體發光元 盖推拔面 接之2個區域la内)、及i個第2推拔 ::鄰 =拔面广上述2個區域〗"及其中(間二2 b而权置’亚透過上述2個第!推拔面 ^ 個區域内所設置的2個最小孔部Ua而連貫 上述中’2個第i推拔面llb分別從絕緣構件2的主面 326V總槽 \94\94145509\TF968049 43 200824058 21 ’朝向平面形狀呈圓形的2個最小 孔部na’形成開口直徑呈逐漸變小狀態的圓錐推拔狀, 並在各自的區域la内,於主面21處形成圓形開口。 第2推拔面11c從絕緣構件2的外部連接面圖中的 下側)起,朝向上述2個最小孔部…,其平面形狀形成 在矩形狀中央一端’分別形成與上述2個最小孔部山呈 同心:半圓連貫的長圓形’且形成如同之前所定義的長圓 開口寬度呈逐漸變小狀能的始妒业门+ Μ〗叙甘击问 狀’同時依跨越相鄰2個 £域1 a、與其中間的區域〗h夕业# 上形成長圓形開口。 之狀怨,在外部連接面22 上述貫通孔11亦最好利用喷砂法 合基板1成為外部連接面22的罝…風換3之’在集 開口,且未被光阻膜所:二的裸:面::,對應於貫通孔11 =:=對集合基板1中裸露出的區域,施行 Γ==穿孔’形成長圓形第2推拔面UC,同 ^ 在成為主面21的接;丨丨 丄的月面侧,在對應於貫 且未被光阻膜所保護而裸露出的區域二 口’ 形,再利用喷砂法對集合基板1中裸露出的U ^ = 擇I·广予度方向牙孔’形成在第2推 上分別各形成1個(合計2個 ❺長固一鈿 法施行穿孔的特徵在於 的推技面llb。利用喷砂 小,因此形成如圖L 022= Μ開口尺寸將逐漸變 上述貫通孔U在夂 的形狀貫通孔η。 -的部分利用形成導;:::=33之際,最小孔部 ¥電層33的導電材料33a沉積而填 326\總槽\94\94145509VTF968049 44 200824058 :,因因:分割前在集合基…於厚度方向上呈封閉狀 二^而可防止螢光體及/或保護樹脂⑼透過貫通孔u 的情況發生。此外,當將相鄰區域1&間 -或lb利用切割等方式去除,而將 ,貫通W中在第2推拔面n:= 層33’稞露出於絕緣構件2側面23,因而可使 ^電層33具有填錫形成部的功能 们例子的相同理由’最好設定在同樣的範圍内。 在3=主=僅揭限於上述所説明的各圖式例’ 【圖式簡=】㈣内,可進行各種設計變更。 本發明集合基板之實施形態一例,以攝像元件搭 载I,巴緣構件為基礎的集合基板部分放大俯視圖。 =2為上述集合基板中,貫通孔的部分放大剖視圖。 分放大職圖。土板刀^而成的絶緣構件中’貫通孔的部 圖4為絕緣構件的主面側俯視圖。 件:視5圖為在主面上接合框體而形成的半導體元件搭載構 圖6為絕緣構件的外部連接面側仰視圖。 圖7為在半導體元件搭载構件之絕緣 面 ^载區域中’搭載半導體元件的攝像元件,且在框^ 接&透光性蓋體而形成的攝像裝置剖視圖。 326\總檔\94\94145509VTF968049 45 200824058 、圖8為本杳明集合基板實施形態另一例,以發光元件搭 载用、、、&緣構件為基礎的集合基板部分放大俯視圖。 圖9為上述集合基板中,貫通孔的部分放大剖視圖。 圖1 〇為由上述集合基板分割而成的絕緣構件令,貫通 孔的部分放大剖視圖。 、 圖11為絕緣構件的主面側俯視圖。 圖12為絕緣構件的外部連接面側仰視圖。 ,13為在半導體元件搭載構件的絕緣構件主面上 件Γ:_,並利用營光體及/或保護樹脂 在封的發先二極體構成構件剖視圖。 極為圖將發光二極體構成構件搭载於封裝上的發光二 朝=二本=二導:搭載構件實_ 圖㈣在貫通 的狀態側視圖。 成^層之n目同貫通孔 圖圖17為上述例子之半導體元件搭载構件的主面側俯視 圖18為外部連接面側的仰視圖。 構Γ在=子二導體元件搭載構件之母封的絶緣 圖,二=:::r分放大俯梘圖。 圖21為貝通孔變化部的放大俯視圖。 圖22為圖2〗中的β—β線剖視圖。 326\總檔\94\94145509\TF968049 46 200824058One position of the direction, and the opening width d is set to be smaller than the through portion: the other portion of the '11 and the planar shape is an oblong shape), and the open-graded small state forms a push-out shape, and is formed at the main surface 21 The long circle is shaped like a mouth. Further, the "different 2 pull-out surface 11c" is formed from the side of the outer connecting surface 2 2 of the insulating member 2 (the lower side in the drawing) toward the above-mentioned minimum hole 胄 ii & and is formed in a state in which the opening width is gradually reduced. And an oblong opening is formed in the outer connecting surface 2. Further, the above-described beton hole 11 forms a spanning region ia (the two regions which are separated by the boundary line L on the collective substrate 1 and which are the semiconductor elementary members BL), and the region lb (which is attached to the two The state of the area removed by cutting or the like between the regions 1 & Therefore, when the conductive layer 33 is formed on the inner surface of the through hole u, the portion of the minimum hole portion Ua is filled with the deposition of the conductive material 33a forming the conductive layer 33, and the through hole n is not divided in FIGS. 19 and 20. In the state of Li, the thickness of the collective substrate i is closed. Therefore, when the light-emitting element LE1 is mounted on the electrode layer 31 and sealed, the phosphor and/or the protective resin FR can be prevented from leaking through the through-hole 丨1 to the back side 326\main file\94\94145509\TF968049 39 200824058 The situation occurs, for example, on the main surface 21 side of the LE1 = a slight 巿 & the substrate 1 is equipped with a light-emitting element, and the paralyzed bed of the region is limited to the entire surface. * , ^ First fat and / or protective resin FR seal, Και more promotes the light-emitting diode κ mountain seal and thus can constitute the structure #LE2 miniaturization. The Dan's side of the insulating member 2 of the respective regions is divided by the cutting 箄ft-FIG. 15 to FIG. 2T, and the conductive layer 33 formed by the conductor element mounting member , is divided by the gate 弟 2 The conductive layer 33 on the inner surface is exposed and exposed. Therefore, it is possible to make the function of the bare-faced <tin forming part, and the member LE2 is spliced and dialed #田, X-polar body m in the county 3 on other components (for example, the light-emitting diode The connection power (4) 32 is used to form the tin-assisted external I reverse electrode layer 32, which improves the mounting reliability. The through-holes having the shape shown in the figure are replaced by the ancient ones, and the intrusion is also formed by sandblasting. The face panel 1 is formed on the one-side side of the external connection surface 22 so as to correspond to the opening of the through-hole n, and the shape of the field which is exposed by the F m is also set to an oblong shape. The sand method applies a selective thickness to the bare exposed area: 1 door + no universal hole, forming a second push 'on the back side of the main surface 21'. Similarly, the pair is in the pass. The hole 11 is open and is not set to be oblong by the shape of the photoresist film. The etched sandblasting method is used to apply a selective thickness direction perforation to the aggregate: two: = ^ region to form the first! push I face b. The characteristics of the perforation by the sand blasting method are gradually dimmed with the advancement of the perforation, so that it can be shaped Forming 〖 (4) n. 326, 图 | | 图 图 图 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 326 贝 贝 贝 贝 贝 贝In other words, referring to the objects 15, 16 , the position where the minimum portion Ua is formed in the thickness direction of the insulating member 2 is expressed by the distance h of the main surface 21 from the minimum hole portion 11 a, preferably exceeding the thickness to of the insulating member 2 The range a of 2/3 times or less is preferably 1/2 or less of the thickness ^ of the insulating member 2. Further, it is preferably about 5#m to 5〇#m. Further, the opening of the smallest hole Ua The width d is preferably set to 1 〇 to 200, especially preferably 〜15 〇/Zm, and more preferably 75 to 125 (four). In addition, the swell: the opening degree d" refers to the two ends of the rectangular center portion. In the ellipse corresponding to the shape in which the semicircles are connected, the width in the direction orthogonal to the center line of the center point of the two end semicircles is connected. The thickness tl in the thickness direction of the insulating member 2 filled with the conductive material 33a in the minimum hole portion 11a is preferably It is set to 1/50 to 1/2 times the thickness t of the insulating member 2, particularly preferably 1/2 〇 to 1/5 times. It is preferable that the thickness of the conductive layer 33 formed on the inner surface of the through hole u is set to be the minimum hole portion ila, and the width d of the port is 〜·2 to 1·〇 times, preferably 〇·3 to 〇·5 times. The size of each portion other than the through hole 11 is preferably set in the same range for the same reason as exemplified above. In other words, the area of the main portion 21 and the outer connecting surface 22 of the insulating member 2 is preferably set to the main surface. 21: The area of the light-emitting element LE1 (the projected area on the main surface 21) is particularly preferably h 3~3·5 times, and more preferably 1. 5 to 3.0 times. Further, the thickness of the member, the bar, the barium member, and the crucible member 2 is preferably set to 〇· ι 〜ι_, and particularly preferably 〇 2 to 〇 5_. · The total area of the electrode layer 32 provided on the outer connecting surface 22 is 326\$i^f\94\94145509\TF968049 200824058 = the ratio of the area of the outer connecting surface 22, preferably set to 50% or more. Good, more on the 7卟μ helmet - preferably below m. _ is better. Further, the above-mentioned ratio-electrode layer 3b and the conductive layer 33 may be made of a known metal material such as a sapphire method, a sputtering method, or the like, or a vacuum. The vapor deposition or the two-layer or more of the grouping method 'forms a single layer structure from Ag, Α1 赤Α1 into the human beauty. Preferably, layer 31 is formed by at least its surface # & Meng, etc., and electrode layer 32 is preferably formed of at least a surface which is formed of Au. Preferably, the insulating member 2 is made of a thermal conductivity _κ or more and a number of 10 x 10 -6 /. 〇 〇 〇 〇 〇 , , 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷 陶瓷After the ceramic scorpion precursor (the ceramic slab-like collective substrate 1), via the above-mentioned collective substrate "moxibustion:: -32 edge = 7 = body constituent member LE2 as described above" will have a plurality of insulation, the size of the piece 2 The collecting substrate 1 partitions a plurality of regions la and forms a through-hole at the 疋 position. On the back surface, the electrode layer 3 is formed on the front surface, and the electrode layer 32 is formed on the moon surface. When the guide 33 1 is formed, the minimum hole portion 11a of the through hole 11 is divided into the respective regions la by mounting light on the electrode layer 31 in a state where the second hole is filled, and the semi-conductive element 2 can be formed. Second: 326\|lit\94\941455O9\TF968049 42 200824058 is produced at the same time. In addition, 'the above-mentioned light-emitting diode constituent member LE2 is plurally formed to form a surface light-emitting body. In addition, the light-emitting diode constitutes The member; ^ ' can be used as the final form of 70 pieces of the light-emitting diode. For example, in a circuit board such as a substrate, a liquid crystal backlight, or the like, a solder wire such as a solder wire, or a light-emitting diode (4), the light-emitting diode component (10) may be soldered. The dry grid is carried on the bottom surface of the package 7 shown in Fig. 14 on the bottom surface of the electrode layer 72 and the opening 7b of the recess 7a; 2, which is made of a light-emitting diode forming member L-heart By forming a seal through the material, a light-emitting diode can be obtained. The molten solder is formed on the inner surface in the through-hole u, and is folded back on the side of the insulating member 2 to form a layer 33, to form a fill-in SL2. Therefore, the reliable production of the installation is improved. As shown in FIG. 21 and FIG. 22, the inner surface of the through-hole u can also be in the shape of a cone which is the same as the ten-thickness, and the shape of the push-up shown in FIG. 19 and FIG. In other words, 2 = llb on the inner surface of the through-hole u of the pattern (which is respectively disposed in the two regions la which are to be connected to the semiconductor light-emitting element cover), and i second push-out:: adjacent = wide-faced 2 Areas " and their (between 2 and 2 b and the right set) are set through the above 2 The two smallest hole portions Ua are connected to the above-mentioned two 'ith i-th push-out surfaces 11b from the main surface 326V of the insulating member 2, respectively, the total groove \94\94145509\TF968049 43 200824058 21 'the two circular shapes that are circular in shape The hole portion na' is formed in a tapered shape in which the opening diameter is gradually reduced, and a circular opening is formed in the main surface 21 in the respective regions la. The second push-out surface 11c is connected from the outer surface of the insulating member 2. The lower side of the figure is oriented toward the two smallest holes... the planar shape is formed at the central end of the rectangular shape to form a concentric with the two smallest holes, respectively: semi-circularly long ovals and formed like The width of the long circular opening defined earlier is gradually becoming smaller and smaller. The initial 妒 门 + 叙 叙 〗 〖 〗 〖 〗 〖 〗 〖 〗 〖 〗 〖 〗 〖 〗 〖 Oval opening. In the external connection surface 22, it is preferable that the through-holes 11 are joined by the sandblasting method to form the external connection surface 22 of the substrate 1 (the wind is replaced by the 3' in the collector opening, and is not provided by the photoresist film: Naked: face:: corresponding to the through hole 11 =:= For the exposed area in the collective substrate 1, the Γ==perforation' is formed to form the oblong second push surface UC, and the same as the main surface 21 The side of the lunar surface of the crucible is in the shape of a region corresponding to the exposed portion which is not protected by the photoresist film, and the U ^ = selected in the collective substrate 1 by sandblasting. In the wide-angle direction, the perforations are formed on the second push, and each of them is formed by a total of two ❺ 固 固 固 施 施 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 = The opening size will gradually change the through hole U in the shape of the through hole η. The portion of the hole is formed by the guide;:::=33, the conductive material 33a of the smallest hole portion 33 is deposited and filled 326\ Total slot\94\94145509VTF968049 44 200824058 :, due to: the assembly base in the front of the split... in the thickness direction is closed, and the phosphor can be prevented. / or the protective resin (9) passes through the through hole u. Further, when the adjacent region 1 & or - lb is removed by cutting or the like, the second push surface n: = layer 33' is penetrated through W Since the enamel is exposed on the side surface 23 of the insulating member 2, the same reason as the function of the tin-filled portion can be set in the same range. It is preferable to set it in the same range. In the example of the embodiment of the present invention, an example of the embodiment of the collective substrate of the present invention is an enlarged plan view of the collective substrate portion based on the image sensor mounting I and the edge member. In the collective substrate, a cross-sectional view of a portion of the through hole is shown in an enlarged view. FIG. 4 is a plan view of the main surface side of the insulating member in the insulating member formed by the earth plate cutter. The semiconductor element mounting pattern 6 formed by bonding the frame on the main surface is a bottom view of the external connection surface of the insulating member. FIG. 7 is an image sensor in which the semiconductor element is mounted in the insulating surface region of the semiconductor element mounting member, and Frame ^ A cross-sectional view of an imaging device formed by a light-transmissive cover. 326\Total file\94\94145509VTF968049 45 200824058 FIG. 8 is another example of an embodiment of a collective substrate, and is used for mounting a light-emitting element, and an edge member. Fig. 9 is a partially enlarged cross-sectional view showing a through hole in the collective substrate. Fig. 1 is an enlarged cross-sectional view showing a portion of the through hole formed by the insulating member divided by the collective substrate. It is a top view of the main surface side of the insulating member. Fig. 12 is a side elevational view of the outer connecting surface of the insulating member. Reference numeral 13 denotes a cross-sectional view of a member of the insulating member of the semiconductor element mounting member, which is a member of the insulating member, and which is formed of a light-emitting body and/or a protective resin. In the extreme diagram, the light-emitting diode constituting member is mounted on the package, and the light-emitting two-way=two-book=two-conductor: the mounting member is _ (four) in a state in which it is penetrated. FIG. 17 is a plan view of the main surface side of the semiconductor element mounting member of the above-described example, and FIG. 18 is a bottom view of the external connection surface side. The insulation pattern of the mother seal of the sub-conductor element mounting member is constructed, and the second =:::r is used to enlarge the top view. Fig. 21 is an enlarged plan view showing a beton hole changing portion. Figure 22 is a cross-sectional view taken along the line β-β in Figure 2; 326\总档\94\94145509\TF968049 46 200824058

【主要元件符號說明】 1 集合基板 la 區域 lb 區域 2 絕緣構件 4 框體 5 金屬層 7 封裝 7a 凹部 11 貫通孔 11a 最小孔部 11b" 11c 推拔面(内面) lid 開口 21 主面 21a 元件搭載區域 22 外部連接面 23 侧面 31 電極層 32 電極層 33 導電層 33a 導電材料 70 基板 71 反射構件 71a 反射面 326\|»94\94145509\TF968049 47 200824058 72 電極層 BL 半導體元件搭載構件 、 FL 蓋體 . FR 螢光體及/或保護樹脂(密封材) L 邊界線 LEI 發光元件(半導體元件) LE2 發光二極體構成構件 LE3 發光二極體 • LS 密封覆蓋或透鏡 PEI 攝像元件(半導體元件) PE2 攝像裝置 SL1 焊料層 SL2 填錫 326\總檔 \94\94145509\TF%8049 48[Description of main components] 1 collective substrate la area lb area 2 insulating member 4 frame 5 metal layer 7 package 7a recess 11 through hole 11a minimum hole 11b" 11c push surface (inner surface) lid opening 21 main surface 21a component mounting Area 22 External connection surface 23 Side surface 31 Electrode layer 32 Electrode layer 33 Conductive layer 33a Conductive material 70 Substrate 71 Reflecting member 71a Reflecting surface 326\|»94\94145509\TF968049 47 200824058 72 Electrode layer BL Semiconductor component mounting member, FL cover FR phosphor and/or protective resin (sealing material) L boundary line LEI illuminating element (semiconductor element) LE2 illuminating diode constituting member LE3 illuminating diode • LS sealing cover or lens PEI imaging element (semiconductor element) PE2 Camera SL1 Solder layer SL2 Filled with tin 326\总档\94\94145509\TF%8049 48

Claims (1)

200824058 十、申請專利範圍: 1. 一種半導體元件搭載構件,其特徵在於 由陶瓷一體形成的絕緣構件,形成一面 載用之主面而背面為與其他構件間連接;=搭 =狀,同時分別具有貫通上述板之厚度方向 '内面形成從設於上述主面侧與外部連接面側開 上述厚度方向之-處所設置之最小孔部而開: 變小之推拔狀; 尺寸逐漸 面何體元件搭載用之電極層’形成於上述絕緣構件之主 形成於外部連接面;及 ,連接主面側之電極層與 與其他構件連接用之電極層, 導電層,形成於貫通孔之内面 外部連接面側之電極層。 中2·Γ申請專利範圍第1項之半導體元件搭载構件,立 中,、纟巴緣構件之熱導率係10w/mK以上。 - 3.如中請專利範圍第μ之半導體元件搭载構m 中,絕緣構件之熱膨脹係數係1〇xl〇_Vt以下 ,、 /.如申請專利範圍第1項之半導體元件搭载構件,並 中’絕緣構件由㈣、Al2〇3、或Sic所形成。 - 5.如申請專職圍第丨項之何體元件 中,絕緣構件之厚度為Ojq·。 ,、 之半導體元件搭载構件,其 由第1推拔面與第2推拔面所 6·如申請專利範圍第i項 中,該半導體元件搭载構件 構成; 326\|I^t\94\94145509\TF968049 49 200824058 ^述第1推拔面以形成貫通孔之内面形成推 向絕緣構件厚度方向之-處所設置的最小孔部而; 口直徑逐漸變小,並在上述主面開口; 卩而開 二第2推拔面以從外部連接面朝向上述最小孔部而 ㈣^逐漸變小之方式形成推拔狀,並在上述外部連接 冋^’上述第丨推拔面和與其連接之主面相交的角产 1、 弟2推拔面和與其連接之外部連接面相交的角产- 2、 及上述兩推拔面所夾的角度θ3均為鈍角。又 中7·:°申請專利範圍第1項之半導體元件搭載構件,i 錢緣構件㈣緣構件 向之距離h,相對於絕绫谨杜々后& m 细的範圍Γ 之厚度’妓在滿足0<h 中8. ^專利範圍第"員之半導體元件搭載構件,其 =小孔敎平面形狀形成圓形,同時,其開口直 Φ9.:、中5#專利範圍第1項之半導體元件搭載構件,其 貝通孔之至少一部份在與絕緣構件主面及外部連接面 相父叉的侧面呈開放狀態。 Ί如申請專利範圍第i項之半導體元件搭載構件,其 /戸#I孔之最小孔部由形成導電層之導電材料所填埋, 在;度方向封閉上述貫通孔。 11*如申請專利範圍第i項之半導體元件搭载構件,其 貝通孔之整體在與絕緣構件主面及外部連接面相交叉 326\總搶\94\94145509VTF968049 5〇 200824058 的側面呈封閉狀態。 12. 如申請專利範園第1 一 中,貫通孔之整體由形成導電層之導搭载構件’其 度方向封閉上述貫通孔。^ 4所填埋,在厚 13. 如申請專利範圍第!項之 成。 4叫王少邛伤由Au所形200824058 X. Patent application scope: 1. A semiconductor component mounting member characterized in that an insulating member integrally formed of ceramics forms a main surface for one side and a back surface for connection with other members; The inner surface of the thickness direction of the plate penetrates from the smallest surface portion provided at the side of the main surface side and the outer connecting surface side in the thickness direction, and is opened and reduced: the size gradually faces and the body element is mounted. The electrode layer formed on the insulating member is formed on the external connection surface; and the electrode layer connected to the main surface side and the electrode layer for connection to other members, and the conductive layer is formed on the inner surface of the through hole. Electrode layer. In the semiconductor element mounting member of the first application of the Japanese Patent Application No. 1, the thermal conductivity of the member of the center and the edge of the bar is 10 w/mK or more. - 3. In the semiconductor device mounting structure m of the patent range, the thermal expansion coefficient of the insulating member is 1〇xl〇_Vt or less, and the semiconductor component mounting member of the first application of the patent scope is 'The insulating member is formed of (4), Al2〇3, or Sic. - 5. In the body element of the application for the full-scale enclosure, the thickness of the insulation member is Ojq·. The semiconductor element mounting member is composed of the first extraction surface and the second extraction surface. 6. The semiconductor element mounting member is formed in the item i of the patent application scope; 326\|I^t\94\94145509 \TF968049 49 200824058 The first push-out surface is formed such that the inner surface of the through-hole forms a minimum hole portion which is provided at a position which is pushed toward the thickness direction of the insulating member; the port diameter gradually becomes smaller, and is opened at the main surface; The second second pushing surface forms a push-out shape so as to gradually decrease from the outer connecting surface toward the minimum hole portion, and intersects the outer surface of the outer connecting surface and the main surface connected thereto The angle of production, the angle of intersection of the 2nd face and the external connection face connected to the brother 2, 2, and the angle θ3 of the above two push faces are obtuse angles. In addition, the thickness of the semiconductor component mounting member of the first application of the patent range, the i-money member (four) edge member, the distance h, relative to the thickness of the fine-grained & m fine range Γ ○ lt;h 8. The patent range of the "member's semiconductor component mounting member, which = small hole 敎 planar shape to form a circle, at the same time, its opening straight Φ9:: 5# patent range of the first item of the semiconductor component In the mounting member, at least a portion of the beacon hole is open to the side surface of the main surface of the insulating member and the external connecting surface. For example, in the semiconductor element mounting member of the item i of the patent application, the smallest hole portion of the hole II is filled with a conductive material forming a conductive layer, and the through hole is closed in the direction of the degree. 11* As in the semiconductor component mounting member of the scope of claim i, the entirety of the beacon hole is closed to the side of the insulating member main surface and the external connecting surface 326\total rushing \94\94145509VTF968049 5〇 200824058. 12. In the first application of the patent specification, the through hole is entirely closed by the conductive mounting layer of the conductive layer. ^ 4 landfills, in thickness 13. As claimed in the patent scope! The result of the project. 4 Called Wang Shaozheng was shaped by Au 14·如申請專利範圍第 中,主面之電極層的最表 或A1合金所形成。 1項之半導體元件搭载構件, 面至少一部份由Ag、Au、A1 其 中15主如申請專利範圍第14項之半導體元件搭載構件,其 ’面之電極層形成為多層構造二 緣構件之-顺,依序包含·· ^構μ罪近絕 層⑴由^、^、阶卜^或該等金屬化合物構成之密接 或NiCr所構成之擴散防 _ (Π)由 pt、Pd、Cu、Ni、Μ〇 止層;及 (ΠΙ)由Ag、A1、或Au所構成之表面層。 广如申請專利範圍第15項之半導體元 中,密接層之厚度為擴散防之牛^ U1〜1.5",表面層之厚度為01w 尽度為 Π.如中請專利範圍第1項之半導體元件搭载構件,並 ,於主面之電極層上積層有Au焊墊。 18.如申請專利範圍第1項之半導體元件搭载構件,其 326V總檔\94\94145509VTF968049 51 200824058 士於絕緣構件之主面設定有半導體元件搭載用之區域, 5 ^•於上述主面上積層有框體,以包圍上述區域。 '如中請專利範圍第18項之半導體元件搭載構件,其 G緣構件與框體之熱膨脹係數均為'它以下, =體之熱膨脹係數與絕緣構件之熱膨脹係數的差為& 1 ϋ / C以下。 項之半導體元件搭載構件,其 體所包圍的半導體元件搭載用 至少由包含半導體元件搭載用14. In the scope of the patent application, the outermost surface of the electrode layer or the A1 alloy is formed. In the semiconductor element mounting member of the first aspect, at least a portion of the surface is made of Ag, Au, or A1. The main component of the semiconductor element mounting member is the semiconductor element mounting member of the fourth aspect of the patent application, and the electrode layer of the surface is formed as a multilayer structure. Shun, in order to contain · 近 近 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( And a stop layer; and (ΠΙ) a surface layer composed of Ag, A1, or Au. In the semiconductor element of the 15th patent application scope, the thickness of the adhesion layer is the diffusion prevention cow ^ U1~1.5", the thickness of the surface layer is 01w. The degree is Π. The semiconductor of the first patent scope The component mounting member has an Au pad laminated on the electrode layer of the main surface. 18. The semiconductor component mounting member according to the first aspect of the patent application, wherein the main component of the insulating member is a region where the semiconductor element is mounted on the main surface of the insulating member, 326V, and the main surface of the insulating member is 5^• laminated on the main surface. There is a frame to surround the above area. 'For the semiconductor component mounting member of the 18th patent range, the thermal expansion coefficient of the G-edge member and the frame is 'below,' the difference between the thermal expansion coefficient of the body and the thermal expansion coefficient of the insulating member is & 1 ϋ / Below C. The semiconductor element mounting member of the present invention is used for mounting a semiconductor element surrounded by the semiconductor element. 20·如申請專利範圍第18 中,絕緣構件之主面上由框 區域’其面積之80%以上, 電極層的金屬層所覆蓋。 圍第·1 i ^衣置’其特徵在於具财:中請專利範 rL::半導體元件搭載構件;以及在上述半導體元件 格載構件中’搭載於絕緣構件之主面的半導體元件。 μ.如申請專利範圍f 21項之半導體裝置,其中 體凡件被密封材所密封。 23·如申睛專利範圍第21項之半導體元件,其中,半導 體凡件搭載構件之主面面積為半導體科在 之投影面積的hl〜4倍。 ’其特徵在於,在申請專 ’其半導體元件使用發光 及保護樹月旨中之至少一 24· —種發光二極體構成構件 利範圍第23項之半導體裝置中 元件,且密封材至少使用螢光體 者0 25. —種發光二極體,其特徵在於具備有: 封裝,具有凹部; 326\總檔\94\94145509\TF968049 52 200824058 二:=項之:光二極體構成構件,其搭載 密封覆蓋(cap)或透鏡, 部密封,且由可透射自發光 構成。 接合在凹部開口 二極體構成構件 ’以將上述凹 之光的材料所 26. —種攝像裝置’其特徵在於具備有· 申請專利_第18項之半導體元 攝像元件’作為半導體元件,搭載於上述;:體 載構件之絕緣構件的主面中由框體所包圍之區域; 盍體’接合在上述框體之上面,以將框體内密封 透光性板材所構成。 元件搭 以及 ,且由 326\||^\94\94145509\TF968049 5320. In the ninth application patent, the main surface of the insulating member is covered by the metal layer of the electrode layer by the frame region '80% or more of the area. The present invention is characterized in that it has a feature: a semiconductor element mounting member; and a semiconductor element mounted on the main surface of the insulating member in the semiconductor element carrier member. μ. The semiconductor device of claim 61, wherein the body member is sealed by a sealing material. 23. The semiconductor component according to claim 21, wherein the semiconductor surface of the semiconductor component mounting member is hl to 4 times the projected area of the semiconductor. 'It is characterized in that at least one of the semiconductor elements of the semiconductor device is used for the illumination and protection of the semiconductor element, and the light-emitting diode constitutes a component of the semiconductor device of the second item, and the sealing material uses at least the firefly. Light body 0 25. A kind of light-emitting diode, which is characterized by: a package having a concave portion; 326\total file\94\94145509\TF968049 52 200824058 2: = item: light diode component, equipped The seal or lens is sealed, and is made of transmissive self-illuminating light. In the recessed-opening diode constituting member 'the material for illuminating the recessed light 26', the image-capturing device' is characterized in that the semiconductor element image sensor of the invention is applied as a semiconductor element. The above-mentioned: the region surrounded by the frame in the main surface of the insulating member of the body member; the body 'joined on the upper surface of the frame to seal the light-transmitting plate in the frame. Component lap and , and by 326\||^\94\94145509\TF968049 53
TW096143369A 2005-02-23 2005-12-21 Semiconductor element mounting member, semiconductor device, imaging device, light emitting diode constituting member, and light emitting diode TW200824058A (en)

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