200822819 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電腦主機板，、尤係一種可彈性支持雙 倍資料速率2 (Double Data Rate 2，簡稱DDR2)記憶體及雙 倍資料速率3 (Double Data Rate 3，簡稱DDR3)記憶體之主 機板。 【先前技術】 ⑩ 現在的一般個人電腦主機板上，除了有中央處理器，控 制晶片組及可供安裝外接卡之插槽外，還有複數用於安裝記 憶體之連接器。用戶可以根據需要，安裝不同數量之記憶 體。隨著記憶體製造技術之快速發展，DDR3記憶體因其在 功耗及速度方面更強之性能將成為未來動態隨機存取記憶 體之主要潮流。然而，從目前普遍使用的DDR2記憶體轉換 至DDR3記憶體仍需要一定之過渡期。 但由於DDR2和DDR3記憶體之操作電壓不同，DDR2 •記憶體之操作電壓為VDD = 1.8V，VTT=0.9V，而DDR3記憶 體之操作電壓為VDD = 1.5V，VTT=0.75V。因而，目前在主 機板之設計上，仍無一款主機板可同時支持DDR2及DDR3 記憶體。因此，如何提供一種電腦主機板，可支援不同規格 之記憶體，即為業界急需解決之課題。 【發明内容】 鑒於以上内容，有必要提供一種可彈性支持不同類型記 憶體之主機板。 一種支持混合式記憶體之主機板，包括一第一連接器、 7 200822819 -^連接器、-與該h連接器及該第二連接器電連 電壓調節電路及-與該電壓調節電路連接的串列存在 單元，該第一連接器用以安裝一第一類型記憶體，該第二遠 接器用以安裝-第二類型記憶體，該第-及第二類型^ 選擇安裝於主機板上’該串列存在_單元用以判別安穿一 該主機板上之記憶體類型，該電壓調節電路根據該串列存在 债測單元偵測到的安裝在主機板上的記憶體類型為記憶體 提供適合之工作電壓。 _ 該支持混合式記憶體之主機板上的串列存在價測單元 可自動偵測安裝在該主板上之記憶體類型，並透過電壓調節 電路提供適合之電壓，使同一主機板可彈性支持不同類型之 記憶體，滿足不同用戶之需求。 【實施方式】 參考圖1，一種支持混合式記憶體之主機板包括一串列 存在偵測單元（serial presence detect，簡稱 SPD ) 1〇、一電 響壓調節電路20、一第一連接器30及一第二連接器4〇。該第 一連接器30用以安裝DDR2記憶體，該第二連接器4〇用以 安裝DDR3記憶體。同一時間在該主機板上只能選擇安裝一 種類型之記憶體。 該SPD10是一組關於記憶體之配置資訊，如速度、容 量、電壓與行、列位址帶寬等，它們存放在一個容量為256 位元組的電子抹除式唯讀記憶體（Electrically Erasable Programmable Read Only Memory，EEPROM)中。可以根據 DDR2記憶體和DDR3記憶體在任何一個SPD Byte(位元組） 8 200822819 中的差異判定所使用之記憶體類型。表1列出DDR2和DDR3 記億體在SPD Byte2中每一位元（bit)對應之數值。 表1 SPD Byte2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO DDR2記憶體 0 0 0 0 1 0 0 0 DDR3記憶體 0 0 0 0 1 0 1 1 該電壓調節器20包括一控制器22、一濾波器24、一線 性穩壓器26及一回授偏壓電路28。該回授偏壓電路28包括 馨兩個場效電晶體Ql、Q2，兩電阻Rl、R2，及一回授電阻 R3。該場效電晶體Q1為PMOS場效電晶體、該場效電晶體 Q2為NMOS場效電晶體。該兩場效電晶體Q1及Q2的閘極 相連並與該SPD10連接，該場效電晶體Q1之源極與該場效 電晶體Q2之汲極連接並與該控制器22之回授針腳連接，該 控制器22之回授針腳端之回授電壓Vfb在本實施方式中設 定為0.6V。該場效電晶體Q1之源極與該場效電晶體Q2之 馨汲極間之節點還與該回授電阻R3之一端相連。該場效電晶 體Q1之汲極透過該電阻R1接地，該場效電晶體Q2之源極 透過該電阻R2接地。該電阻Rl、R2之阻值分別為1.65千 歐姆、2.2千歐姆，該回授電阻R3之阻值為3.3千歐姆。該 場效電晶體Q1及Q2之導通截止狀態由SPD10中的BitO和 Bitl的值決定。該控制器22之輸出端與該濾波器24之輸入 端連接，該濾波器24之輸出端輸出電壓VDD，該濾波器24 之輸出端與該回授偏壓電路28的回授電阻R3之另一端連 接，該電壓VDD傳送給該線性穩壓器26，並透過該線性穩 9 200822819 塵器2·6轉換為電麗νττ分別提供給該第一連接器％及該 =連接二40。該據波器24之輸出端還直接與該第一連接 ° §弟連接器40連接向該連接器30、40輸出電壓 VDD 〇 s田在2第一連接器3〇上安裝DDR2記憶體，該第二連 ，二、4〇工接，電腦系統開機時，基本輸入輸出系統(BI〇s) '買 HPD10 *的資訊，SPDByte2 * _和 bitl 的值為 〇〇, _ =疋第一連接器30上安裝DDR2記憶體，故場效電晶體Q1 導通，該電阻R1接入電路，因為回授偏壓電路28必須將該 控制益22回授針腳端之回授電壓Vfb調整至控制器22回授 針腳之没定值0.6V，根據Vfb與VDD之分壓公式 VOD=W(il3+iU)/Rl，計算得 vDD 為 18V，故控制器 22 將輸出電壓調整為18V，並透該過濾波器24濾波輸出， VDD分別直接提供給該回授偏壓電路28及安裝在該第一連 接30上的DDR2記憶體，VDD又透過線性穩壓器26轉 φ換成VTT (0.9V)提供給DDR2記憶體。 當在該第二連接器40上安裝DDR3記憶體，該第一連 接器30空接，電腦系統開機時基本輸入輸出系統(BIOS)讀 取SPD10中的資訊，SPD Byte2中bitO和bitl的值為11， 判定第二連接器40上安裝DDR3記憶體，故場效電晶體Q2 導通，該電阻R2接入電路，因為回授偏壓電路28必須將該 控制器22回授針腳端之回授電壓調整至設定值0.6V ’ 根據Vfb與VDD之分壓公式VDD=Vfb*(R3+R2)/R2,計算 得VDD為1.5V，故控制器22將輸出電壓調整為1.5V ’並 200822819 透過濾波器24濾波輸出，VDD分別直接提供給該回授偏壓 電路28及安裝在該第二連接器40上之DDR3記憶體，VDD 又透過線性穩壓器26轉換成VTT(0、75V)提供DDR3記憶 體。 在該支持混合式記憶體之主機板上可選擇安裝不同類 型之記憶體，並根據SPD偵測到之不同記憶體規格，自動調 整向記憶體提供合適的電源電壓，在記憶體換代時，尤其在 DDR2記憶體轉換至DDR3記憶體之過渡期内，提供使用者 ®更大之應用彈性。 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉 本案技藝之人士，在爰依本發明精神所作之等效修飾或變 化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明支持混合式記憶體之主機板較佳實施 φ 方式之原理圖。 【主要元件符號說明】 串列存在偵測單元 10 電壓調節電路 20 控制器 22 濾波器 24 線性穩壓器 26 回授偏壓電路 28 第一連接器 30 第二連接器 40 場效電晶體 Ql，Q2 電阻 Rl，R2 回授電阻 R3 11200822819 IX. Description of the invention: [Technical field of the invention] The present invention relates to a computer motherboard, in particular, an elastic data support double data rate 2 (DDR2) memory and double data rate 3 (Double Data Rate 3, DDR3 for short) memory motherboard. [Prior Art] 10 On the current general PC motherboard, in addition to the central processing unit, the control chip set and the slot for mounting the external card, there are a plurality of connectors for mounting the memory. Users can install different amounts of memory as needed. With the rapid development of memory manufacturing technology, DDR3 memory will become the main trend of future dynamic random access memory due to its superior performance in power consumption and speed. However, the transition from the currently widely used DDR2 memory to DDR3 memory still requires a certain transition period. However, due to the different operating voltages of DDR2 and DDR3 memory, the operating voltage of DDR2 memory is VDD = 1.8V, VTT = 0.9V, and the operating voltage of DDR3 memory is VDD = 1.5V, VTT = 0.75V. Therefore, at present, there is still no motherboard that can support both DDR2 and DDR3 memory in the design of the main board. Therefore, how to provide a computer motherboard that can support different specifications of memory is an urgent problem for the industry. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a motherboard that can flexibly support different types of memory. A motherboard supporting a hybrid memory, comprising a first connector, 7 200822819 -^ connector, - electrically connected to the h connector and the second connector, and - connected to the voltage regulating circuit a serial presence unit, the first connector is for mounting a first type of memory, the second connector is for mounting a second type of memory, and the first and second types are selected to be mounted on the motherboard. The serial presence _ unit is configured to determine the type of memory that is worn on the motherboard, and the voltage adjustment circuit provides a suitable memory for the memory type installed on the motherboard according to the serial presence of the debt detecting unit. Working voltage. _ The serial-based price measurement unit on the motherboard supporting the hybrid memory can automatically detect the type of memory installed on the motherboard, and provide a suitable voltage through the voltage regulating circuit, so that the same motherboard can flexibly support different Types of memory to meet the needs of different users. [Embodiment] Referring to FIG. 1 , a motherboard supporting a hybrid memory includes a serial presence detect (SPD) 1 , an electrical voltage adjustment circuit 20 , and a first connector 30 . And a second connector 4〇. The first connector 30 is for mounting DDR2 memory, and the second connector 4 is for mounting DDR3 memory. Only one type of memory can be installed on the motherboard at the same time. The SPD10 is a set of configuration information about the memory, such as speed, capacity, voltage and row and column address bandwidth, etc., which are stored in a 256-bit electronic erased read-only memory (Electrically Erasable Programmable). Read Only Memory, EEPROM). The type of memory used can be determined based on the difference between the DDR2 memory and the DDR3 memory in any one of the SPD Bytes (2008). Table 1 lists the values of each bit (bit) of DDR2 and DDR3 in SPD Byte2. Table 1 SPD Byte2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO DDR2 Memory 0 0 0 0 1 0 0 0 DDR3 Memory 0 0 0 0 1 0 1 1 The voltage regulator 20 includes a controller 22, a filter 24, A linear regulator 26 and a feedback bias circuit 28 are provided. The feedback bias circuit 28 includes two field effect transistors Q1, Q2, two resistors R1, R2, and a feedback resistor R3. The field effect transistor Q1 is a PMOS field effect transistor, and the field effect transistor Q2 is an NMOS field effect transistor. The gates of the two transistors Q1 and Q2 are connected to and connected to the SPD 10. The source of the field effect transistor Q1 is connected to the drain of the field effect transistor Q2 and is connected to the feedback pin of the controller 22. The feedback voltage Vfb of the feedback pin of the controller 22 is set to 0.6 V in the present embodiment. The node between the source of the field effect transistor Q1 and the anode of the field effect transistor Q2 is also connected to one end of the feedback resistor R3. The drain of the field effect transistor Q1 is grounded through the resistor R1, and the source of the field effect transistor Q2 is grounded through the resistor R2. The resistances of the resistors R1 and R2 are respectively 1.65 kilo ohms and 2.2 kilo ohms, and the resistance of the feedback resistor R3 is 3.3 kilo ohms. The on-off states of the field effect transistors Q1 and Q2 are determined by the values of BitO and Bitl in SPD10. The output of the controller 22 is connected to the input of the filter 24. The output of the filter 24 outputs a voltage VDD, and the output of the filter 24 and the feedback resistor R3 of the feedback bias circuit 28 The other end is connected, and the voltage VDD is transmitted to the linear regulator 26, and is converted to the first connector % and the = connection 40 through the linear stable 9 200822819 dust collector 2·6, respectively. The output end of the wave device 24 is also directly connected to the first connection connector 40 to output the voltage VDD to the connector 30, 40. The DDR2 memory is mounted on the 2 first connector 3A. The second connection, the second and the fourth, the computer input system, the basic input and output system (BI〇s) 'buy HPD10 * information, SPDByte2 * _ and bitl value 〇〇, _ = 疋 first connector The DDR2 memory is mounted on the 30, so the field effect transistor Q1 is turned on, and the resistor R1 is connected to the circuit, because the feedback bias circuit 28 must adjust the feedback voltage Vfb of the control pin 22 to the pin terminal to the controller 22 The feedback pin has a fixed value of 0.6V. According to the voltage division formula VOD=W(il3+iU)/Rl of Vfb and VDD, the calculated vDD is 18V, so the controller 22 adjusts the output voltage to 18V and filters through it. The filter 24 filters the output, and VDD is directly supplied to the feedback bias circuit 28 and the DDR2 memory mounted on the first connection 30. The VDD is further converted to VTT (0.9V) by the linear regulator 26. Available for DDR2 memory. When the DDR3 memory is mounted on the second connector 40, the first connector 30 is vacant, and the basic input/output system (BIOS) reads the information in the SPD 10 when the computer system is powered on, and the values of bitO and bitl in the SPD Byte2 are 11. It is determined that the DDR3 memory is mounted on the second connector 40, so the field effect transistor Q2 is turned on, and the resistor R2 is connected to the circuit, because the feedback bias circuit 28 must feed the controller 22 back to the pin end. The voltage is adjusted to the set value of 0.6V. According to the voltage division formula VDD=Vfb*(R3+R2)/R2 of Vfb and VDD, the VDD is calculated to be 1.5V, so the controller 22 adjusts the output voltage to 1.5V' and 200822819 The filter 24 filters the output, and VDD is directly supplied to the feedback bias circuit 28 and the DDR3 memory mounted on the second connector 40. The VDD is further converted into a VTT (0, 75V) through the linear regulator 26. Provide DDR3 memory. On the motherboard supporting the hybrid memory, different types of memory can be installed, and according to the different memory specifications detected by the SPD, the appropriate power supply voltage is automatically adjusted to the memory, especially when the memory is replaced. Provides greater flexibility for users® during the transition period from DDR2 memory to DDR3 memory. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a preferred embodiment of the φ mode of a motherboard supporting the hybrid memory of the present invention. [Main component symbol description] Tandem presence detecting unit 10 Voltage regulating circuit 20 Controller 22 Filter 24 Linear regulator 26 Feedback bias circuit 28 First connector 30 Second connector 40 Field effect transistor Ql , Q2 resistor Rl, R2 feedback resistor R3 11