TW200822287A - Method of fabricating semiconductor device having fine contact holes - Google Patents

Abstract

A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Description

200822287 26022pif.doc IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and more particularly to manufacturing a mask pattern formed in a patterned pattern to form a fine contact hole (fine contact hole) A method of a semiconductor device. [Prior Art] The semiconductor device includes a discrete device such as an electric crystal, a resistor, and a capacitor. The separating device is electrically connected to each other via a contact plug or interconnecting device formed in the contact opening π of the through insulating layer. For example, the NAND flash memory includes an active area parent fork that is the same as each other in the semiconductor substrate. An extended word line, and a selection line that is adjacent to the word line and is parental to the active area. The NAND type flash memory further includes a bit line insulated from and intersecting with the word line and the selection line by an interlayer dielectric layer: the bit line is electrically connected to the active area near the selection line via the contact window opening, respectively . The contact window opening is generally formed by a patterning process. The patterned gas 耘 includes a mask _, which is formed by a yellow light process (10) __FQeess, and an electrical layer exposed by the opening.曰 Because the size of the contact window opening becomes smaller with the accumulated sound of the semiconductor device, the size of the lang is also small. “It’s difficult to make two first coats to the required opening size. For example, due to the complexity of the layout on the half plate (topol〇gy), the yellow light process, the soil selection and the word line) Diffuse reflection (diffusereflecii〇n). Therefore, 歹, such as the size of each opening, there is still a considerable degree of existence. Because ^ ensure that the 200822287 26022pif.doc method to ensure that the contact plugs filled in the opening of each contact window There is a consistent resistance. Therefore, the reliability of the semiconductor device is degraded. [Invention] Accordingly, the embodiments described in the present application relate to a mask pattern formed by using a pattern to be manufactured with subtle and substantial A method of a semiconductor device having a uniformly uniform contact opening. ο

One embodiment of the present invention provides a method of fabricating a semiconductor device. For example, the method includes first forming an isolation layer defining an active region on a semiconductor substrate. Then, an interlayer dielectric is formed on the semiconductor substrate having the isolation layer. Next, a first molding pattern is formed on the interlayer dielectric layer. Further, a second pattern having a space therebetween may be formed between the first pattern patterns. = a mask pattern enclosing the side walls of the first and second molding patterns. The openings are formed by removing and patterning. The mask is patterned to engrave the interlayer dielectric layer to form a contact opening. [Embodiment] The present invention will now be described more fully hereinafter with reference to the appended claims. The embodiment explicitly stated in the present application. Rather, it is provided to be thorough and complete, and to convey the scope of the invention to those skilled in the art. In Guanzhong, for the sake of clarity, it is exaggerated:: the thickness of the area. Throughout the specification, like reference numerals indicate that a material (such as a layer, a film, a region, or a substrate) is referred to as a member; when it is referred to as being directly on the other component, or vice versa, when the 7° member is referred to as When located directly on another component 6 200822287 26022pif.doc, there are no intermediate components. 1 is a plan view of a semiconductor device in accordance with an embodiment. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 11A, 12A, 13A, and 14A are cross-sectional views taken along line M' of Fig. 1. It is a flowchart of a method of manufacturing a semiconductor device according to the first embodiment. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are cross sections along the line π-ιγ of Fig. 1. Figure is a flow chart of a method of fabricating a semiconductor device in accordance with a first embodiment. Referring to Figures 1, 2A and 2B, a semiconductor substrate 1 is provided. The semiconductor substrate 100 may be a germanium substrate. The material of the semiconductor substrate 1 is, for example, SiC, SiGe or GaAs. A pad layer 103 is formed on the semiconductor substrate 100. The pad layer 103 includes at least one of a thermal oxide layer and a silicon nitride layer. A lower hard mask layer l6 is formed on the underlayer 103. The lower hard mask 〇 curtain layer 106 includes a silicon oxide. In one embodiment, the lower hard f curtain layer 106 comprises a hafnium oxide layer. In one embodiment, the lower/hard mask layer 106 is not formed (i.e., the formation of the lower hard mask layer 1 〇 6 is omitted). • Referring to Figures 1, 3A and 3B, first curtain patterns 109 spaced apart from one another are formed on the lower hard mask layer 1〇6. Each of the upper hard cover and the case 109 includes a material different from the lower hard mask layer 1〇6. For example, the ruthenium mask layer 106 includes oxidized stone, and the first upper hard mask pattern is polycrystalline silicon (P〇ly_silion) or silicon nitride. Each first captain | = The pattern is linear. In one embodiment, the lower hard mask layer soup of 9 weeks 1] is formed by the 200822287 26022 pif.doc-upper hard mask 11 case to form the recessed region 107. A conformal sacrificial layer 112 is formed overlying the recessed regions of the first-upper hard mask pattern and the lower hard mask layer 106. Thus, a portion of the sacrificial layer 112 located between the first upper hard mask patterns ι 9 can be defined as a trench 112a. By adjusting the thickness of the sacrificial layer 112, the trench 112a forms a bottom surface having substantially the same n-groove as the upper-top hard mask 109. The bottom surface of the disk-upper mask pattern (10) may be coplanar. -shell. The 2 layers m may include a material that is selective with respect to [the upper hard mask pattern (10). For example, when the first upper hard mask pattern 109 is etched, the sacrificial layer 112 includes yttrium oxide. The sacrificial layer 112 and the lower hard mask layer 106 comprise substantially the same material. For example, the sacrificial layer 112 and the lower hard cover include yttrium oxide. The sacrificial layer 112 is formed to cover the sidewall of the upper hard mask pattern 109 when the beaker is scraped 1 1Q6. / static 2 Figure 1, Figure 4A and Figure 4B, in the thickness of the cover defined by the sacrificial layer 112 is substantially uniform and linear, the second upper hard brother - upper hard mask pattern 115 ^ placed on the first - upper hard cover Qin Between the patterns H) 9 and surrounded by the sacrificial layer 112. Therefore, the side walls and the bottom surface of the second upper hard cover are surrounded by a sacrificial layer ι 2 . The second upper hard mask pattern 115 includes the first quality of the fish. U hard mask power pattern 109 the same material 200822287 26022pif.doc In one embodiment, the second upper hard mask pattern 115 is disposed in the first layer 112 of the first upper hard mask pattern 1〇9 The plate-shaped cylinder is hard-turned to the material layer, and the upper surface of the hard mask is flattened until the top surface of the upper hard mask material layer is substantially coplanar with the top surface of the upper cover: case 109 To form a second

Hard mask picture f 115. The method of planarizing the upper hard mask material layer is, for example, etch back (4) back and/or chemical mechanical polishing method (4) ^ pdishing, CMP). When the upper hard mask material layer is planarized using the back process, the hard mask material is made on the side such that the top surface of the second upper hard mask pattern 115 is substantially the top surface of the first upper hard mask pattern 1Q9. For the coplanar. When the CMP technique is used to planarize the upper hard mask material, the hard mask material layer is flattened until the first hard mask is exposed. Referring to FIGS. 5A and 5B, a portion of the sacrificial layer 112 exposed by the second upper hard mask layer 115 is etched. After the (four) sacrificial layer 曰ιΐ2 is exposed, the hard mask layer 106 and the mat layer 1〇3 are lowered. As a result, the sequentially stacked first pad pattern 1G3a and the lower-lower mask pattern riQ6a are formed under the =; hard Ϊ綦 pattern 1 〇 9. At the same time, the second pad pattern legs, the second hard mask pattern and the age _(10) which are sequentially stacked are also formed under the second upper hard mask pattern 115. Referring to FIG. 1, FIG. 6A and FIG. 6B, the first and second 塾 patterns 1〇3a and i03b, the first "0" second lower hard mask pattern 106aw _, and the first and second hard mask patterns 1Q9 and 115 is a butterfly, and the substrate 100 is formed to form a trench 117. Therefore, by the semiconductor substrate 200822287 26022pif, doc is sufficient to form the trenches 117 ______ of the active region 118a, ^ ^ " ~ ^ ^ cloth mask patterns 109 and 115 are formed into a line shape, so the active regions 118a are defined It is linear and extends in the longitudinal direction of the semiconductor substrate 1〇〇. Referring to Figures 1, 7A and 7B, an isolation layer 121 is formed to substantially fill the trenches 117. The isolation layer 121 includes an insulating layer such as a high density plasma oxide. ο ο left by forming an insulating layer filled in the trench 117 shown in FIG. 6A, and then removing the first and second pad patterns 1 〇 3 & and 1 〇 north, first ^ second hard The mask patterns 1 and 1 and the first and second upper hard mask patterns 109 and 115 are formed to form an isolation layer 121 Ό + 曰 with reference to FIG. 5 and FIG. 8A, and electricity is formed on each active region U8a. Carcass. The transistor includes a formation on each active region 118a

And a doped region 136 formed on each side of the main structure C on both sides of the structure 134. For example, the fine (4) inner domain. The 至 曰 7 (4) 隹 & field 136 includes the source and the bungee area ^ The electric Japanese version can be a unit cell transistor CT, and at least one emperor can be a selective transistor ST. Cell I曰Μ M Hair Day :: Line Selection; Line SSL or Ground Selecting Crystal Cell CT can be the electrical layer of flash memory. The second dielectric layers i to 124 may be through the dielectric layer "'an electric layer. The above-mentioned layer 10 200822287 26022pif.doc pen layer at least - layer is, for example, oxidized stone eve, nitrogen oxynitride eve (si0N) , nitrogen s, ilOgen-doped Si oxide), high dielectric constant (h (four)) dimorphism or a combination of materials. High dielectric constant dielectric material; inlet 疋 ^ 1 de, oxidation, bismuth oxide or the like or Initiating f) ο 5. Bay (four) storage layer] 27 at least the layer comprises a oxynitride (s_, a nitrogen-constant dielectric material or a substance or a combination thereof), and two at least one layer of the layer 130 includes oxidation Material of Shi Xi (for example, medium temperature oxide (MT)), high dielectric or similar or a combination thereof. In one embodiment, the data storage layer 127 includes too much 曰 ( Nan〇^^^ 〇, ^^ a ^ 'ls(Mo)' ::Secondary: In the example, the nanocrystalline structure includes the oxide of human, (7) () or the like or its electric: material. In another example, the material of the nanocrystalline structure package (four), the wrong 1 fossil ” t boron or the like or a combination thereof. The sequential second cell electricity: " The gate layer and the control idle electrode. The semiconductor substrate 1 (10) on the sounding = transistor ST and CT has a shape 139. The dielectric layer 139 is, for example, an oxidized stone. The stop layer 142 is formed on the # 曰 layer 139. A buffer layer 145 is formed on the engraving stop layer (4) 142. Buffer i. For example, when the surname stop layer 142 has a _ selective material, the 〇@secret layer 142 is a nitride, and the buffer layer 145 is 200822287 26022pif. Doc oxidized stone material, etc. Referring to Fig. 1, Fig. 9A and Fig. 9B, a first *molding layer is formed on the buffer layer 145. The first molding layer includes a material having a selective selection and properties with respect to the buffer layer 145. The mold layer is, for example, a material such as polysilicon. Next, the first mold layer is patterned to form a linear first mold line 148. The first mold layer can be patterned using photolithography and I-etching processes. Each of the first molding lines 148 is formed in a form overlapping with an odd or even number of active regions in the active region 〇118a. Therefore, the pitch P1 between the first molding lines 148 is larger than the micro pattern used to pattern the first molding layer. Minimum resolution that can be achieved by the shadow process As described above, the first molding line 148 is formed in a line shape. Thus, the first molding line 148 has a substantially uniform width. By etching a portion of the buffer layer 145 between the first molding lines 148 to form A recessed region 147. A conformal spacer layer 151 is formed on the semiconductor substrate 100 having the first molding line 148. The spacer layer 151 covers the top and sidewalls of the first I) molding line 148, and defines a portion of the recessed region 147. Buffer layer 145. Therefore, the spacer layer 151 defines a linear groove 151a on the buffer layer 145 between the first molding lines 148. The groove 151a may be formed to have substantially the same width as the first molding line 148 by adjusting the thickness of the spacer layer 151. The bottom surface of the trench 151a is substantially coplanar with the bottom surface of the first molding line 148 >. In an embodiment, the spacer layer 151 comprises substantially the same material as the buffer layer 145. Referring to Figures 1, 10A and 10B, a second mold layer is formed on the semiconductor substrate 100 having the spacer layer 151 to fill the trench 151a. No. 12 200822287 26022pif.doc A molded layer includes a material layer that is the same as the first molded layer. Next, a patterning (e.g., planarization) process is performed on the first patterned layer to form a second molding line 154 that fills the trench 151a. Thus, the second molding line 154 is uniformly uniform in shape and linear, and is located on the buffer layer 145 between the first molding lines 148. The first mold line 154 is disposed at substantially the same level as the first mold line 148. For example, the bottom surface of the second molding line 154 is substantially coplanar with the bottom surface of the first molding line 148. Further, the width of the second molding line 154 is substantially the same as the width of the first molding line i4g. In the consistent application, each younger brother makes a line 148 and an odd active area 118a. Therefore, each of the second molding lines 154 overlaps with the even number of active regions 118a. Thus, the pitch P2 of the first and second molding lines 148 and 154 is smaller than the pitch P1 between the first molding lines 148. The second mold layer is planarized using etch back or CMP techniques. When the second molding layer is planarized using a return process, the second molding layer is inscribed such that the top surface of the second molding line 154 is substantially coplanar with the top surface of the first molding line 148. When the cyp technique is used to planarize the second mold layer, the second mold layer is planarized until the top surface of the first mold line 148 is exposed. On the semiconductor substrate 100 having the second molding line 154, a linear resist pattern 157 which is bonded to the first and second molding lines 148 and 154 is formed. The photoresist pattern 157 is formed to have a substantially uniform predetermined width. When the second etch layer is planarized using the etch back process described above, a portion of the spacer layer 151 placed over the first pattern line 148 is also patterned by #, and then a photoresist pattern 157 is formed. In one embodiment, the photoresist pattern 157 is formed to intersect the partial active region 118a such that the string selection line 13 of the transistor ST is selected. 200822287 26022pif.doc SSL level is located in the photoresist pattern 157 and the cell transistor CT Between lines WL. The photoresist pattern 157 is substantially parallel to the string selection line SSL. Referring to FIG. 1, FIG. 11A and FIG. 11B, a portion of the spacer layer 151 exposed by the photoresist pattern 157 and the first and second molding lines 148 and 154 are etched by using the photoresist pattern 157 as an etching mask to form a first One and second molding patterns 148 & and 154a. For example, the spacer layer 151 is etched by a dry etching process using an etching gas having an etch selectivity to the first and second molding lines 148 ο ο 154. Subsequently, the first and second molding lines 148 and 154 are rhymed. According to an embodiment, since the linear first and second molding lines 148 and 154 are patterned using the photoresist pattern 157 of a predetermined width, the first and second molding patterns 148a and 15 are formed to have substantially uniform widths, respectively. , =' g| is the width of the second molding line W and the width of the first molding line (10) is the same as the width of the second molding pattern. Then, in addition to the photoresist pattern 157 (for example, the use of the ashing stripping process is 8. Coffee). The first and second molding patterns 14 and 154a hood Qin _ first and second molding patterns 148M 154a The door (10) is spaced apart by a layer 151 to form a bit @;, r52, and thereby exposing a portion of the buffer; and the second === is the first curtain, the part of the _. Therefore, the first stack is sequentially stacked; The second and second τ punch patterns are formed on the etch stop layer 142. Similarly, the first buffer pattern 145b, the spacer pattern 152 and the second are sequentially stacked. The pattern i54a is formed on the end of the layer 142. Thus, the _thivation pattern 1-5a and the first pattern 148a are sequentially referred to as the first aperture pattern 155a, and sequentially stacked. The second buffer pattern Μ%, the spacer pattern 152, and the first pattern 154a are referred to as a second aperture pattern i55b. In the embodiment where the spacer layer 151 and the buffer layer 145 comprise substantially the same material, the same etching may be performed. In the process, the etch spacer layer 151 and the buffer layer 145 are viewed in plan view, the first sum The second aperture molding pattern 15 and 155b are formed to have a major axis (maj or axe) and a minor axis (minor axe). The long axes of the first and second aperture die patterns 155a and 155b are along the active region H8a. The longitudinal direction extends in substantially the same direction. Referring to Figures 1, 12A and 12B, a mask layer is formed on the semiconductor substrate 1 having the first and second aperture patterning patterns 155a and 155b. The sound includes a material having an insecticidal selectivity with respect to the first and second molding patterns 148a and 154a, the spacer pattern 152, and the first and second buffer patterns 145a and 145b. For example, the mask layer includes an organic material such as light. • Impedance, anti-reflective coating (ARC), amorphous carbon material, or the like, or a combination thereof. Next, the patterned mask layer (eg, planarization) is A mask pattern 160 is formed. In one embodiment, the mask layer is patterned using an etch back process until the top surfaces of the first and second aperture patterning patterns 155a and 155b are exposed. Thereafter, the first and second layers are removed. Opening patterning patterns 155a and 155b, 15 200822287 26022pif.doc to form the first and second openings 161 Μϋ 16 lb in the curtain pattern (10). In the case of the case, by patterning the first and second molding patterns (10) a and 154a, and then leaving the spacing pattern 152 And the first and second balance diagrams Yin*l45a and 145匕, and removing the first and second aperture molding patterns 155a and 155b, and the spacing between the second and second apertures is substantially parallel to the string selection line SSI The direction of ^. .耆r, referring to FIG. 13A and FIG. 13B, the mask pattern 160 is used as a mask, the lateral termination layer 142 and the interlayer dielectric layer 139 to form an active region U8a adjacent to the string selection line SSL. First and second contact window openings 163a and i63b. The layer 142 and the interlayer dielectric layer 139 may be terminated by a side-by-side process. Thus, the first and second contact opening openings ^3a and 163b are formed to have a size of the real f. Although the first and second contact opening 163a and 163b are formed to have substantially uniform dimensions, although the first and second contact opening 163& and the aspect ratio are large. , J As described above, the mask pattern 160 includes an organic material. Thus, when the interlayer dielectric layer 139 is left to form the first and second 'contact window openings 163a=163b, the sidewalls of the first and second contact opening 16% and 16 are coated with a mask pattern. 160 thin layer of organic material. Since the sidewalls of the first and first contact window openings 163a and 163b are coated with a thin polymer layer, the width of the first and second contact opening 163 & 163b can be prevented from increasing to the contact opening 163a. And the extent to which 163b can communicate with each other. Thus, the first and second contact opening 163 & 163 and 163b are formed to have a longitudinally vertical side wall or a positively-inclined side 16 200822287 26022 pif.doc wall. When the first and second contact opening 163a and 163b have positively inclined side walls, the widths of the respective first and second contact opening 163a and 163b become smaller from the upper region toward the lower region thereof.罩 Referring to Figures 1, 14A and 14B, the mask pattern 16 is removed. Thereafter, the etch stop layer 142 is removed. A contact conductive layer is formed on the semiconductor substrate 1A having the first and second contact opening 163a and 163b. In one embodiment, the contact conductive layer comprises a material such as doped polysilicon, metal or the like or a combination thereof. The contact conductive layer is planarized by a CMP or etch back process until the top surface of the interlayer dielectric layer 139 is exposed to form contact plugs cn filled in the first and second contact opening 163a and 163b. The contact interposer CN includes first and second contact plugs 166a and 166b that are filled in the first and second contact opening openings 2 and 163b, respectively. As shown in Figs. 11A and 11B, the first to the eleventh-closed patterning patterns 155a and 155b are formed to have a long axis and a short axis, respectively. Therefore, the long axis and the short axis seen in the plan view, where the long axis of i is along with the main secret, 118_longitudinal side: = this, in order to reduce the contact plug called doping area 丨 = ^ = ^, training curry (3) The first conductive layer 139 overlying the dummy region overlaps between the first contact plug 166a and the second contact plug 166b: the first conductive line 169a is formed to overlap the first conductive line 169a. Even number of active areas. Each of the second conductive cores 200822287 26022pif.doc The active regions 118a located between the first conductive lines 169a The conductive lines 169a and 169b are referred to as bit lines BL. Brother I. The method of forming the first and second conductive lines is as follows. First, first: forming a first conductive line l69a on the interlayer dielectric layer I39 and overlapping the first contact plug, and then forming a bit line spacer covering the sidewall of the first conductive line (not shown) And then, forming a two-side D wall $second conductive line 169b disposed between the turns of the wire 169a and having contact with the bit spacer layer, and removing the bit line spacer layer 'however, in the example only, The bit line spacer layer is not removed (eg, the removal of the bit line spacer layer is omitted). Therefore, the bit line spacer layer remains between the first and second conductive lines 169a and 169b. According to the embodiment depicted in FIGS. 1 through 14B, the first and second openings 161a and 161b are formed to have substantially uniform dimensions, respectively, as compared to forming the openings directly in the mask pattern 16A by the lithography process. . Therefore, the subsequently formed first and second contact opening 163a and 163b have a real/quality uniform size in both the sectional view and the Q plan view. Therefore, the first and second contact plugs 166a and 166b respectively filled in the first and second contact opening 163a and 163b have substantially uniform impedance. A method of manufacturing a semiconductor device according to a second embodiment will be described hereinafter with reference to Fig. 1 and Figs. 15A to 20B.

Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A and Fig. 20A are cross-sectional views taken along line I-Ι of Fig. 1, which is a flow chart of a method of manufacturing a semiconductor device according to a second embodiment. 15B, 16B, 17B, 18B, 19B, and 20B are cross-sectional views taken along line ΙΙ-ΙΓ of Fig. 1, which are 18 200822287 26022 pif. doc Flowchart of a method of manufacturing a semiconductor device according to a second embodiment . Referring to FIGS. 1, 15A and 15B, a semiconductor substrate 1 having an active region U8a defined by an isolation layer 121 is formed according to the methods described above with respect to FIGS. 2A to 7A and FIGS. 2A to 7B. . ο ο A transistor is formed on each active region 118a. The transistor includes a gate structure 234 formed on each active region 118a and a doped region 236 formed in each active region on both sides of the gate structure 234. At least one of the transistors is a cell transistor ct and at least the germanium transistor is a selective transistor ST. The gate electrode of the unit cell CT is used as the word line WL and intersects with the active region n8a. The blue electrode of the transistor ST is selected as the string selection line SSL or the ground selection line GSL, and extends across the active region 118a. In one embodiment, the gate structure 234 of the cell transistor ct includes a gate dielectric layer 224, a gate 227, a gate dielectric layer 23, and a gate electrode 233 stacked in sequence. The floating gate 227 is, for example, a polycrystalline stone. Doped region 230 can be a source and drain region. In another embodiment, the gate structure 234 of the cell transistor CT can include a first dielectric layer, a data storage layer, and a second dielectric gateless electrode stacked in sequence. On the semiconductor substrate 100 having the transistors ST and CT, a layer of tantalum layer 239 is formed. The interlayer dielectric layer 239 is, for example, hafnium oxide. θ Referring to FIG. 1, FIG. 16B and FIG. 16A, an acoustic layer xj and a winter stop layer 242 are formed on the interlayer dielectric layer 239. The engraved termination layer 242 includes a layer of dielectric material relative to the interlayer. For example, when the interlayer dielectric layer 239 is used, the engraved termination layer 242 may be a material such as nitride. 19 200822287 26022pif.doc A first mold layer is formed on the last stop layer 242. The first mold layer includes a material having an etch selectivity with respect to the etch stop layer 242. For example, when the etch stop layer 242 includes tantalum nitride, the first mold layer includes a polysilicon or the like. Next, the first mold layer is patterned to form a linear first mold line 248. The first mold layer can be patterned using lithography and etching processes to make the first mold line 248 have a substantially uniform width. In one embodiment, each of the first molding lines 248 is formed to overlap an odd or even number of active regions in the active region. The spacer layer 251 is formed to cover the sidewall of the first molding pair 8. Forming a layer of material having an etch selectivity with respect to the first molding line 248 on the semiconductor substrate 1 〇〇 and the first molding line 248 in a conformal manner, and then etching the material layer by anisotropic etching to The spacer layer 251 is formed such that the spacer layer 251 is on the sidewalls of the first molding line 248 and has a substantially uniform width. /, , , = 3⁄4 Fig. 1 ' and FIG. 17B, a second mold layer is formed on the = substrate having the spacer layer 251. The second molded layer includes substantially two-half damascene lines 248 forming a substantially two-layered wire 254 having a substantially uniform width. The second molding line 254 is also linear. When using the I-worm and/or CMIM branch to planarize the second mold-making back to flatten the second mold layer, two: making the top surface and the second layer of the second mold line 254 coplanar . In the embodiment - the surface of the surface is substantially 20 200822287 26022pif.doc. Since the first and second molding lines 248 comprise substantially the same material, the second molding layer is overetched and the first molding line 248 is also inscribed. Thus, the top surfaces of the first and second lemon lines 248 are substantially coplanar.

V. When the CMP technique is used to planarize the second mold layer, the top surface of the second mold line 254 is substantially coplanar with the top surfaces of the first mold line 248 and the spacer layer 251. Thus, the second molding line 254 is disposed in substantially the same level as the first D molding line 248. When each of the first molding lines 248 is formed to overlap with the odd active regions, each of the second molding lines 254 is formed to overlap with the even number of active regions. A linear resist pattern 257 crossing the first and second molding lines 248 and 254 is formed on the semiconductor substrate having the second molding line 254. The photoresist pattern 257 is formed to have a substantially uniform predetermined width. In one embodiment, the photoresist pattern 257 is formed to intersect the partial active region 118a such that the string select line SSL level of the select transistor ST is between the photoresist 257 and the word line WL of the unit cell CT. . The photoresist pattern 257 is substantially parallel to the string selection line SSL. Referring to FIG. 1, FIG. 18A and FIG. 18B, the first and second molding lines 248 and 254 are inscribed by the photoresist pattern 257 as an etch mask to form first and second aperture patterning patterns 248a and 254a. . Subsequently, the photoresist pattern 257 is removed. The spacer layer 251 is then removed (e.g., | insect). Therefore, the first and second dies 4 patterns 248a and 254a remain on the I-terminating stop layer 242. According to an embodiment, since the first and second molding lines 248 and 254 are patterned in a linear shape with a photoresist pattern 257 having a predetermined width, the first and 21 200822287 26022 pif.doc first aperture molding is fortunately 943⁄43⁄4 degrees . Further, the first and second = 2 grounds respectively have substantially uniform widths of a major axis and a minor axis. The first hole molding pattern 2 and the 254a respectively have a long axis fm and a moving area of the second aperture molding patterns 248a and 254a: or the longitudinal direction of the _ is substantially the same direction Ο 以及 degree and the photoresist pattern ^5^^ and The widths 248a and 254a of the two _' lines 248 and 254. The visibility is formed to form the first and second molding patterns to form a mask layer on the ί conductor substrate 1〇0 having the first and second aperture mask layer L phases. _ Selective: and = and · Impedance, ARr db, cover layer including return, such as light, Illustrated - amorphous carbon material or the like or a combination thereof. The nth (fourth) process is to planarize the mask layer until the top surface of the opening pattern 248a and 254a is exposed. The mask Pit removes the first and second aperture pattern patterns 248a and 254a, so the mask j Figure 2, forming the first and second openings 26ia and secret. Line _彳t two = xian and 鸠 along the line with the selection of the cover ^ ^ 1, Figure 2GA and Figure, with the cover pattern 26G for money The etch stop layer 242 and the interlayer dielectric layer are disposed, and the contact openings 242 are adjacent to the first and the third regions of the active region 118a: (4) and 13-, and then the etch stop layer 242 is removed. Filling the 22nd 200822287 26022pif.doc and the first contact window opening to form the contact plug CN (for example, as shown in Fig. 14A and Fig. 14B; +, m ice one: knowing). The plug CN includes first and second contact plugs 266a and 266b respectively filled in the first and 'first contact openings'. The first and second contact plugs 266a and 266b are formed on the dielectric layer 239 and the first contact plug 266a. Overlapping f ^ = line 269a (eg, as depicted in Figures 14A and 14B). Between the second & pen, complex %9a 'formed with the second contact plug 266b overlapped the conductive line 26% The first and second conductive lines 269a and 26% are referred to as 'bit lines BL. Each of the first conductive lines 269a is formed to overlap an odd or even number of active regions within the active region 118a. Each of the second conductive lines 269b is formed. To focus on the active area 118a between the first conductive lines 269a in a horizontal direction. According to the embodiment described above, the first and second molded patterns are patterned by patterning the first and first modes. The mask pattern openings formed along the first and second molding patterns have substantially uniform dimensions. Therefore, the subsequently formed contact window openings have substantially uniform dimensions and are filled in the contact window openings. The contact plug has a substantially uniform impedance. Therefore, the upper The method can increase the reliability of semiconductor wins. Thus, a method of fabricating a semiconductor device according to an embodiment described herein includes forming an isolation layer defining an active region in a semiconductor substrate. Formed on the semiconductor substrate having the falling layer. The first molding pattern is formed on the interlayer dielectric layer, and a second molding method is formed between and spaced apart from the first molding pattern to form the surrounding first and second moldings. A mask pattern of the sidewalls of the pattern. The openings are formed by removing the first and second mold patterns. Using a mask pattern as an etch mask, the interlayer is etched to form a contact opening. In one embodiment, the first molding pattern and the second molding pattern are formed. The method includes: forming a first molding line on the interlayer dielectric layer, forming a second molding line on the interlayer dielectric layer, and forming a second molding line The first molding line is disposed between the first molding line and spaced apart from the first molding line, and then the first molding line is patterned to form a first molding pattern and the second molding line is patterned to form a second molding pattern.一 In one embodiment, at least a portion of the first and second molding lines are substantially coplanar. In an embodiment, the first and second molding patterns are formed to have the same size. In an embodiment, the first and second molding patterns are formed to have a long axis and a short axis as viewed in plan. In an embodiment, the major axes of the first and second molding patterns have the same direction as the longitudinal directions of the first and second molding lines. } In one embodiment, a buffer layer is formed on the semiconductor substrate prior to forming/forming the first molding line. In another embodiment, after the first molding line is formed, the buffer layer is disposed on both sides of the first molding line by etching to form a recessed region. In one embodiment, forming the second molding line includes first forming a conformal spacer layer covering the first molding line and covering the buffer layer having the recessed region, and then forming a molding layer on the semiconductor substrate having the spacer layer, and then forming The molding layer is planarized such that the top surface of the second molding line is at the same level as the top surface of the first molding line. 24 200822287 26022pif.doc In one embodiment, forming the first and second patterned patterns includes first forming a photoresist pattern on the spacer layer and the second molding line, and then bonding the light to the first and second molding lines. The resist pattern is an etch mask, etching the spacer layer and the first and second molding lines to form the first and second molding patterns, and then removing the photoresist pattern, and then using the first and second molding patterns as an etching mask, A spacer layer and a buffer layer around the first and second mold patterns are etched. In one embodiment, the method of forming the second molding line comprises first forming a spacer layer covering the first molding line on the semiconductor substrate having the first molding line, and then forming the molding on the semiconductor substrate having the spacer layer. The layer, and the planarized molding layer, such that the molded layer remains between the first molding lines. In one embodiment, forming the first and second mold patterns comprises first forming a photoresist pattern crossing the first and second molding lines on the semiconductor substrate having the first molding line, and then using the photoresist pattern as an etching mask The first and first molding lines are etched to form the first and second molding patterns, and then the photoresist pattern is removed, followed by etching the spacer layer to expose the side U walls of the first and second molding patterns. In a consistent embodiment, a plurality of active regions are separated from each other by an isolation layer and each active region is defined as a line by an isolation layer. • In one embodiment, each of the first molding lines is formed to overlap an odd, one, or even active region in the active region, and the second molding line is formed to be an active region between the first molding line and the active region. overlapping. In two embodiments, the definition of the active region includes first forming a first hard mask pattern on the semiconductor substrate, forming a second hard mask pattern between the first hard mask patterns, and then etching the first and second hard portions. A mask pattern between the 25 200822287 26022pif.doc semiconductor substrate to form a green, neon fill fill and remove the first and second hard mask patterns.胄—layer, forming ί;: Shi: in; the definition of the moving region includes first in the semiconductor substrate domain, followed by: forming a surrounding buffer layer to form a recessed region ^, and the formation of the seventh is repeated in the first hard mask. An wg曰' Ο ο the sagittal layer of the sacrificial layer of the buffer layer, and then formed by the: sacrificial layer between the _ second hard mask pattern, = hard mask pattern and located in the first and the Second, the first and second hard masks are used to form the trenches, and then the formation is filled in. Forming a first-hard mask pattern thereon, then forming a sacrificial covering the sidewalls of the n-semiconductor substrate, and then forming a second layer between the second sidewall of the second hard mask pattern having contact with the sacrificial layer After the first and second hard cover cases are _^1, the sacrificial plates are removed to form a ditch, and then a ruthenium-etched conductor-based hard mask pattern is formed. The layer of m, and removed, in one embodiment, on the formation of the interlayer dielectric reed active region, and in the gate structure "structure formation region. Doping in the germanium region - in the embodiment, each gate structure includes The first dielectric layer 262222287 26022pif.doc layer stacked in sequence is located at the gate, the lean storage layer, the second dielectric layer, and the (four) pole. In another, the gate structure includes the electric layer and phase stacked in sequence. , a dielectric layer and a control gate. In the embodiment, the mask pattern is formed by an organic material layer. In the actual method, the method for manufacturing the semiconductor device further includes a punch pattern and forms a filling contact opening. Contact plug.

。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, the scope of the present invention is allowed by the law to allow for the scope of the patent, and the maximum allowable interpretation is not limited to the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a semiconductor device in accordance with an embodiment. 2A, 3A, 4A, 5A, 6A, 7A, 8A, A, 10A, UA, Fig. 1, and Fig. 1A are cuts (4) of the line w', which are based on A flow chart of a method of manufacturing a half-set of the first embodiment. 4 Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, ^B, ® 10B, Figure 11B, Figure 12B, Figure 13B and Figure 14B are along

The interception of the two strong lines 11_11, which is a flow chart of a method for manufacturing a semi-guided garment according to the first embodiment. Figs. 15A, 16A, 17A, 18A, 19A and 20A: a cross-sectional view of line H of Fig. 1, which is a flow chart of a method of manufacturing a body device according to the second embodiment. 200822287 26022pif.doc FIGS. 15B, 16B, 17B, 18B, 19B, and 20B are cross-sectional views taken along line ΙΙ-ΙΓ of FIG. 1, which are flowcharts of a method of fabricating a semiconductor device according to a second embodiment. . [Main component symbol description] 100: semiconductor substrate 103: pad layer 103a: first pad pattern 〇103b: second pad pattern 106: lower hard mask layer 106a: first lower hard mask pattern 106b: second lower hard mask Curtain pattern 10 7 · recessed area 109: first upper hard mask pattern 112: sacrificial layer 112a: trench) / 112b: sacrificial pattern / i 115 : second upper hard mask pattern 117 : trench 118 a · active area 121 · Isolation layer 124: First dielectric layer 127: Data storage layer 130: Second dielectric layer 133: Gate electrode 28 200822287 26022pif.doc 134 Gate structure 136 Doped region 139 Interlayer dielectric layer 142 1 Insect termination layer 145 buffer layer 145a: first buffer pattern 145b: second buffer pattern () 147: recessed region 148: first molding line 148a: first molding pattern 151: conformal spacer layer 151a: linear groove 152: spacer pattern 154 The second molding line 154a: the second molding pattern ^ 155a: the first opening pattern 155b: the second opening pattern 157: the photoresist pattern 160: the mask pattern '161a: the first opening 161b · · the second Opening 163a: first contact opening 163b: second contact opening 16 6a: first contact plug 29 200822287 26022pif.doc 166b: second contact plug 169a: first conductive line. 169b: second conductive line 224: second conductive line 227: floating gate 230: inter-gate dielectric layer 233 : Control gate 〇 234 : gate structure 236 : doped region 239 : interlayer dielectric layer 242 : etch stop layer 248 : first molding line 248a : first aperture molding pattern 251 : spacer layer 254 : second molding line - 254a: second aperture molding pattern 257: photoresist pattern 260: mask pattern 261a · first opening 261b: second opening 266a: first contact plug 266b: second contact plug 269a: first conductive Line 269b ··Second conductive line 30 200822287 26022pif.doc BL : Bit line GSL : Ground selection line. WL : Word line SSL : String selection line CN : Contact plug ST : Select transistor CT : Cell transistor P1 : Spacing P2: Spacing Ι-Γ : Line ΙΙ-ΙΓ : Line

Claims (1)

200822287 26022pif.doc X. Patent Application Range: 1. A method of manufacturing a semiconductor device, comprising: • forming an isolation layer on a semiconductor substrate, the isolation layer defining an active region in the semiconductor substrate; Forming an interlayer dielectric layer on the semiconductor substrate, forming a first/mold pattern on the interlayer dielectric layer; forming a second molding pattern on the interlayer dielectric layer, the second mold pattern being disposed on Between the first molding patterns and the first molding pattern; forming a mask pattern surrounding the sidewalls of the first molding pattern and the sidewalls of the second molding pattern; removing the first molding And patterning the second mold pattern to form an opening in the mask pattern; and etching the interlayer dielectric layer to form a contact window opening using the mask pattern as an etch mask. The method of manufacturing a semiconductor package according to the above item 1, wherein the forming the first molding pattern and the second molding pattern comprises: forming a first molding line on the interlayer dielectric layer ♦ forming a second molding line on the interlayer dielectric layer, the second molding line being disposed between the first wedge lines and having a gap with the first molding line; patterning the Forming a first/mold pattern; and patterning the second mold line to form a second mold pattern. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the at least one portion of the first molding line is substantially at least one of/the second molding line. Partially coplanar. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the width of one of the first molding patterns is the same as the width of a pattern of the one mold. Ο 5. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the first molding pattern and the at least one of the second molding patterns has a major axis and a minor axis in plan view. 6. The method of fabricating a semiconductor device according to claim 5, wherein the active region extends through the semiconductor substrate in a longitudinal direction, and the long axis of the at least one first patterned pattern and The long axis of at least one second molding pattern extends substantially in the same direction as the longitudinal direction. The method of manufacturing a semiconductor device according to claim 2, further comprising forming a buffer layer on the layer before forming the first molding line. The method of manufacturing a semi-method as described in claim 7 further includes: forming the first molding line above the buffer layer, the first mold forming four buffer layer phases Adjacent to at least the opposite side of the first molding line, after the formation of the first molding line, each of the buffer layers adjacent to the at least one and the opposite side The method of manufacturing a semiconductor according to claim 8 of the invention, wherein the forming the second molding line comprises: conformal on the first molding line and each Forming a spacer layer in the recessed area; forming a molding layer on the spacer layer; and top patterning the molding layer such that at least one of the second molds, the surface substantially and at least one The top surface of the first molding line is coplanar. The method of manufacturing a semi-conductive garment according to claim 9, wherein the first molding pattern and the second molding product are formed. Included in: the spacer layer and the second Forming a photoresist pattern on the line, the photoresist pattern and the first molding line and the second molding line parent fork' using a photoresist pattern as an etching mask, etching the portion of the first molding line a spacer layer; an etching mask as an etching mask, etching a portion of the first molding line and a portion of the second molding line; removing the photoresist pattern; and the first molding pattern and the The second mold 4 is patterned as an etching mask, and the portion of the spacer layer between the first molding line and the second molding line is retained, and the pattern and the pattern are The second molding pattern is an etching mask, and a portion of the retardation layer exposed in the recessed region is etched. The method of manufacturing a semiconductor device according to claim 2, wherein the The second molding line includes: forming a spacer layer over the first molding line; 34 200822287 26022 pif.doc ο ο forming a molding layer on the spacer layer; and leaving the patterned layer to be patterned such that a portion The molding layer maintains an adjacent Between the pair of moldings, the method of manufacturing the semi-^^^ package according to the πth aspect of the patent application, wherein the first molding pattern and the second mold & And f include: a vapor on which the spacer layer and the second molding line are formed. The photoresist pattern is further described, and the first molding line and the second mold are formed by the second mold. The photoresist pattern is an etching mask, etching part of the young line and the second molding line; removing the photoresist pattern; and &, ten, a dielectric line and the portion of the etched portion Layer to expose the younger brother, the second molding line (4). (4) Manufacturing semiconductor devices 13. As claimed in the scope of patents!顼 υ 炎 炎 直 离 离 离 离 离 离 离 离 & & & & & & & & & & & & & & & & & & & & & & & Wherein the isolation layer is to be used by each of the active gas units. 14. As claimed in the patent application, the first: the first molding pattern, the Le Neville,鸣 橥 多个 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二Between the regions σ 15 · The method of claim 1 wherein the forming the isolation layer comprises: forming a semi-conductive hard mask pattern on the semiconductor substrate. 200822287 26022pif.doc forming a second between the first hard mask pattern, the second hard mask pattern and the first mask, and the first hard mask And the second ruthenium sapphire is an etched mask, the portion of the semiconductor substrate between the first and second hoods and the second hard mask pattern is formed to form a groove, a hard cover The screen removes the first hard mask pattern ------ 16 · The system described in the third paragraph of the patent application & Pei body facing white (filling the trench with an insulating material; and / and the second one ...... Shu The method of forming the spacer layer: forming a retardation layer on the semiconductor substrate; forming a first hard mask pattern on the buffer layer such that a portion of the first hard mask layer is adjacent And opposite sides of at least one of the first hard mask patterns; after the forming the first hard mask pattern, the buffer adjacent to the opposite side of the at least one first hard mask pattern Forming a recessed region in each portion of the layer, forming a sacrificial layer covering the sidewall of the first hard mask pattern and disposed in each of the recessed regions; on the sacrificial layer and in the third crucible Forming a hard mask pattern between the mask patterns, the portion of the sacrificial layer above the first hard mask pattern is engraved; and the first hard mask pattern and the second layer are described a portion of the sacrificial layer between the hard mask patterns to form a sacrificial pattern under the second hard mask pattern; 36 200822287 26022 pif.doc ϋ a mask pattern is etched with the first hard mask pattern and The brother-π second hard mask mask mask, the tentacles are located in the a first hard mask method and a household; The mask case is Ο ο and the sacrificial hard mask pattern is removed. 17. The method of claim 1, wherein the forming the isolation layer comprises: forming an first hard mask on the semiconductor substrate; forming a cover a side curtain of the first hard mask pattern, which forms a second break between the first hard mask patterns and a sidewall of each of the second hard mask patterns contacts the Sacrificing " removing the sacrificial layer; ^ i internal is etched with the first hard mask pattern and the second mask: a tomb mask mask, etched in the first hard mask a portion of the semiconducting/body substrate between the curtain pattern and the first/stone case to form a trench; filling the trench with an insulating material; and removing the first-hard mask pattern and the first 〉 Hard mask pattern. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a gate structure on the active region before forming the interlayer dielectric layer; and on opposite sides of the structure A doped region is formed in the active region. The method of fabricating a semiconductor device according to claim 18, wherein at least one of the gate structures comprises a first dielectric layer, a data storage layer, a second dielectric layer, and a gate electrode. 20. The method of fabricating a semiconductor device according to claim 18, wherein at least one of the gate structures comprises a gate dielectric layer, a floating gate, a gate dielectric layer, and a control gate. 21. The method of fabricating a semiconductor device according to claim 1, wherein the mask pattern comprises an organic material. 22. The method of fabricating a semiconductor device of claim 1, further comprising: removing the mask pattern; and forming a contact plug filling the contact opening. 23. The method of fabricating a semiconductor device of claim 2, further comprising forming the second molding line after forming the first molding line. U 38