200820418 UMCD-2006-0227 21197twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電感器，且特別是有關於一種電 感器之佈局及其製造方法。 【先前技術】 電感為（inductor)疋非常重要的被動元件，常被應用 馨 於射頻（radio frequency，RF)電路、壓控振盪器（v〇ltage controlled oscillator，VC0)、低噪放大器（1〇w n〇ise amplifier，LNA)或是功率放大器（power amplifier，pA) 等。例如無線通訊系統，很明顯地將電感器整合於單一晶 片中是最佳解決方案。受惠於半導體技術的進步，利用互 補金氧半（Complementary Metal-Oxide Semiconductor， CMOS)製程’整合於晶片中的電感器在GHz頻帶的應用 上可以具有適當的品質因數Q (例如8〜1〇)。然而，習 知技術之電感态佈局必需佔用大量晶片面積（大約〇 _ x0.3mm)，因此不利於高密度整合之應用。 圖1是一種壓控振盪器之電路圖。壓控振盪器1〇〇包 括電阻器141、P型電晶體Ι3ι與132、二極體ι21與122、 電容器in、112、113與114、電感器1〇1與102等。依 ，電板（pad) BV之偏壓電壓（bias v〇ltage)，壓控振盪 器1 〇〇決定其輸出電板ουτ+與 ουτ-所輸出信號之振盪頻 率。圖2是說明以習知技術實施圖}壓控振盪器i⑽之佈 局圖。請同時參考圖1與圖2,在此僅強調其佈局方式， 200820418 UMCD-2006-0227 21197twf.doc/e 而不贅述其元件連接關係。由圖2可以 電感器101與102之佈局面产月疋看出早早 即匈囬積就比電阻器141、P型電晶 體131與132、二極體ι21蛊12? 尸生冤曰日 士 ^ 興122、電容器111〜114之佈 局面積總和還大。由於電感器、101請必需佔用大量曰 片面積’導致積體電路成本增加。 一用大里曰曰 吐吝ίϊ度ΐ路設計向來要求佔用最小晶片面積，以降低 生產成本。為了使晶片面積最小化 哭200820418 UMCD-2006-0227 21197 twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to an inductor, and more particularly to an arrangement of an inductor and a method of fabricating the same. [Prior Art] Inductor is a very important passive component, often used in radio frequency (RF) circuits, voltage controlled oscillators (VC0), low noise amplifiers (1〇) Wn〇ise amplifier, LNA) or power amplifier (pA). For example, in wireless communication systems, it is clear that integrating the inductor into a single wafer is the best solution. Benefiting from advances in semiconductor technology, inductors integrated into the wafer using the Complementary Metal-Oxide Semiconductor (CMOS) process can have an appropriate quality factor Q (eg, 8~1〇) in the GHz band. ). However, the inductive layout of the prior art requires a large amount of wafer area (approximately 〇 _ x 0.3 mm), which is disadvantageous for high density integration applications. Figure 1 is a circuit diagram of a voltage controlled oscillator. The voltage controlled oscillator 1 includes a resistor 141, P-type transistors Ι3ι and 132, diodes ι 21 and 122, capacitors in, 112, 113 and 114, inductors 〇1 and 102, and the like. According to the bias voltage of the BV of the board (bias v〇ltage), the voltage controlled oscillator 1 determines the oscillation frequency of the output signals of the output boards ουτ+ and ουτ-. Figure 2 is a layout diagram illustrating the implementation of the voltage controlled oscillator i (10) in the prior art. Please refer to FIG. 1 and FIG. 2 at the same time, and only emphasize its layout manner, 200820418 UMCD-2006-0227 21197twf.doc/e without repeating its component connection relationship. From Fig. 2, it can be seen from the layout of the inductors 101 and 102 that the early Hungarian back product is better than the resistor 141, the P-type transistor 131 and 132, and the diode ι21蛊12. The total layout area of the capacitors 111 to 114 is still large. Since the inductor and 101 must occupy a large amount of chip area, the cost of the integrated circuit is increased. The use of large 曰曰 吝 ϊ ϊ ϊ ΐ 设计 设计 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求 要求In order to minimize the wafer area, cry
的Q值’因此習知技術（例如美國專利公告號觀55= 459^35等）以積體電路後段製程在積體電路土方形 -個具有厚介電層（通常為多晶硫亞氨）的電感器。然而， 其需要特賴鄕程核形錢感^，且增加額外 與生產複雜度。 、另外，美國專利公告號US6518165專利案揭露-種電 感器之佈局。此習知技術將電感器、配置於電路區域（d舰^ area)上方，藉以節省晶片面積。由於此習知技術將電减 器之'«f疊於區域上方’因此電感器之信號與電路 區域中之信號將不可避免地相互耦合。為了改善此一耦合 效應，US6518165專利案採用特殊製程方式，把電感器之 下方之介電物質完全掏空，並盡可能地將電感器抬高以遠 離電路區域。然而，所屬領域具有通常知識者均知，此習 知技術雖可以節省晶片面積，但是其必須以特殊製程來形 成電感為。此習知技術會增加額外的成本與生產複雜度， 對於產業利用而言此習知技術並不實用。 200820418 UMCD-2006-0227 21197iwf.doc/e 【發明内容】 本發明的目的就是提供—種電感器之 於任何標準製程，同時可以節省晶片面積。 乂應用 本發明的再-目的是提供一種電感器之 不增加額外的成本與生產複雜度的前提，二在 器所佔晶片面積之功效。 逹到即1電感 基於上述及其他目的，本發明提出—種 局’包括基底以及導電路徑。前述基底包含至少^饰 域，其中該主動區域包含至少一電路。導電路押配， 上方，並且沿著主動區域邊緣之方向配置於主動區找= 附近:其中導電路徑之㈣為器之兩端。純域邊緣 從另-觀點來看’本發明提出一種電感器之 首先於基底形成至少一主動區域:其 中5亥主動域包含至少—魏。然後錄底上方， ，域邊緣之方向’以及於主龍域邊緣附近，形^導電 路徑，其中導電路徑之兩端為電感器之兩端。或¥電 依照本發明的較佳實施例，上述之導電路捏圍繞該主 動區域而成單圈線圈。 依照本發明的較佳#闕，战之導電路徑圍繞該主 動區域而成多圈線圈。 一、曾依照本發明的較佳實闕，上述之導電雜被配置於 ^電層中’該導電層位於該基底上方導 最上層金屬層Ctopmetal 一）。 θ 了以疋 200820418 UMCD-2006-0227 21197twf.doc/e 依照本發明的較佳實施例，上述之導電路徑被 多個導電層中，該些導電層位於該基底上方。 · ' 依照本發明的較佳實施例，上述更包括形成至少 蔽層（shielding layer)，其中該遮蔽層配置 該基底之間。 电以益與 一本發明因沿著主動區域邊緣之方向，將電感器 路徑配置於主動區域邊緣附近，因此可以在不增加 成本與生純雜度的前提下，以任何鮮製程形成電感哭 之佈局’制節省電感ϋ所佔晶片面積之功效。… 為讓本發明之上述和其他㈣、特徵和優點能更明顯 易f重，下文特舉較佳實施例’並配合所附圖式， 說 明如下。 【實施方式】 以下諸實施例將以圖i之麼控振盪$ 1〇〇4例，說明 =月應用於壓控振盪⑽之功效。所屬領域具有通常 =者當可依縣㈣讀和及下料實關之教示或 ，礒，而將本發明應用於其他任何f要電感器之積體電路 宁。 、 於圖1之屢控振盈器1〇〇中，交互輕接之p型電晶體 與:132被用來產生負回授以維持财振μ。取代電晶 體電、机源之多晶發電阻器141被用來定義尾電流 ^rent)。電感器而、1〇2以及電容器⑴〜114可以決 疋壓控振盪器100之振盈頻率。 200820418 UMCD-2006-0227 21197twf.doc/e 圖3A是依照本發明實施例說明電感器佈局之立體 圖。圖3B是依照本發明實施例說明電感器佈局之俯視圖。 為了與習知技術相比較，本實施例將壓控振盪器100中電 阻器141、P型電晶體131與132、二極體121與122、電 容器111〜114之佈局維持與圖2相同。 請同時參照圖3A與圖3B，基底300包含至少一主動 區域，其中該主動區域包含由電阻器141、電晶體131與 132、二極體121與122、電容器111〜114、電板BV、OUT+ 與OUT-所構成之電路。電感器ιοί之導電路徑沿著前述 主動區域邊緣之方向而配置於主動區域左侧邊緣附近。電 感益102之佈局相似於電感器ιοί，電感器1〇2之導電路 徑亦沿著前述主動區域邊緣之方向，而配置於主動區域右 側邊緣附近。 圖4是依照本發明實施例說明圖3A所示壓控振盪器 佈局之控制電壓-輸出頻率特性圖。此圖是使圖3A之壓控 振盪裔操作在2·4 V所量測緣製而成。請同時參照圖】、圖 • 3A與圖4,此測量過程將電板（pad)BV之偏壓電壓（^狀 voltage)操作於ov〜2·4ν之間。可以從圖中清楚看出， 圖3Α壓控振盪器之輸出電板ουτ+與 〇υτ_所輸出之振盪 頻率可以操作於4519MHz〜5019MHz之間，此結果可以 滿足無線區域網路（例如8〇2.11b/g)所需頻帶4824MHz 〜4960MHz 〇 圖5是依照本發明實施例說明圖3A所示壓控振盪器 佈局之位移-相位雜音特性圖。請同時參照圖工、圖从與 200820418 UMCD-2006-0227 21197twf.doc/e 圖5，假定輸出電板ουτ+與 0UT_所輸出之振盪頻率為 4945·7ΜΗζ ’圖3A之電感器將於600kHz與1MHz之位矛多 (offset)條件下分別獲得_118.5(1价紐與_124.6(1价紐: 位雜音（phase noise)。此結果可以滿足無線區域網路（例 如802.1 lb/g)所要求之相位雜音規格（如圖5所示）。 以下將本實施例與習知技術進行比較，請參照表1。 為了能公平地比較出本實施例與習知技術之優劣，以下將 以「優勢數值」（figure-of_merit，以下稱FOM )作為頻率 與功率消耗之綜合性評比指標。FOM之計算式如下：. FOM = 101〇g p · ffoff] 2, sup 、f〇」 + L{f( off 其中L{f〇ff}表示在輸出頻率為f0且位移頻率為f〇ff之條件 下SSB相位雜音量測，而psup表示壓控振盪器之功率消耗 (單位為mW)。 表1:應用本發明實施例電感器佈局之壓控振盪器與習知The Q value 'is therefore known technology (for example, US Patent Bulletin No. 55 = 459^35, etc.) in the integrated circuit back-end process in the integrated circuit earth--a thick dielectric layer (usually polycrystalline sulfimine) Inductor. However, it requires a special sense of nuclear money and adds extra and production complexity. In addition, U.S. Patent Publication No. 6,518,165 discloses a layout of an inductor. This prior art technology places the inductor above the circuit area (d ship area) to save wafer area. Since this conventional technique places the '_f over the area' of the reducer, the signals of the inductor and the signals in the circuit area will inevitably couple with each other. In order to improve this coupling effect, the US6518165 patent uses a special process to completely vent the dielectric material underneath the inductor and lift the inductor as far as possible away from the circuit area. However, it is well known to those of ordinary skill in the art that although this technique can save wafer area, it must be formed by a special process. This prior art adds additional cost and production complexity, which is not practical for industrial use. 200820418 UMCD-2006-0227 21197iwf.doc/e SUMMARY OF THE INVENTION It is an object of the present invention to provide an inductor for any standard process while saving wafer area.乂Application The re-purpose of the present invention is to provide an inductor without the added cost and production complexity, and the effect of the wafer area occupied by the device. The present invention proposes a substrate comprising a substrate and a conductive path. The aforementioned substrate comprises at least a decorative region, wherein the active region comprises at least one circuit. The guiding circuit is compliant, above, and arranged along the edge of the active area in the active area to find = nearby: wherein the conductive path (4) is the two ends of the device. Pure domain edge From another point of view, the present invention proposes an inductor that first forms at least one active region on the substrate: wherein the 5 Hz active domain contains at least - Wei. Then, at the top of the bottom, the direction of the edge of the domain and the vicinity of the edge of the main dragon domain, the shape of the conductive path, where the two ends of the conductive path are the ends of the inductor. Or electric power According to a preferred embodiment of the present invention, the above-mentioned guiding circuit is pinched around the main moving region to form a single-turn coil. According to a preferred embodiment of the present invention, the conductive path of the war is formed into a plurality of coils around the active area. According to a preferred embodiment of the present invention, the conductive impurities are disposed in the electrical layer. The conductive layer is located above the substrate to expose the uppermost metal layer Ctopmetal (a). θ 疋 200820418 UMCD-2006-0227 21197 twf.doc/e In accordance with a preferred embodiment of the present invention, the conductive path is formed by a plurality of conductive layers over the substrate. According to a preferred embodiment of the present invention, the above further includes forming at least a shielding layer, wherein the shielding layer is disposed between the substrates. According to the invention, the inductor path is disposed near the edge of the active region due to the direction along the edge of the active region, so that the inductor can be formed by any fresh process without increasing the cost and the purity of the raw material. The layout 'savings the efficiency of the chip area occupied by the inductor. The above and other (four) features, advantages and advantages of the present invention will become more apparent, and the preferred embodiments will be described hereinafter with reference to the accompanying drawings. [Embodiment] The following embodiments will oscillate $1〇〇4 in Fig. i to illustrate the effect of =month applied to the voltage controlled oscillation (10). The field of the art has the usual = when the county can be read and unloaded by the teachings, or 礒, and the invention is applied to any other integrated circuit of the inductor. In the repeatedly controlled vibrator 1 of Figure 1, the interactively connected p-type transistor and :132 are used to generate negative feedback to maintain the gain μ. A polycrystalline resistor 141, which replaces the electromorphic, machine source, is used to define the tail current ^rent). The inductor, 1〇2, and capacitors (1) to 114 can be used to determine the oscillation frequency of the voltage controlled oscillator 100. 200820418 UMCD-2006-0227 21197twf.doc/e FIG. 3A is a perspective view illustrating the layout of an inductor in accordance with an embodiment of the present invention. 3B is a top plan view illustrating an inductor layout in accordance with an embodiment of the present invention. In comparison with the prior art, the present embodiment maintains the layout of the resistor 141, the P-type transistors 131 and 132, the diodes 121 and 122, and the capacitors 111 to 114 in the voltage controlled oscillator 100 in the same manner as in Fig. 2. Referring to FIG. 3A and FIG. 3B simultaneously, the substrate 300 includes at least one active region, wherein the active region includes a resistor 141, transistors 131 and 132, diodes 121 and 122, capacitors 111 to 114, and an electric board BV and OUT+. The circuit formed by OUT-. The conductive path of the inductor ιοί is disposed near the left edge of the active area along the direction of the edge of the active area. The layout of the electrical benefit 102 is similar to that of the inductor ιοί, and the conductive path of the inductor 1〇2 is also along the edge of the active region and is disposed near the right edge of the active region. 4 is a graph showing control voltage-output frequency characteristics of the voltage controlled oscillator layout of FIG. 3A in accordance with an embodiment of the present invention. This figure is made by the pressure-controlled oscillating operation of Fig. 3A measured at 2.4 V. Please refer to the figure, Fig. 3A and Fig. 4. This measurement process operates the bias voltage (^ voltage) of the pad BV between ov~2·4ν. It can be clearly seen from the figure that the oscillation frequency outputted by the output plates ουτ+ and 〇υτ_ of the voltage controlled oscillator of Fig. 3 can be operated between 4519MHz and 5019MHz, and the result can satisfy the wireless local area network (for example, 8〇). 2.11b/g) Required Band Band 4824 MHz to 4960 MHz FIG. 5 is a diagram showing the displacement-phase noise characteristic of the voltage controlled oscillator layout shown in FIG. 3A in accordance with an embodiment of the present invention. Please refer to Fig. 5 and 200820418 UMCD-2006-0227 21197twf.doc/e Figure 5, assuming that the output frequency of the output board ουτ+ and OUT_ is 4945·7ΜΗζ 'The inductor of Fig. 3A will be 600kHz Obtain _118.5 (1 price NZD and _124.6 (1 price NZ: phase noise) with the 1MHz offset (this condition) can satisfy the wireless local area network (for example, 802.1 lb/g). The required phase noise specifications (as shown in Figure 5). For comparison of the present embodiment with the prior art, please refer to Table 1. In order to be able to fairly compare the advantages and disadvantages of the present embodiment with the prior art, the following will be The figure-of-merit (FOM) is used as a comprehensive evaluation index of frequency and power consumption. The calculation formula of FOM is as follows: FOM = 101〇gp · ffoff] 2, sup, f〇” + L{f( Off where L{f〇ff} indicates the SSB phase noise level measurement under the condition that the output frequency is f0 and the displacement frequency is f〇ff, and psup represents the power consumption of the voltage controlled oscillator (in mW). Table 1: Application Voltage Controlled Oscillator of Inductor Layout and Conventional Embodiments of the Present Invention
振盪頻率 相位雜音 調整範圍 F0M (MHz) (dBc/Hz) (%) (dBc/Hz) 本實施例 4.9 -124.6 . 10.5 -184.7 文獻1 5.6 -116.7 11.3 -184.0 文獻2 53 426.0 3.8 -188.2 文獻3 4.0 -117.0 13.0 -180.3 上述表1中，「文獻1」為西元2004年Oscillation frequency phase noise adjustment range F0M (MHz) (dBc/Hz) (%) (dBc/Hz) This embodiment 4.9 -124.6 . 10.5 -184.7 Document 1 5.6 -116.7 11.3 -184.0 Document 2 53 426.0 3.8 -188.2 Document 3 4.0 -117.0 13.0 -180.3 In Table 1 above, "Document 1" is in 2004.
Symposium」第 127-130 頁所發表之「A 5Giiz 200820418 UMCD-2006-0227 21197twf.doc/e transformer-coupled CMOS VCO using bias-level shifting technique」論文，「文獻2」為西元2002年「RFIC Symposium」第 93-96 頁所發表之「High performance SOI and bulk CMOS 5GHzVCOs」論文，「文獻3」為電機電 子工程師協會(IEEE，Institute of Electrical and Electronic Engineers)於西元2002年7月固態電路會刊第37卷第7期 第 953 至 958 頁（Solid-state Circuits，VOL· 37，NO. 7, PP· 953-958)所發表之「Lifluence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-um CMOS technology」論文。從表1可以看出，應用 本實施例電感器佈局之壓控振盪器之效能與習知技術相當 (甚至優於習知技術），然而本實施例所佔晶片面積卻是 最小的。 請同時參照圖3A與圖3B，設計者可視其需求，選擇 性地將主動區域中之敏感元件配置於主動區域邊緣，以改 善耦合效應。例如，本實施例將電晶體131與132、二極 體121與I22等主動元件配置於主動區域之下侧邊緣處（靠 近電感器101與102之導電路徑）。 另外’設計者可視其需求，選擇性地將遮蔽層 (shielding layer)配置於電感器與基底之間，以改善耦合 效應。前述遮叙層（未纟會示）可以依照晶圓薇之標準設計 規則而配置之。為避免產生寄生電容，本實施例亦可允許 設計者免除前述遮蔽層。 11 200820418 UMCD-2006-0227 21197twf.doc/e 壓控振盪器100之振盪頻率是由電感器1〇1、1〇2之電 感值以及電容器111〜114之電容值所決定。於本實施例 中，設計者可視其需求而先決定電感器101、102之佈局（即 決疋電感值），然後依據已確定之電感值以及目標頻率而 決定電容器111〜114之電容值（即決定電容器ηι〜114 之面積）。因此，本實施例更具有使電路設計更富彈性之 效果。 _ <、前述實施例中雖沿著前述主動區域邊緣之方向，而將 電感101與102之導電路徑分別配置於主動區域左侧邊 緣附近以及右侧邊緣附近，但其只是本發明之實施範例之 一。本發明之電感器佈局方式不應被限制於此。設計者亦 可以曰將電感器之導電路徑圍繞主動區域而成單圈線圈。圖 6A疋依照本發明說明電感器佈局之另一實施例。於圖 中電感器620之導電路徑圍繞主動區域61〇而成單圈線 圈。電感器620之導電路徑沿著主動區域61〇邊緣之方向， 而被配置於主動區域610邊緣附近。 _ 、叹汁者可視其需求而決定電感器620之導電路徑是否 ，接主動區域⑽邊緣，或者決定是否將電感器㈣之部 刀（曰或王口 p) ^電路徑豐覆於主動區域MO邊緣内側。圖 6B疋,依知本發明說明電感器佈局之另一實施例。於圖6B 中，電感益620之導電路徑依然圍繞主動區域61〇而成單 ，線圈，且電感器620之導電路徑依然沿著主動區域61〇 邊緣之T向而被配置於主動區域61〇邊緣附近。與圖6A 不同的是’圖6B中電感器620之導電路徑有部分導電路 12 200820418 uivil,j^-zu06-0227 21197twf.doc/e 徑疊覆在主動區域610邊緣内侧。圖6C是依照本發明說 明電感器佈局之另一實施例。於圖6C中，電感器^ 導電路徑依然沿著主動區域61〇邊緣之方向而被配置於主 動區域610邊緣附近。與圖6A、4B不同的是，圖6c中 電感器620之導電路徑全部疊覆在主動區域61〇邊緣内侧。 1 上述諸實施例所示電感器之導電路徑可以被配置於單 一導電層中，例如將單圈線圈電感器之全部導電路徑配置 於最上層金屬層（top metal layer)中。設計者可視其需求 而將電感器之導電路徑配置於多個導電層中。 設計者可以視其需求，將電感器之導電路徑圍繞主動 區域而成多圈線圈。圖7A是依照本發明說明電感器佈局 之另一實施例。於圖7A中電感器720之導電路徑沿著主 動區域710邊緣之方向，於主動區域71〇邊緣附近圍繞主 動區域710而成多圈線圈（圖中以二圈代表之）。圖7b 中電感器720之導電路徑有部分導電路徑疊覆在主動區域 - 710邊緣内側。 _ 设计者可視其需求而將電感器620之導電路徑全部配 置於主動區域710外。圖7B是依照本發明說明電感器佈 局之另一實施例。於圖7B中，電感器72〇之導電路徑依 然圍繞主動區域.610而成多圈線圈，且電感器72〇之導電 路在依然沿著主動區域71〇邊緣之方向而被配置於主動區 域710邊緣附近。與圖7人不同的是，圖7B中電感器72〇 之導電路徑全部在主動區域71〇外側。 13 200820418 UMCD-2006-0227 21197twf.doc/e 上述諸實施例所示多圈線圈電感器之導電路徑可以被 配置於單一導電層中，例如將電感器之全部導電路徑配置 於最上層金屬層（top metal layer)中。設計者可視其需求 而將電感器之導電路徑配置於多個導電層中。 依照本發明之精神，在此提供一種電感器之製造方法 實施範例。此電感器之製造方法包括：於基底形成至少_ 主動區域’其中該主動區域包含至少一電路；於基底上方 ⑩ 形成一遮蔽層（shielding layer);以及於基底上方沿著主 動區域邊緣之方向，以及於主動區域邊緣附近，形成導電 路徑。其中，該導電路徑之兩端為電感器之兩端，而該遮 蔽層配置於電感器與基底之間。前述導電路徑可以圍繞主 動區域而成單圈線圈，或者前述導電路徑可以圍繞主動區 域而成多圈線圈。此導電路徑可以全部配置於單一導電層 (位於基底上方）中，亦可以被配置於多個導電層中。前 述導電層可以是最上層金屬層（t〇pmetallayer)，或是其 他金屬層或多晶矽層等。前述遮蔽層可以依照晶圓廠之標 • 準設計規則而配置之。此配置於該電感器與該基底之間的 遮蔽層被用來改善耦合效應，設計者可視其需求而選擇性 地免除前述遮蔽層相關步驟。 細上所述，本發明因沿著主動區域邊緣之方向，將電 感姦之導電路徑配置於主動區域邊緣附近，因此可以在不 增加禎外的成本與生產複雜度的前提下，以任何標準製程 形成電感器之佈局，達到節省電感器所佔晶片面積之功效。 14 200820418 υινι^-ζυυ6-0227 21197twf.doc/e 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在^ 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍定者 為準。 I疋有 【圖式簡單說明】 圖1是一種壓控振盪器之電路圖。 圖2是說明以習知技術實施圖1壓控振盪器之佈局圖。 圖3A是依照本發明實施例說明電感器佈局之立體圖。 圖3B是依照本發明實施例說明電感器佈局之俯視 圖4是依照本發明實施例說明圖3人所示壓控振盪器 佈局之控制電壓-輸出頻率特性圖。 圖5是依照本發明實施例說明圖3A所示壓控振盪器 佈局之位移-相位雜音特性圖。 圖6A是依照本發明說明電感器佈局之另一實施例。 圖6B是依照本發明說明電感器佈局之另一實施例。 圖6C是依照本發明說明電感器佈局之另一實施例。 圖7A是依照本發明說明電感器佈局之另一實施例。 圖7B是依照本發明說明電感器佈局之另一實施例。 【主要元件符號說明】 100 :壓控振盪器 101、1〇2 :電感器 、112、113、114 ··電容器 121、122 :二極體 15 200820418 UM(JD-2UU6-0227 21197twf.doc/e 131、132 : P型電晶體 141 :電阻器 300 ··基底 610、710 :主動區域 620、720 :電感器 BV :偏壓電壓電板 OUT+、OUT-:輸出電板"A 5Giiz 200820418 UMCD-2006-0227 21197twf.doc/e transformer-coupled CMOS VCO using bias-level shifting technique", Symposium, pp. 127-130, "Document 2" is "RFIC Symposium" in 2002 "High performance SOI and bulk CMOS 5GHz VCOs" paper published on pages 93-96, "Document 3" is the Institute of Electrical and Electronics Engineers (IEEE), in the July 2002 issue of Solid State Circuits. Lifluence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25, Vol. 7, pp. 953-958 (Solid-state Circuits, VOL 37, NO. 7, pp. 953-958) -um CMOS technology" paper. As can be seen from Table 1, the performance of the voltage controlled oscillator using the inductor layout of this embodiment is comparable to that of the prior art (even superior to the prior art), however, the wafer area occupied by this embodiment is the smallest. Referring to FIG. 3A and FIG. 3B simultaneously, the designer can selectively configure the sensitive components in the active area at the edge of the active area to improve the coupling effect. For example, in this embodiment, active elements such as transistors 131 and 132, diodes 121 and I22 are disposed at the lower side edge of the active region (the conductive path close to the inductors 101 and 102). In addition, the designer can selectively arrange a shielding layer between the inductor and the substrate to improve the coupling effect. The aforementioned masking layer (not shown) can be configured according to the standard design rules of Wafer. To avoid parasitic capacitance, this embodiment also allows the designer to dispense with the aforementioned masking layer. 11 200820418 UMCD-2006-0227 21197twf.doc/e The oscillation frequency of the voltage controlled oscillator 100 is determined by the inductance values of the inductors 1〇1 and 1〇2 and the capacitance values of the capacitors 111 to 114. In this embodiment, the designer can determine the layout of the inductors 101 and 102 (ie, the inductance value) according to the requirements, and then determine the capacitance values of the capacitors 111 to 114 according to the determined inductance value and the target frequency (ie, the determination The area of the capacitors ηι to 114). Therefore, this embodiment has an effect of making the circuit design more flexible. _ < In the foregoing embodiment, the conductive paths of the inductors 101 and 102 are disposed near the left edge of the active region and the vicinity of the right edge, respectively, along the direction of the edge of the active region, but it is only an embodiment of the present invention. one. The inductor layout of the present invention should not be limited thereto. The designer can also make the conductive path of the inductor around the active area into a single coil. Figure 6A illustrates another embodiment of an inductor layout in accordance with the present invention. In the figure, the conductive path of the inductor 620 is formed around the active area 61 into a single turn coil. The conductive path of the inductor 620 is disposed along the edge of the active region 61 and is disposed near the edge of the active region 610. _, stalker can determine whether the conductive path of the inductor 620 is connected to the edge of the active area (10), or whether to determine whether the inductor (4) of the inductor (曰 or Wangkou p) ^ electric path is abundant in the active area MO Inside the edge. Figure 6B shows another embodiment of the inductor layout in accordance with the present invention. In FIG. 6B, the conductive path of the inductor 620 is still formed around the active region 61 to form a single coil, and the conductive path of the inductor 620 is still disposed along the edge of the active region 61〇 at the edge of the active region 61〇. nearby. The difference from FIG. 6A is that the conductive path of the inductor 620 in FIG. 6B has a partial guiding circuit 12 200820418 uivil, j^-zu06-0227 21197twf.doc/e. The path is overlaid on the inner side of the edge of the active region 610. Figure 6C is another embodiment of an inductor layout in accordance with the present invention. In Fig. 6C, the inductor ^ conductive path is still disposed near the edge of the active region 610 along the direction of the edge of the active region 61. In contrast to Figures 6A and 4B, the conductive paths of inductor 620 in Figure 6c are all overlying the inner edge of active region 61. 1 The conductive paths of the inductors shown in the above embodiments may be arranged in a single conductive layer, for example, the entire conductive path of the single-turn coil inductor is disposed in the uppermost metal layer. The designer can arrange the conductive path of the inductor in a plurality of conductive layers depending on the needs thereof. Designers can turn the conductive path of the inductor around the active area into multiple coils, depending on their needs. Figure 7A is a diagram showing another embodiment of an inductor layout in accordance with the present invention. In Fig. 7A, the conductive path of the inductor 720 is along the edge of the active region 710, and a plurality of coils are formed around the active region 710 near the edge of the active region 71 (represented by two circles in the figure). The conductive path of inductor 720 in Figure 7b has a portion of the conductive path overlying the edge of active region - 710. _ The designer can place the conductive paths of the inductor 620 all outside the active area 710 depending on their needs. Figure 7B is another embodiment of an inductor layout in accordance with the present invention. In FIG. 7B, the conductive path of the inductor 72 依然 still forms a multi-turn coil around the active region .610, and the conductive circuit of the inductor 72 配置 is disposed in the active region 710 while still along the edge of the active region 71 〇. Near the edge. Unlike the person in Fig. 7, the conductive paths of the inductor 72A in Fig. 7B are all outside the active region 71〇. 13 200820418 UMCD-2006-0227 21197twf.doc/e The conductive paths of the multi-turn coil inductors shown in the above embodiments may be arranged in a single conductive layer, for example, the entire conductive path of the inductor is disposed in the uppermost metal layer ( Top metal layer). The designer can arrange the conductive path of the inductor in a plurality of conductive layers depending on the needs thereof. In accordance with the spirit of the present invention, an embodiment of a method of fabricating an inductor is provided herein. The inductor manufacturing method includes: forming at least an active region in the substrate, wherein the active region includes at least one circuit; forming a shielding layer over the substrate 10; and a direction above the substrate along the edge of the active region, And forming a conductive path near the edge of the active area. The two ends of the conductive path are both ends of the inductor, and the shielding layer is disposed between the inductor and the substrate. The aforementioned conductive path may form a single turn coil around the active area, or the conductive path may form a plurality of turns of the coil around the active area. The conductive paths may all be disposed in a single conductive layer (above the substrate) or may be disposed in a plurality of conductive layers. The conductive layer may be an uppermost metal layer (t〇pmetallayer), or another metal layer or a polysilicon layer. The aforementioned masking layer can be configured in accordance with the fab's standard design rules. The shielding layer disposed between the inductor and the substrate is used to improve the coupling effect, and the designer can selectively eliminate the aforementioned shielding layer related steps depending on the needs thereof. As described in detail, the present invention arranges the conductive path of the electric attraction in the vicinity of the edge of the active area along the direction of the edge of the active area, so that the standard process can be performed without increasing the cost and production complexity. The layout of the inductor is formed to save the chip area occupied by the inductor. 14 200820418 υινι^-ζυυ6-0227 21197 twf.doc/e Although the present invention has been disclosed in the preferred embodiments as above, it is not intended to limit the invention, and any one of ordinary skill in the art may deviate from the invention. In the spirit and scope, the scope of protection of the present invention is subject to the scope of the patent application. I 疋 [Simple description of the diagram] Figure 1 is a circuit diagram of a voltage controlled oscillator. 2 is a layout diagram illustrating the implementation of the voltage controlled oscillator of FIG. 1 in accordance with conventional techniques. 3A is a perspective view illustrating an inductor layout in accordance with an embodiment of the present invention. Figure 3B is a plan view showing the layout of the inductor in accordance with an embodiment of the present invention. Figure 4 is a diagram showing the control voltage-output frequency characteristics of the voltage controlled oscillator layout shown in Figure 3 in accordance with an embodiment of the present invention. Figure 5 is a diagram showing the displacement-phase noise characteristics of the voltage controlled oscillator layout of Figure 3A in accordance with an embodiment of the present invention. Figure 6A is another embodiment of an inductor layout in accordance with the present invention. Figure 6B is another embodiment of an inductor layout in accordance with the present invention. Figure 6C is another embodiment of an inductor layout in accordance with the present invention. Figure 7A is a diagram showing another embodiment of an inductor layout in accordance with the present invention. Figure 7B is another embodiment of an inductor layout in accordance with the present invention. [Description of main component symbols] 100: Voltage controlled oscillator 101, 1〇2: Inductors, 112, 113, 114 · Capacitors 121, 122: Diode 15 200820418 UM (JD-2UU6-0227 21197twf.doc/e 131, 132: P-type transistor 141: Resistor 300 · Base 610, 710: Active region 620, 720: Inductor BV: Bias voltage plate OUT+, OUT-: Output plate
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