TW200820256A - Parallel threshold voltage margin search for MLC memory application - Google Patents

Abstract

A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.

Description

W2914 200820256, IX. Description of the invention: [Technical field to which the invention pertains] The present invention is (iv) based on the multi-layer unit ("Μ1χπ), and _ is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ [Prior Art] = Flash memory cell storage - floating gate structure or other storage of stored charges. _Charge voltage ((10). In the 1 action, read the gate of the battery body, and the memory does not have this current h or the electrical _ η conduction (for example, conduction). In other words, during the reading action, the equivalent value of the memory unit may be assigned a numerical value of "", while the reading is done; the transmission is very small or there is no transmission current π 乍 乍 〇 之 之 。 。 。 。. How to add to this electric structure and = the storage structure is removed, the programming and erasing of this memory unit P 'change this stored value from 1 to Q. This charge system _ , the structure is maintained until this It is very popular to use this document to maintain this information in the case of He Jicun and the company. In addition, the flash memory can be provided by providing different quantities. _ = up to the table to store) the value of the data on the basis of the date, a little negative charge slightly increased the memory of the pity, a chat, the base charge is more advanced - step increase attached. - early 70 Vth' and more negative, (d) for mx mosquitoes this memory 5 200820256TW2914 single 兀 has been charged (programmed) to What state. For example, in the four-level quasi-unit that stores the poor position of the two digits, vth is assumed. The red c & is not privately edited or has been erased (it may be essentially not present) The threshold voltage of the state of the charge on the remaining structure of the charge," the ratio indicates the threshold voltage when a relatively small amount of negative charge has been transferred to the charge storage structure, and handsome 2 indicates that more negative charge has been transmitted. The threshold voltage at the charge storage configuration, and Vth3 indicates that the R voltage is not present when more negative charges have been transferred to the charge storage structure. One of the readings between Vth.舆Vthl (word line or The voltage sensed by the device will indicate whether the device has been programmed, and then 'apply a word line voltage between vthi and Vth2 and sense if the device is turned on or not' will indicate the device Whether it has been programmed to the first level or the > = level, etc. Alternatively, a fixed word line voltage is applied, and the current conducted by the unit is compared with the three reference currents simultaneously. In this way, Sensing all four of this MLC in a read action A memory array incorporating MLC is typically read in a well-known manner. This known % mode applies a read voltage (Vt) to a selected word line and then senses the current coupled to the bit line of the MLC block or The voltage, ΜΙχ block is activated by the word green by using a row of sense amplifiers. The typical read action is page type. For example, a 2 billion bit ("2Gb") memory device ( Or the memory array) can be designed as 〖28, 两 two thousand bytes ^2ΚΒ") page. The sensed value is loaded into a data latch or buffer, such as familiar flash The memory is well known to those skilled in the art. For example, see U.S. Patent No. 6,538,923 issued to Parker on March 25, 2003. A page is then programmed and read in the order of operation on the block of matching sense amplifiers 6 W2914 200820256. The sense amplifier includes a -base rate in the case of a continuous read operation of multiple f-levels, or a voltage or current system on the bit line of the group reference d which is used to parallel (5) take the level of the level. Or this group of benchmark comparisons to detect the batch of the unit, thus detecting the state of the memory. The Vth of these cells, which are programmed in an array and in an array of single pages, are programmed to be internal to the voltage of the threshold voltage. Therefore, the reference current applied to read one of the reading voltages of one mlc or the sense of the current used to sense the -MLC must fall within the distance between the Vth voltage distributions of the multi-programming level. This spacing is shown in the read voltage range or read capacity. It is important to verify that the MIX device has a sufficient read voltage range. The prior art technique for determining the read margin of the boundary of the distribution of each Vth level at each of the programmed levels is time consuming and uses a lot of storage capacity (tester memory) for different programming bits. Quasi-login_ Data read from the wafer. Therefore, there is a need for a technique for determining read tolerance that avoids the problems of these prior art techniques. SUMMARY OF THE INVENTION In accordance with the present invention, a method of operating a memory array is provided, the memory array comprising MLCs, each cell storing multiple bits. The method is for determining a read margin across a plurality of threshold levels of the array and includes the step of performing a programming operation to store a known data set in one of the tested blocks in the array, where Each cell in the tested block stores - the code in the multiple 200820256Tw29i4 bit code - where each multiple bit 70 code in the set of multiple bit codes corresponds to multiples that can be programmed into the cell _ (four) ^ one. Regarding the 2-digit code, this level will be more than /, ^ is only the % code has four 2-digit code, you can use the multiple bit code package in the memory of the four elements of the memory of the early morning. 、3 corresponds to a first threshold level and has a known total number of codes π of the sum total number α, ν ν 6 as shown in this one; s corresponds to a second threshold bit Known 乂 and thousands of 匕 know the total number of codes and so on. After the execution of the operation, use a first word, 吟 仃 、, flat

φ a ^ sub-line voltage reads the block under test, the macro table is not programmed to a first programming level, 疋 1 + - the number of first memory cells; the first: =, and the decision is programmed to The second part is called the first brother of a younger brother. _ 篦 - Sing, Le - 匕顼 sum. The first read sum code is compared with the first P ▲ 关于 关于 关于 关于 关于 , , , , , , , , 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The sum code compares the information. The word line voltage is up to == the increment is stepwise, or the win is 1 ^ j X. One part of this specific range is stepped.

The change, while the read sum code and/or comparison information is registered for each stepped voltage. In a particular embodiment, the word line voltage is a word line voltage that reaches a particular range, e.g., stepwise in steps of 100 mV. The read sum code and/or comparison information regarding the registration of the word line voltage of the range is used to determine a read range between the first programming level and the second programming level, wherein the reading range is For a range of word lines, in this range, the applied word line voltage level produces a number of sum codes that are related to the known total number of blocks in the array under the array. match. In a particular embodiment, the memory array comprises two levels of 8 'W2914 200820256 elements per unit ("MLCn"), and the data set has a third known total of one of the codes corresponding to a threshold level. In this case, the first: total number table is not programmed to the first programming level, the second programming level is two. The plural number of MLCs, and the second known total number is represented by = standing position or brother II a multiple of the ranks.

And: the second read sum code is 'calculated a third read total::: two: the read sum code indicates that the second programming level is one of the second ^", --- the read sum code indicates that the first A programming level, a Cth number, a third 'programming level' - the first MLC reading number, and a second = indicating the number of the first total number of codes in the second compilation. The sum code hides the itr system and the younger brother - the known total is compared, the second has been compared with the third known total number, and the third read total code is tied to the specific one: the first total is provided ^ The layer unit ^^^ has been tested for another part of the body of a page, or a reading action - memory array or comparison information and the page reading range Use the sum code and /. The page read mode level and the second code light level between the memory array is tested: for subsequent page read action storage. Or, part., | block system one One of the pages of the ^1^ memory device is in a specific two-dimensional byte (214f -, the measured block of the memory array is one 14>About the Store on NI) page' and the read summa contains 15 digits<〇· for each of the four quasi-cell quasi-units N-1 level. Therefore, three read sums can be generated玛, and for the 2K bit 9 200820256TW2914 'tuple page, for each page with a total of 45 bits of information (2K Bytes page stores 16 Κ bits) can produce three 15-bit read sum codes. Therefore, more Generally speaking, for a test block comprising 2 bits, the first read sum code, the second read sum code, and the third read sum code comprise respective unit bit codes for tolerance testing or tolerance search. The analysis is performed as described in this group of bit codes, rather than the data of the 2W bits of this group, which substantially reduces the memory resources required for the test processing. Sum code and/or comparison information Alternatively, it may be used to confirm the correct operation. For example, if the read sum code is lower than the desired (known) sum code, another programming pulse may be applied to the selected one of the memory arrays. Memory unit and read the new sum code, and Comparing the new sum code with the expected sum code. The technique applied here is also suitable for a single level cell memory array. In a particular embodiment, reading each cell at the first word line voltage comprises two bits. The step of the MLC memory array includes simultaneously comparing: a cell current of a memory cell with a first reference value, a second reference value, and a third reference value to generate a two-dimensional data output, Indicating a programming state of one of the memory cells. In one embodiment, an integrated circuit (n 1C") having an MLC memory array includes a built-in self-test ("BIST") design (including logic), for example A state machine and other dedicated circuits, a processor controlled by software or a combination of processors and dedicated circuits, are designed to operate the MLC memory array in accordance with the techniques described above. In a particular embodiment, the BIST logic 200820256 dual 4 • provides a pass/fail result from 1C to a tester indicating whether any page in the array meets a certain minimum read tolerance. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described below with reference to the accompanying drawings, and the following detailed description is given as follows: [Embodiment] Please refer to Figures 1-6 for the MLC type. A detailed description of the techniques for read margin search in memory arrays.

10 Figure 1 is a graph 100 showing the read voltage Vt distribution of an MLC product exemplified by one of two bits stored per cell. The vertical axis represents the number of cells in a memory array programmed to a threshold level, and the horizontal axis is the Vt applied to the word lines of the MLCs, which will overcome the charge storage structure of the cell. Transfers charge and allows this unit to conduct current. The four distributions are displayed as levels L0, LI, L2, L3 (status or data values). For the purpose of discussion, the level L0 represents 11 one-bit data value, L1 represents 10 one-digit data value, L2 represents 01 one-digit data value, and L3 10 represents (10) one-digit data value; however, these performances It is optional, and other numerical definitions are also possible. The state (value) of the MLC can be determined by applying a read voltage to the word line of the MLC and sensing the current via the cell. For example, if the MLC is programmed to a threshold level LI, L2, or L3, then one of the read voltages within a first Vt tolerance 102 (eg, REF1) will not turn on the MLC (ie, arrive via via This unit conducts current above a reference level to the state of a bit line). When the current through the MLC is compared to a reference ratio of 11 200820256TW2914 ' (for example, by a sense amplifier), the user knows that the MLC is at the lowest level L0 (which often represents an erase unit). In a similar manner, voltages are applied to the word line in the vt range 104 of the second Vt tolerance 104 and the third tolerance 1〇6 to identify levels L1 and [2, and levels L2 and L3. Figure 2A shows the threshold voltage distribution for two different pages of an MLC memory product. The curves L0, LI, L2, L3 represent the distribution of the threshold voltage of the wafer within a certain range. Curves 204, 206, 208, and 210 represent the distribution of read voltages found in one of the pages within the wafer with respect to different programming levels. For example, page 0 (η Ρ 0 Π ) has a distribution 204 of threshold voltages for level L , and a distribution 206 of threshold voltages for level L1. The Vt range (read range) between L0 and L1 on P0 is the voltage difference WL_01-P0 between the high boundary of the distribution 204 and the low boundary of the distribution 206. Similarly, WL-12-P0 represents the Vt range between the high boundary of the threshold voltage distribution 206 of the level L1 and the low boundary of the threshold voltage 208 of the level L2 on P0, while WL-23JP0 Represents the high boundary of the distribution 208 of the threshold voltage φ at the level L2, and the Vt range between the low boundaries of the distribution 210 of the threshold voltage with respect to the level L3 on P0. The second page P4 has different distributions 212, 214, 216, 218 of the respective levels L0, LI, L2, L3. As mentioned above, the Vt ranges of P4 are milk-zero 〇>4^12 one? 4 and Zhayi 23-?4. In this simplified example, the narrowest read range for any page between any two levels is WLJ2_P0. MLC memory products typically have a minimum read range specification of 12 200820256 Na, (eg 300 mV). If WL_12_P0 is less than this minimum read range specification (ie less than 300 mV), then this product test fails. Different pages in an MLC memory product may and often must have different Vt ranges and have different read voltage ranges between different sets of values. The conventional read tolerance test method searches for the word line level from the lowest value of one of the specific ranges to a highest value, and records the result of sensing the stepped word line voltage. Vt tolerance (read range). These results are compared to a previously known set of programming data. The results of these records are analyzed to find the lower bound above this tolerance. The page read/step WL process is repeated three times per cell per cell MLC product (once per read range) until the entire MLC memory array has been read and tolerantly logged. This method has several drawbacks. The boundary of each level of each page is searched to calculate this read range, which takes a considerable amount of time. A large tester memory is needed to store the bit information for this entire wafer (for example, two billion bits in the above example). Logins from this entire wafer • The data is evaluated to calculate the boundaries of each read unit, which must be performed for each read range (e.g., three times in a four-bit MLC device). Figure 2B is a flow chart showing one of the prior art methods 200 for determining such read voltage ranges (Vt tolerance search) for an MLC type of memory. A reference value (e.g., reference level 1 ("REF1")) is set to represent a first data value (step 220) and is coupled to a sense amplifier array. The word line level applied to this page is set to the lowest level in a particular range (step 222) (either to the highest level or an arbitrary level). This page is read (step 224) by 13 200820256 tw2914, and this data is output and registered in this tester memory (step 226). If the full wafer is not being read (branch 228), the number of pages will increase (k+1) and the loop will be repeated until all pages in the memory are read at the word line level ( Branch 23〇). If the word line voltage is not at this maximum allowable value (branch 232), then the word line voltage is increased (j + 1) and this loop is repeated for each word line voltage value (branch 228) until this maximum is reached The word line voltage is up (branch. If this reference value is not this maximum reference value (eg ref3) (branch 10236), then this reference value is stepped mi) (eg from _ to REF2 or handed to just) and for each division Lay each word line crocodile repeats loops 228 and 232. After the word line voltage has changed stepwise for all three reference values (branch 238), the entire wafer's recorded data is analyzed (step 240) and the minimum read range of the wafer is determined (steps are taken from any of the pages) The narrowest term between the two values is taken. • Under the prior art, the reality of the present invention uses the read sum code (jS-read face code) to determine the minimum of the MLC memory product. The read range, rather than the Wang Bian film record, is the process used in Figure 2b. The read sum code represents the number of cells that are read (4) and read at each page towel at a given threshold level. In the bit red, there are three reading ranges, one between ^ and ", the second between li^ L and 2, and the third between 12 and u. Therefore, three are used. Read two = code. Other embodiments have more or less data levels, and the number of read voltage ranges corresponds to increase or decrease. For the sake of convenience of discussion, 200820256w29i4 two-element MLC will be used in an example. Medium, and will explain three confirmed mother code SUM1, SUM2, SUM3 Figure 3 shows the sum code generated in the MLC-type memory array relative to the programming quasi-parallel. SUM3 is the number of cells sensed at the programming level three L3. For example, if a page is two thousand bits Group, and each unit has two bits, then for SUM3[0 ·· 14], we will have a bit width 'this is because the most two number of units programmed into level L3 is 1 (think of this page) All MLCs have been programmed to L 3). The best of layer 3 is ^ 10 number is 〇 (which means that all pages do not have any programming MLC) 〇 SUM2 is for programming level L2 and L3 The number of sensed units of two thousand bytes may not be programmed into the MLC of the page of L2 or L3 (ie, each bit on the page is located in li or L〇),

Below, this number is 0, or all MLC systems are L2 or 1^3, in this case, ^1, this number is 16K. Therefore, SM2 also has a 15-bit wide sound / If SUM 2 is not 〇, the number of MLCs located at L2 can be determined by == stealing SUM3. ^ SUM 1 is the number of cells sensed by programming levels l 1 , L2 and L3. Furthermore, SUM1 has a 15-bit width, and the number of cells programmed to [I, u, and L3 may be determined using SUM1, SUM2, and SUM3. If the number of bits for SUM1 is zero, then all MLCs located on this page are assumed to be at L0. The entire two thousand-byte page can be represented using only 45 bits (three only 15 bits each). The expected values of SUM1, SUM2, and SUM3 are from before or after the data is to be loaded into the memory array. Continued ^^ The main sum code is after the MLC page has been programmed. If the summation mar is expected to match the read sum code, the word line (directly in the "positive center has been generated. In other words" by using a voltage applied to the sub-line (which is within the hard-tolerance range) to read the voltage Read page ® °, this internal logic controls the test read process of the MLC memory device, and uses the read (four) complex read cycle until a load buffer is full of a page = poor (refer to Figure 5A for reading) Take the structure as an example). The sum code of the page determined by the second "beats" (MLC level) is compared with the expected sum code of that page. For example, if the programming page has (SUM3 ' SUM2, SUM1) = (15, h OBFF,15, h 33FF,if h 3C00) ' Then L3 has 3071 (3Κ-1) bits; L2 has 10240 (10Κ) bits; L1 has 2049 (2K-1) Bit; and L0 has 1024 (1K) bits. So ' SUM3 = (3Κ-1) ; SUM2 = (13Κ-1) ; SUM1 (15Κ). _ However, after a read action, we can get new The sum code (SUM3, SUM2, SUM1) (15, h 0BFD, 15, h 33FF, 15, h 3C00). The new sum code is shown in L3 with two bits. , which is read as L2 under this read bias state (word line voltage). The third level reference level (1^^3) is wrong, and it means that if we want to get the correct data, REF3 should be adjusted lower. However, after a read action, if for the same data set, we get the read sum code (SM3, SM2, SUM1) = (15, h 0BFF, 16 200820256_4 • 15, h 33FF,15,h 3C02), then we will know that under this read bias state (word line voltage), there is one bit in L2, which is read as L1, and there are two in L0. The bit is read as L1. In this example, both REF2 and REF1 should be adjusted to read the correct data value for the entire page. The programming level L1 has a programming acknowledgment level PV1 (" Vt limit π) and an upper limit EV1 of L1, the programming confirmation level PV1 is typically located below the allowable Vth distribution of the MLC of the memory array programmed to L1. Similarly, the programming level L2 has been programmed to L2 One of the lower limit of the MLC PV2 and an upper Vt limit EV2. The third programming level L3 has a similar limit, The legend is not shown in detail. A similar technique can be applied to an SLC-style memory cell array of one unit per cell. The following describes an MLC type for testing read tolerance according to an embodiment of the present invention. The method of operation of the memory array. The first and second desired sum codes are calculated from the array data (i.e., the data to be programmed or programmed into an MLC test block, such as a page selected by one of the MLC memory devices). The first desired sum code represents the number of MLCs to be programmed into at least one first programming level (i.e., the total number of cells programmed to a first programming level and a second programming level). The second desired sum code represents the number to be programmed into a second programmed level. The MLC in the memory array (e.g., page) is taken from various word line voltage terms and the sum code of the brothers and brothers is calculated. In one embodiment, the initial word line voltage is the lowest allowed word line voltage, and after reading the MLC, the 17 2 〇〇 820256rW2914 " word line voltage is increased. Alternatively, the word line voltage is turned high or low, or otherwise changed to obtain the desired comparison information. The first read sum code represents the number of MECSs read at the first programmed level or the second programmed level (i.e., the total number of cells read at l 1 and L2). The second read sum code represents the number of MLCs read at the second programmed level. The read sum code pattern for each word line voltage is compared to the corresponding expected sum code. In some embodiments, the word line voltage, particularly to sense the entire range of programmed levels, is evaluated. Or, the word line range. I am only able to estimate it. It is generally indicated that the sum code comparison information of the word line voltages for which the read total code system matches the expected sum code is stored. A read range (vt tolerance) between the first programming level and the second programming level is determined based on the sum code comparison information. 4 is a flow chart showing an operation method 411 of an MLC-type memory array according to an embodiment of the present invention, for indicating whether a wafer passes a read tolerance test, and the operation method is preferably performed by BIST logic on a wafer. . Xin ▲ species only check, and   Shoufang to use based on the information read from this page, than the total of ^ 45 bits (in the 2K byte page is two yuan per unit) and f The 45-bit το sum is consumed, and this check sum method is used to determine whether the page take action has passed or failed. The pass/fail beta system is 45 digits (each SUM1, SUM2, and SUM3 is 15 digits), and non = = 2K bytes for each page used in the conventional method σί1 & can improve test time , to reduce the need to perform Vt tolerance testing, and to promote the built-in self-test (nBlSTn) of 1C with MLC-type memory array. 18; W2914 200820256, according to the method shown in Figure 4, the expected sum code is calculated from the page data value of the MLC array to be programmed as a page, or the sum code is otherwise provided. The desired sum code is expected to be read and stored for access by the test logic (step 412). The word line level is set to an initial value (e.g., the lowest word line voltage for a particular read operation) (step 414). The page is read to produce a read material (step 416). Using this read data, you can determine the read sum code and load the read sum code into the step

The values in the comparison are compared to provide a comparison result for each word line level (step 418). The result of the comparison regarding the word line level is stored (step 42〇). Referring to Figure 5C, it can be seen that the comparison result can be stored as a simple one-bit pass/fail value for each word line level for each threshold level of the cell. If the entire wafer is not evaluated by this wordline level (branch 422), then the page value is incremented and the loop continues until the full wafer has been evaluated (branch 424). 90 The line position is expected to be evaluated, and if there is no word line level (branch 426) that is allowed for this read action, then the face is leveled by a word line (1 + 1). In order to increase the similarity of the 5C chart - the set of funds. Or, the value of this word line is recorded and the maximum allowed value is reduced and decreased when each person passes the loop, or the value of the word line is opened 7 each time to 'change to another value, until there is a leap; It is evaluated. Similarly, the page can be evaluated with the value of all word lines of interest as it continues to the next page. Other examples have steps to replace the order. After evaluating the full wafer with all the word line values of interest (branch 19 200820256, · 428), calculate the minimum read range (step 43〇), which is further explained below with reference to Figures 5A-5c. Figure 5A is an example of a sensing structure 500 that is used to simultaneously read two bits in each cell. The bit line voltage load circuit 5 〇 supplies the load current from the clamp circuit 504B to the ΜΙχ cell 5 〇 2 and supplies the load current to the two reference cells REF, REF 2, and foot 3 in a similar manner. The load circuit 5〇4A of the 70G line of the single 7G is controlled by a sensing enable signal SENB, and such load circuits on the reference unit bit lines are always set in this example. The reference cells are programmed using a circuit test, a circuit programmer, and a on-wafer reference programming circuit to enable them to have different threshold voltages. When a word line voltage (WL) is applied to such reference cells and ΜΙχ cells 5〇2, each will generate a different reference current IREF1, lRm, 丨, and the MLC cell 502 will generate an ICell 〇 read action representation MLC Unit 502 has been programmed to which of the four programming levels (L0, LI, L2, L3). The reference cells are biased such that each reference cell conducts a reference current that is inversely proportional to the associated programming level, Vt. The sense amplifiers 506, 508, 510 compare the ICell with I_, hm, and I to generate data values], D2, and D3, respectively. If the current through the MLC unit 502 is greater than a reference current, it represents the Vfh of the MLC unit that is tied to the reference unit. For example, if ICELL is greater than IREF1, sense amplifier 506 outputs a di value of logic "丨". Other sense amplifiers operate in a similar manner, from these sense amplifiers 5〇6, 508, 510 20 200820256; r fine a/u · FW2914 data values (ie, logic "1" or logic "0&quot ;) D1, D2, D3 are provided in parallel to a data calculation block 512.

The data calculation block generates a two-dimensional data output Dm indicating which of the MLC units is programmed. For example, if the MLC unit is at the programming level L0, then the ICell is greater than their ΙκΕΠ, greater than IREF2, and greater than Im3, while the data calculation block outputs DoiTT = 11 ("壹壹,,"). Similarly 'D 〇UT = 1〇(“壹壹”) indicates that this MLC unit is programmed to L1, etc. Table 1 shows the representative relationship between the sense amplifier output and DoiJT: Table 1 D1 D2 D3 D〇UT 1 1 1 11 0 1 1 10 0 0 1 01 0 0 0 00 Figure 5B shows a summary code calculation area according to one of the embodiments. The sum code block uses a standard logic comparator and an adder area, thus omitting detailed operations. Description: Data output from a set of data calculation blocks (Example D 512 also see Figure 5A, 512, D_) (for example, 52 ° ° is provided to the three comparators for multiple units of crying ^ 524, 526. In this example, 64 parallel units are evaluated using a parallel sense amplification block. It is familiar with this technique to operate other numbers of sense amplifiers from none to level. 21 200820256 一-«面m · rW2914 L2 or L3 level unit. Comparator output is provided to The 528 is operative to generate a read, which is stored in the epoch temporary crying 53 第二 the second comparator bank 524 compares the plurality of data outputs with a Q1 or 〇〇 value indicating a single &amp of the L2 or L3 level programmed And / out to the second two adder 534 to generate SUM2, which is stored in a second 16-bit register 536. The third comparator error 526 compares a plurality of data output and 〇〇 values, which represents The cells are programmed to the L3 level; and the outputs are provided to a third adder 538 to generate SUM3, which is stored in a third 16-bit register 540. First, second, and third Comparator banks 522, 524, 526 operate in parallel and cooperate with adders 528, 534, 538 to produce SUM1, SM2, SUM3 in parallel. The number of cells programmed to the L3 level is represented by SUM3. Programming to L2 The number of cells is determined by subtracting SUM2 from SUM3 (see Figure 3), and the number of cells programmed to the L1 level is determined by subtracting SUM1 from SUM2. The remaining cells are located at l〇 (Erase) Level. In other words, during a single read of 64 MLCs, the sum code SUM1, rang SU M2 and SUM3 indicate how many of the 64 MLCs are located in U, L2, and L3. It is known that the total number of units in the test block also allows us to determine the number of units located in L0, in other words, the total number of units minus SUM1. Using these techniques, a single read sequence can be used to identify MLC arrays that are programmed to different levels. There is no need to repeatedly read the array with many word line voltages for each programming level (compare Figure 2B, Reference numeral 236). Fig. 5C shows a truth table using the technique described herein for tolerance measurement, which is related to the MLC memory of one page in 1C. In the first column of the chart 22 PW2914 200820256, the word 'Green' γ is displayed and the increase of 4 volts starts at 4.5V and ends at 6.1V memory matrix - the specific range ^ ^ to ^ / This nREFl error? ,, the first 歹j sub-line electric dust. The figure in this chart is labeled as the comparison information, and the first reference level 1 shows that the sum of the first reference levels is wrong. Or, the number of units of the REF1 that indicates the level of the REF1, which indicates the level of the U County (four), is matched with the expected number indicated by SUM1, and “〇"

, # : The eyes match each other. Marked as "REF2 error on this chart? The π::1 歹丄9 series shows no comparison information about the sum of the second reference levels, and the level of _, _ _ is wrong for that word line voltage. Alternatively, starting from the lowest word line voltage (in this example, 4·5 ν), a page read operation is performed, and the sum code for all three levels is compared with the expected code. For this low word line voltage, a comparison of all three sum codes will indicate a fault, reminiscent of REF1, REF2 and REF3 should be adjusted (REn may be too high) or the word line voltage will leave the appropriate tolerance. When the word line voltage is increased (in this case, it reaches 4·8V), SUM1 will become correct (REFi error = 〇 (pseudo)), because the correct one is programmed to be the absolute sum of LI, L2 and L3? Take the number of cells, which means that the level L2 does not match /, the expected number represented by SUM1, and "〇 indicates that these numbers match each other. This chart is marked with „REF3 error? The third column of „ shows the comparison of the sum code of the third reference level, which indicates that the word of Peng is wrong with the word line voltage. Or, "1, the third column indicates the unit of reading The number 'it indicates that the level L3 does not match the expected number represented by s brain, leak and SUM1, and "〇" indicates that these numbers match each other. 23 FW2914 200820256 The total number of MLCs will be read with this Vt. However, there is no difference between the number of cells programmed at different levels (see Figure 3, SUM1). SUM2 and SUM3 will be wrong (Rej?2 error=1, REF3 error=1) ‘Assume that there are certain MLCs located on L2 and L3 on this page. When the word line > 1 continues to increase to the maximum allowable value for a page read operation, the result displayed on the truth table 500 can be obtained. Numerical values and conditions are for illustrative purposes only and are provided for purposes of illustration and discussion only. The range of read voltages between each level can be determined from the data showing the chart for Figure 5C for each reference on this page. It can be seen from Fig. 5C that the reading range for the word line voltage is from 4.8V to 5.2V for REF1, which means that there is 400 mV between L0 and L1. Similarly, the read range for word line voltage versus REF2 is from 5.0 V to 5.4 V, which means 400 mV between L1 and L2. The reading range of the word line voltage is from 5.3 V to 5.6 V for REF3, which means that 3 〇〇 my is between L2 and L3. This processing is repeated for other pages of MLC memory arrays ("full wafer readout)) and obtains a minimum read voltage range. BIST can be implemented by providing a minimum read range value to a tester. = 2 The BIST logic on the wafer automatically performs a full-wafer read operation', while the word line voltage is stepped across its range. μ or test H stores the read wire, and calculates these totals (4) = ίΓτΐί See section 6. Figure) and allowable (limb) minimum read mode 7 BIST logic can optionally pass the pass of the IC chip, the individual page pass/fail information can be set to set the MLC book array to "be The lock surface is lost ^ ' 夭 页面 页面 而 而 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 While this reduces the total amount of memory available to the consumer on the IC, it allows for the use of one or more pages 1C that cannot pass the minimum read range specification. Figure 6 shows an illustration of a test system 600 for testing a 1C 602, while the 1C 602 has built-in self-test BIST logic 6〇4A, 604B, 604C (to simplify the description of the test flow, only shown as multiple Function block). For example, BIST logic can be embedded in 矽 or other 1 (: semiconductor material, or temporarily loaded into one of the programmable logic sections of the IC. BIST logic implicitly controls the MLC memory array during page-to-face read operations The word line voltage is supplied by the tester or provided on the wafer. The number of pages of the MLC P train 606 is estimated by these allowable word lines. As described above, the WST logic 604 stores these reads. Taking the result, calculate the sum of the three sum codes. The sum of the sum codes obtained from these read actions and the specific (allowable) minimum read range. The selectable BIST logic provides the pass φ 匕/failed bucks. To test benefit 608. Alternatively, these sum code values are provided to (iv) mu, which compares these sum and (4) sum code values i and the minimum read voltage range for such pages or this IC. In the embodiment, the BIST logic (9) provides a failure value if any of the pages in the MLC array are not 7G into any minimum read range specification. Compared to the prior art techniques discussed based on Figures 2A and 2B, Embodiment of the present invention There are several advantages. The _, does not need to find the voltage boundary of each word line of each level, because this reading range is directly determined from these sum codes. I secondly, it is not needed. Store this bit information about the overall crystal (the entire memory list) and only store the expected her and the code ' to compare with the read total code. The third 'login data is the sum: the yuan is the parent information' instead of The overall chip does not need to repeat this read operation three times for three different reference values, because the parallel read system for all three reference levels is executed to generate the sum code. Embodiments of the invention provide reliable testing that achieves vt tolerance with fewer test times, while some embodiments include BIST. The embodiments described herein are applied to multiple bit cells based on MLC technology. Also based on SLC technology In order to apply this technique to a single bit early, in summary, although the present invention has been disclosed above in a preferred embodiment, = is not defined by (10). The present invention has In the spirit and scope of the present invention, # can be used for various = and retouching. Therefore, the protection of the present invention

The scope defined by the patent scope shall prevail. <A. Month 26 'W2914 200820256, [Simplified Schematic] Figure 1 shows the Vth distribution of the multiple threshold levels of the illustrated MLC products. Figure 2A shows the distribution of the threshold voltage cells of the MLC memory products for two different pages. Figure 2B shows a conventional method of determining the read voltage range of the mlc type memory. Figure 3 shows a graph used to illustrate the generation of the sum code. Figure 4 is a flow chart showing the operation of the mlc-type memory array in accordance with an embodiment of the present invention. Figure 5A is an example of a sensing structure in accordance with an embodiment. Figure 5B shows an exemplary sum code calculation block 520 according to an embodiment. Figure 5C shows the sum code comparison information for the memory of one page in an iC. Figure 6 shows an illustration of a test system for testing 丨c with B丨s τ logic. 27 200820256rw2914 • [Main component symbol description] LO, LI, L2, L3: curve/level 100: Fig. 102: first Vt tolerance 104: second Vt tolerance 106: third Vt tolerance 200: method 204, 206, 208, 210: curve 10 212, 214, 216, 218: distribution 220, 222, 224, 226, 230, 234, 238, 240, 242: steps 228, 232: loop 411: method of operation 412, 414, 416, 418, 420, 424, 428: Step 500: Sensing Structure 502: MLC Unit • 504A: Load Circuit 504B: Clamp Circuit 512: Data Calculation Block 522: First Comparator Bank 524: Second Comparator Storage 526: third comparator storage 528: first adder 530: register 28 200820256rW2914 '534: second adder 536: second 16-bit register 538: third adder 540 · · Three 16-bit scratchpad 6 0 0: test system

602 : 1C 604A, 604B, 604C : Self Test BIST Logic 606 : MLC Memory Array / 29

Claims (1)

200820256rw2914_职』!/u - 1 VY 厶7, - X. Patent application scope: 1. An integrated circuit comprising: a memory array located on the integrated circuit; and the integrated circuit Logic, which is designed to: program a data set into one of the memory cell arrays, wherein the memory cell block comprises a plurality of memory cells; Within a range, repeatedly reading the memory block located at the word line voltages as voltages and voltages of the respective word lines within the range to calculate the read sum code information, the representation being located in the first programming a number of read memory cells and a number of read memory cells at the second programming level; and performing reading of the read sum code information on the integrated circuit and providing the read sum code information At least one action of one of the outputs on the integrated circuit. 2. The integrated circuit as described in claim 1 includes logic on the integrated circuit for analyzing the read sum code information and providing a pass/fail result. 3. The integrated circuit of claim 1, wherein the logic stores desired sum code information, which is expressed as a number of first memory cells in which the data set is programmed to a first programming level, and The data set is programmed to a second memory unit number of the second programming level, and the logic includes logic to compare the read sum code information with the desired sum code information. The integrated circuit of claim 1, wherein the memory unit block is composed of a multi-layer unit (n MLCn) of one page. 5. The integrated circuit of claim 1, wherein: the memory block comprises a multi-level cell having four programming levels; and the read sum code information comprises: a first read sum code Representing the number of first memory cells in the block sensed by the first programming level; a second read sum code representing the memory cells of the known data set 10 a sum of the first number and a number of second memory cells in the block sensed by the second programming level; and a third read sum code indicating the first of the memory cells The number, the second number of memory cells and the third number of one of the memory cells in the block sensed by the third programming level. 6. The integrated circuit of claim 5, wherein the block comprises 2N4 bits, and the first read sum code, the second counted sum code, and the third read sum code Contains the respective N, .bit codes. 7. The integrated circuit of claim 1, comprising a row of sense amplifiers, the sense amplifiers being configured to be compared in parallel during the application of one of the word line voltages in the range One of the blocks selects one of the cells and a plurality of references to indicate the programming level of the selected cell. 8. The integrated circuit of claim 1, comprising a row of sense amplifiers configured to compare a current from one of the selected cells in the block with a first reference The value, a second reference 31 200820256tw2914 —^ir/iyrwj//u ' i vv &quot; value and a third reference value are used to generate a two-dimensional data output indicating a programmed state of the selected unit. 9. The integrated circuit of claim 1, comprising logic for determining whether the read sum code matches the desired sum code information, and if the read sum code does not match, an additional programming process is performed. Applied to the memory unit block. 10. A method of operating a memory array, comprising the steps of: programming a known data set into a memory block; • providing desired sum code information indicating that the known data set is programmed to be a first a number of first memory cells of the programming level, and a number of the second memory cells programmed to the second programming level for the known data set; performing a test process comprising: at a plurality of word lines Repeatingly reading the memory blocks located in the word line electrical calendars within the range of voltages, calculating read sum code information for each word line voltage within the range, indicating the number of reads at the first programming level a memory unit and a memory unit located in the second programmed bit; and comparing the desired sum code information with the purchased sum code to provide for each word line voltage within the range The sum code compares the information; and analyzes the sum code to compare the tribute to determine the read tolerance of one of the memory blocks. 11. The method of operation of claim 10, wherein the memory array comprises a plurality of blocks, and the method further comprises performing the programming, providing, performing, and analyzing steps on the plurality of blocks for Decide whether any of the 32 200820256 face w blocks have a read tolerance that does not meet the specifications. 12. The method of operation described in claim 10, further includes the step of logging in the read sum code information. 13. The method of operation of claim 10, wherein the memory block is comprised of a multi-layer cell (''MLC'1) of one of the pages of a memory device. 14. The method of operation described in claim 13 of the patent application, further comprising the step of reading the page by using the read tolerance. 15. The method of operation of claim 10, wherein the memory block is part of a MLC memory device. 16. The operating method of claim 10, wherein: the memory block comprises a multi-layer unit having four programming levels; the expected sum code information comprises: a first expected sum code, which is represented Programming the known data set as a first programming level, a first memory sum number; a second expected sum code indicating that the first memory unit number is programmed for the known data set a sum of the number of second memory cells of the second programming level; and a third desired sum code indicating the number of the first memory cells, the number of the second memory cells, and being programmed for the known data set a sum of the number of third memory cells in a third programming level; and the read sum code information includes: a first read sum code indicating that the block is sensed at the first programming level a first number of memory cells; a second read sum code indicating the number of the first memory cells and 33 20082_〇256rw2914* is the second data level of the known data set in the block Measured a sum of the number of second memory cells; and a third read sum code indicating the number of the first memory cells, the number of the second memory cells, and sensing in the block with the third programming level The sum of the number of third memory cells. The method of claim 16, wherein the block comprises 2 bits, and the first ^read sum code, the second read sum code, and the third read sum code Contains the respective N bit codes. The method of claim 1, wherein the step of repeating reading includes coupling a unit to a sense amplifier for each word line voltage within the range, the sense amplifiers simultaneously comparing A current from the unit and a plurality of references to indicate the programming level of the unit. 19. The method of claim 1, wherein the step of repeating reading comprises coupling a unit to a sense amplifier, wherein the sense amplifier simultaneously compares one of the word line voltages within the range. A cell current of the memory cell is coupled to a first reference value, a second reference value, and a third reference value to generate a two-dimensional data rounding indicating a programmed state of the memory cell. A method for determining a read range tolerance in a memory array of an integrated circuit (&quot;ICn), the method comprising the steps of: a) from being to be loaded into a plurality of pages The data of the memory array provides a plurality of expected sum codes, each of the expected sum codes corresponding to each of the memory units, each of the C memory units being programmed on each of the pages to correspond to at least a plurality of the plurality of expected sum codes Programming level; 34 200820256W29l4 —j/ju ~ ^ yy ^ b) programming the memory array of the pages, each page containing a first memory unit programmed on the page to be a first programming level a number, and a number of second memory cells programmed to a second programming level on the page; c) setting a word line voltage to a first selected word line voltage; d) reading the voltage at the word line The memory array of the page to provide read data; e) calculating a read sum code for the page from the read data; • f) comparing the read sum code with a corresponding expected sum code to generate a comparison result, This period The sum code indicates the number of the memory cells programmed on the page to at least one of the first programming level and the second programming level; g) storing the comparison result, h) for the next two pages Repeat steps (e) through (h) until the memory array of all pages has been read; i) set the word line voltage to the next word line voltage, and repeat • steps (d) to ( h); j) repeating step (i) until all word line voltages within a selected range have been applied to the pages and the pages have been read; and k) from These comparison results calculate one of the 1C read range tolerances. 21. The method of determining according to claim 20, wherein: the step (e) of calculating the read sum code for the page comprises calculating a one corresponding to at least the first programming level. The first number is more than 35 200820256_4 times _ * person two / | 7fT13 J / / UX TT ' layer unit (&quot; MLCn) one of the first read sum code, and the calculation corresponds to being programmed to at least the second programming bit Comparing one of the second number of MLCs with the second bought sum code, comparing the read sum code with the corresponding expected sum code step (f) comprises: comparing the first read sum code with a first A summation code is expected to generate a first comparison result, and the second read sum code and a second expected sum code are compared to generate a second comparison result; and the step (g) of storing the comparison result includes: storing the The first comparison 10 results with the second comparison result. 22. The method of determining according to claim 21, wherein the step (k) of calculating the read range tolerance from the comparison results comprises: calculating a first read range tolerance and one for the 1C Second read range tolerance. 23. The method of determining of claim 20, wherein the word line voltages of the selected range span a particular maximum read range. 24. The method of determining according to claim 20, wherein the word line voltages of the selected range extend from a minimum allowable read voltage to a maximum read voltage. 25. The method of determining of claim 24, wherein the step (k) of calculating the read range tolerance occurs after the step (j). 26. The method of determining according to claim 20, wherein the step (f) of comparing the read sum code with the corresponding expected sum code to produce the comparison result occurs on the 1C. 36 200820256 一^/lViW3&lt;/li * 1.W2914 ' 27. A method of operating a memory array comprising the steps of: applying a programming process to program a known data set to include a plurality of memory block units An array of memory block cells; providing desired sum code information indicating that the known data set is programmed to be one of the first programming levels and the first memory cell number is programmed for the known data set Forming a second programming level, the number of second memory cells; reading the memory block located at a word line voltage, for each word line voltage meter in the range has been *1 bought the sum code The read sum code poverty indication indicates a memory unit located at one of the first programmed levels and a memory unit located at a read number of the second programming level, and compares the desired sum code information with The read sum code information; and if the read sum code does not match the desired sum code information, an additional programming process is applied to the memory unit block. 37