200816635 95-013 20314twf.doc/t 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種傳輸介面中斷系統，且特別是有 關於一種防止匯流排上資料遺失的傳輸介面中斷系統。 【先前技術】 在現今的電腦系統中’電腦與周邊裝置常用的溝通方 式為中斷請求(interrupt request)，也就是當電腦需要傳輪資 料或下達指令至週邊裝置時，電腦系統預先發出一中斷^ 求至週邊裝置，此時週邊裝置停止傳輸資料至電腦，= 待電腦傳輪指令或資料。 ，寻BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission interface interruption system, and more particularly to a transmission interface interruption system for preventing data loss on a bus. [Prior Art] In today's computer systems, the common communication method between the computer and the peripheral device is an interrupt request, that is, when the computer needs to transmit data or issue instructions to the peripheral device, the computer system issues an interrupt in advance^ To the peripheral device, the peripheral device stops transmitting data to the computer, and then waits for the computer to transmit instructions or data. ,Searching
•V ^舉例來說，目前鍵盤與電腦之間常用的匯流排為個人 系統=型介面(Personal System 2，PS2)，而此匯流排上包 1二貝料信號線以及一時脈信號線，此兩條信號線之二 =如圖！所示。目！中所包含資料信號s_與時脈^ ^ cLK’為PS2介面的傳輸協定中完整的一筆資料，且 月:、2過時脈信號線與資料訊號線傳輸此筆資料至電 需要發出中:1/鍵盤傳輸資料至電腦時’若電腦此時 信號 停止傳輪資料， ^間(例如⑽μθ，以告知鍵盤 介面的傳輪说—/鍵现荨待接收資料或指令。而在P S 2 位的時間在第伽見^ ’若電腦將時脈訊號Sclk設於低電 才門在^個時脈週期的上升邊卵㈣如)之前， 5 200816635 95-013 20314twf.doc/t 則電腦將忽略此筆資料，並且鍵盤必須在下 至電腦時，重新傳輸此筆·。反之，若電=貧1 ^設於低電位的時間在第10 _脈的上升么:; 則電腦將保留此筆資料，而鍵盤 ’ 時，不需重新傳輪此筆資料。 人傳輪讀至電腦 然而’在實際的傳輸情況下，以PS2介面為例 輸弟10辦脈週期的期間，若電腦正好發出巾至 Γ:• V ^ For example, the current bus bar commonly used between the keyboard and the computer is a Personal System 2 (PS2), and the bus bar includes a 1 bunker signal line and a clock signal line. Two of the two signal lines = as shown! Shown. Eye! The data signal s_ and the clock ^ ^ cLK' contained in the data are a complete data in the transmission protocol of the PS2 interface, and the monthly:, 2 over-clock signal line and the data signal line transmit the data to the power needs to be issued: 1 / When the keyboard transmits data to the computer, 'If the computer stops the transmission data at this time, ^ (for example, (10) μθ, to inform the keyboard interface of the transmission wheel - / key is now waiting for receiving data or instructions. And in the PS 2 bit time In the first glance ^ 'If the computer sets the clock signal Sclk to the low-powered door before the rising edge of the clock cycle (4), for example, 5 200816635 95-013 20314twf.doc/t the computer will ignore the pen Data, and the keyboard must retransmit the pen when it is down to the computer. Conversely, if the electricity = lean 1 ^ is set at the low potential at the 10th pulse, the computer will retain the data, and the keyboard will not need to retransmit the data. The person reads the computer to the computer. However, in the actual transmission situation, the PS2 interface is taken as an example. During the period of the 10th pulse cycle, if the computer just sends the towel to the Γ:
將，信號設於低電位)，且忽略所接收 “筆貝枓。但疋，若此時由於傳輸延遲或其他的原因 ，成週&裝置(例如鍵盤與滑鼠)判定此時脈信號ν 第10個時脈之後，才被電腦設於低電位，因此鍵盤在下一 次傳輸資料至電腦時’不會重新傳輪此筆資料。因而，造 成此筆資料的遺失，嚴重時可能整個電腦運作都出現 【發明内容】 有鑑於此，本發明的目的就是在提供一種傳輸介面中 斷系統，確保電腦與週邊裝置判定發出中斷要求的時間一 致，並防止發出中斷要求時資料的遺失。 本务明的再一目的是提供一種防止匯流排之資料遺 失方法，用以防止傳送中斷要求至匯流排時，匯流排上的 貢料遺失。 為達上述或其他目的，本發明提出一種傳輸介面中斷 系統，用以防止一匯流排上的資料遺失，此傳輸介面中斷 系統包括重置電路與邏輯電路。其中，當重置電路接收到 的時脈信號由第一邏輯狀態轉換至第二邏輯狀態之次數到 6 200816635 95-013 20314twf.doc/t 達一預設值時，則致能重置信號。而邏輯電路耦接至重置 電路，並接收重置信號，輸出中斷信號，當重置信號致能 時，禁能中斷信號，以停止發送中斷要求至匯流排。 依照本發明的較佳實施例戶斤述傳輸介面中斷系統，上 述之邏輯電路更接收一要求中斷信號，且上述之傳輸介面 . 中斷系統更包括一韌體單元，此韌體單元用以提供要求中 ‘ 辦彳§號至邏輯電路，當要求中斷信號致能且重置信號致能 ( 時，韌體單元持續致能要求中斷信號直到重置信號失能。 依照本發明的較佳實施例所述傳輸介面中斷系統，上 述之邏輯電路為一及閘，此及閘之第一輸入端接收重置信 號，其第二輸入端接收要求中斷信號，其輸出端輸出中斷 信號。 依照本發明的較佳實施例所述傳輸介面中斷系統，上 述之重置電路包含N個計數電路，其N值等於預設值，每 一計數電路各自包括一及閘與一 D型正反器。而此及閘包 .1 括第一輸入端、第二輸入端與輸出端。此D型正反器包括 D輸入端、Q輸出端以及反向時脈輸入端，其d輸入端摩馬 .· 接及閘的輸出端，其反向時脈輸入端接收時脈信號。其中， 第i+Ι個計數電路的及閘之第一輸入端耦接第丨個計數電 路的D型正反器之Q輸出端，最後一個計數電路的Β型 正反裔更包括反Q輸出端，其反Q輸出端|馬接第1個計數 電路、第i個計數電路與最後一個計數電路的及閘的第二 輸入端，第1個計數電路的及閘的第一輸入端接收一致能 7 200816635 95-013 20314twf.doc/t 電位VH，其巾。 、、依如、本發明的較佳實施例所述傳輸介面中斷系統，上 述之匯流排包括一資料信號線以及一時脈信號線，且重置 電路搞接日守脈信號線，以接收時脈信號，而上述之匯流棑 例如包括個PS2介面，並且連接至少一週邊裝置，其中週 •邊裝置包括滑鼠與鍵盤。 \ 〃為達上述或其他目的，本發明再提出一種防止匯流排 D ^料遺失方法。當匯流排上時脈信號由第—邏輯準位轉 第一邏輯準位之次數達到一預設值，則禁止發送中斷要求 至匯流排。 依照本發明的較佳實施例所述防止匯流排之資料遺 失方法，更包括提供一韌體單元，用以提出中斷要求。 依照本發明的較佳實施例所述防止匯流排之資料遺 失方法，上述禁止發送中斷要求至匯流排的步驟又可細分 為下列步驟：首先，判斷時脈信號由第一邏輯準位轉第二 y 邏輯準位之次數是否達到一預設值；之後，若時脈信號由 第一邏輯準位轉第二邏輯準位之次數未達到預設值時，則 韌體單元所發出之中斷要求將發送至匯流排；反之，若時 脈信號由第一邏輯準位轉第二邏輯準位之次數已達到預設 值時，則阻擋韌體單元所發出的中斷要求至匯流排。 依照本發明的較佳實施例所述防止匯流排之資料遺失 方法，上述之阻擋韌體單元所發出的中斷要求該匯流排的 步驟之後包括當韌體單元所發出的中斷要求被阻擔時，韋刃 8 200816635 95-013 20314twf.doc/t 體單元將延遲1定時間再次發出巾斷要求。 本發明透過在特定的時間阻擋或延遲發 可確保電腦與週邊裝置判定發出：Ϊ 的_二致，亚防止發出中斷要求時資料的遺失。 易愔為二=二,上3和其他目的、特徵和優點能更明顯 ，下文特+ #χ佳實施例，並配合所關式，作說 明如下。 u 。Set the signal to low level and ignore the received pen. But if at this time, due to transmission delay or other reasons, the device & device (such as keyboard and mouse) determines the pulse signal ν After the 10th clock, it was set to a low level by the computer, so the keyboard will not retransmit the data when the next time the data is transmitted to the computer. Therefore, the loss of this data may cause the entire computer to operate. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a transmission interface interruption system that ensures that the time required for the computer to determine the interrupt request is the same as that of the peripheral device, and prevents the loss of data when the interrupt request is issued. One object is to provide a method for preventing data loss of a busbar to prevent loss of tributary on the busbar when the transmission interruption request is made to the busbar. To achieve the above or other objects, the present invention provides a transmission interface interruption system for To prevent loss of data on a bus, the transmission interface interrupt system includes a reset circuit and a logic circuit, wherein when the circuit is reset The number of times the received clock signal is switched from the first logic state to the second logic state to 6 200816635 95-013 20314twf.doc/t reaches a preset value, enabling the reset signal. The logic circuit is coupled to The circuit is reset and receives a reset signal, and outputs an interrupt signal. When the reset signal is enabled, the interrupt signal is disabled to stop transmitting the interrupt request to the bus. According to a preferred embodiment of the present invention, the transmission interface interrupt is interrupted. The system, the logic circuit further receives a request interrupt signal, and the transmission interface. The interrupt system further includes a firmware unit, and the firmware unit is configured to provide a request to the logic circuit when the interrupt signal is requested. When the enable and reset signal is enabled (when the firmware unit is continuously enabled, the interrupt signal is required until the reset signal is disabled. According to a preferred embodiment of the present invention, the transmission interface interrupt system, the logic circuit is a gate The first input of the gate receives the reset signal, the second input receives the request interrupt signal, and the output outputs the interrupt signal. According to a preferred embodiment of the present invention In the interface interruption system, the reset circuit includes N counting circuits whose N value is equal to a preset value, and each counting circuit includes a gate and a D-type flip-flop, and the gate package. An input terminal, a second input terminal and an output terminal. The D-type flip-flop includes a D input terminal, a Q output terminal, and a reverse clock input terminal, and the d input terminal is connected to the output terminal of the gate. The reverse clock input terminal receives the clock signal, wherein the first input end of the i+th counting circuit is coupled to the Q output end of the D-type flip-flop of the second counting circuit, and the last counting circuit The Β-type positive and negative descent also includes an inverse Q output, its anti-Q output terminal | horse connected to the first counting circuit, the ith counting circuit and the last counting circuit and the second input of the gate, the first count The first input of the circuit and the gate receives the uniform energy 7 200816635 95-013 20314twf.doc / t potential VH, its towel. The transmission interface interrupt system of the preferred embodiment of the present invention, wherein the bus bar comprises a data signal line and a clock signal line, and the reset circuit engages the day-defining signal line to receive the clock. The signal, and the above-mentioned bus 棑 includes, for example, a PS2 interface, and is connected to at least one peripheral device, wherein the peripheral device includes a mouse and a keyboard. In order to achieve the above or other objects, the present invention further proposes a method for preventing busbar loss. When the number of times the clock signal on the bus is changed from the first logic level to the first logic level reaches a preset value, the transmission of the interrupt request to the bus bar is prohibited. The method for preventing data loss of a bus bar according to a preferred embodiment of the present invention further includes providing a firmware unit for requesting an interrupt request. According to the preferred embodiment of the present invention, the method for preventing data loss of the bus bar, the step of prohibiting the transmission of the interrupt request to the bus bar may be further subdivided into the following steps: first, determining that the clock signal is switched from the first logic level to the second Whether the number of y logic levels reaches a preset value; after that, if the number of times the clock signal is changed from the first logic level to the second logic level does not reach the preset value, the interrupt request issued by the firmware unit will be Send to the bus; otherwise, if the number of times the clock signal is changed from the first logic level to the second logic level has reached the preset value, the interrupt request from the firmware unit is blocked to the bus. According to a preferred embodiment of the present invention, the method for preventing data loss of a bus bar, the step of interrupting the blocking of the firmware unit to require the bus bar includes, after the step of interrupting the firmware unit is blocked, Wei Blade 8 200816635 95-013 20314twf.doc/t The body unit will delay the request for a predetermined time. The present invention prevents the computer and peripheral devices from making a decision by blocking or delaying the transmission at a specific time: Ϊ 二 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Yi Yi is two = two, the top 3 and other purposes, features and advantages can be more obvious, the following special + #χ佳example, and with the closed type, as explained below. u.
【實施方式】 、目丽的傳輸介面中，由於電腦與週邊對於發出中斷要 求的時間認定不同，而造成資料的遺失。因此，本發明提 出一種傳輸介面中斷系統與防止匯流排之資料遺失^法， 月色夠使電腦正常的發送中斷要求，又同時能夠防止匯产排 上資料的遺失。 ’ Μ 圖2為本發明實施例之防止匯流排之資料遺失方法的 步驟/”L程圖。首先，计數匯流排上的時脈信號(步驟S2 1〇)。 在本實施例中，匯流排例如為PS2介面，而此匯流排上例 如包括一資料信號線以及一時脈信號線。 之後，當時脈信號由第一邏輯準位轉第二邏輯準位之 次數達到一預設值，禁止發送中斷要求至匯流排（步驟 S220)。在本實施例中，此預設值例如為10，也就是當時 脈信號的第10個時脈由第一邏輯準位轉第二邏輯準位 時，將禁止發送中斷要求至匯流排。 圖3為本發明實施例之防止匯流排之資料遺失方法的 泮細步驟流程圖。清餐考圖3 ’首先’提供^ 一拿刃體單元， 9 200816635 95-013 20314twf.doc/t 用以提出中斷要求(步驟S31〇)。在本實施例中，此章刀體單 元包含於電腦中，並接收電腦中控制晶片之指令，以發出 中斷要求。 接下來，週邊裝置透過PS2介面開始傳輸資料至電腦 (步驟S32〇)。此時’ PS2介面上所包含之時脈信號線與資 - 料吼號線的時序圖如前面圖1所示。 ' 之後，接收端接收到PS2介面上的時脈信號，並計數 (" 此時脈信號的週期（步驟S330)。 接下來，接收端判斷時脈信號由第一邏輯準位轉第二 邏輯準位之次數是否達到一預設值(步驟S340)。在本實施 例中，此駿值為1G，而第—邏輯準位為此時脈信號的高 電位，第一邏輯準值為此時脈訊號的低電位，也就是說在 步驟S340中，判斷時脈信號是否到達第1〇個時脈週期。 之後，若日守脈^號由第一邏輯準位轉第二邏輯準位之 次數未達到預設值時，則允許勃體單元 。將傳送至PS2介面(步驟⑽);反之，若時士 邏輯準位轉第二邏輯準位之次數已達到預設值時，阻擔韋刃 體單元所發出的中斷要求傳送至PM介面(步驟:在 本實施例中，當時脈信號到達第Π個週期時，又允許中斷 要求傳送至PS2介面，以防止資料的遺失。 最後，當韋刃體單元所發出的中斷要求被阻擋時，韋刃體 單元將延遲-預定時間後，再次發出中斷要求（步驟 S370)。在本實施例中，若第1〇個時脈週期中，韌體單元 200816635 95-013 20314twf.doc/t 並未發出終端要求時，步驟S370將可省略。本領域具通 常知識者應當知道，步驟S370的實施方式也可例如為韋刃 體裝置在發出一中斷要求後，偵測所發出的中斷要求是否 已被傳送至PS2介面，當偵測出所發出的中斷要求被阻播 時，將持續發出中斷要求，直到偵測出中斷要求已被傳送 至PS2介面。 由上面描述的實施例可觀察出，在習知的pS2介面 中’若發出中斷要求的時間接近第10個時脈的上升邊緣 日守，則容易發生資料遺失。然而，本發明之實施例利用在 部份時脈週期中阻擋中斷要求，將能夠禁止中斷要求在接 近第10個時脈的上升邊緣時發出，也就能夠防止匯流排上 資料的遺失。 圖4為本發明實施例之傳輸介面中斷系統方塊圖。請 翏照圖4，當重置電路41〇所接收到的時脈信號由一 =一邏輯狀態轉換至一第二邏輯狀態之次數到達一預設值 日守則致此重置信號sRST。而當邏輯電路43〇接收到重置 乜唬SRST致能時，邏輯電路43〇將禁能中斷信號&，以停 止發送中斷要求至匯流排。 圖5為本發明實施例之傳輸介面中斷系統的詳細電路 方塊圖。本實施例中此匯流排例如為PS2介面，而PS2介 面上包^時脈信號線與資料訊號線之信號時序如圖1所 示面所連接的週邊裝置例如包括滑鼠與鍵盤等等。 σ月麥恥圖5，傳輸介面中斷系統包括重置電路510、 200816635 95-013 20314twf.doc/t 邏輯電路530與韌體單元550。其中，重置電路51〇接收 匯流排上之一時脈信號sCLK(時脈信號Sclk如圖1所示）， 並輸出一重置信號SRST。韌體單元550用以提供要求中斷 t號SIRq。而邏輯電路530搞接至重置電路與勃體單 兀550，並接收重置信號Srst與要求中斷信號&叫，輸出 一中斷“號s〗。在本實施例中，韌體單元55〇接收電腦中 控制晶片之指令，以發出要求中斷信號&叫。 圖5中重置電路510包括N個計數電路，此n值等 於一預設值，在本實施例中，N值例如為1〇，也就是重置 電=510包括10個計數電路，且每個計數電路在圖$中分 別才示不為512-1〜512-10。每個計數電路^孓丨〜〗12_1〇又各 自包括一及閘（and gate)514-l〜514-10與一 d型正反器 (D-typeFlipFlop)5l6_i〜516_1〇。而每個及閘 包括第一輸入端、第二輸入端與輪出端。每個D型正反器 1 516 10包括D輸入端、Q輸出端及反向時脈輸入端。 一重置電路51〇中的⑺個計數電路512-1〜512-10内的 兀件輕接關係相同的部份為〇型正反器 輸入令而|馬接及閘514-1〜514-10的輸出端，並且d型正反器 51=1〜516-10的反向時脈輸入端皆同樣地接收ps2介面上 ?夺脈信號。以計數電路5m為例，其D型正反器^ 白、D輪入端輕接及閘淋i的輸出端，並且^型正反器 16 1的反向時脈輸人端接收時脈信號。 除了计數電路512-1之外，其他的計數電路 12 200816635 95-013 20314twf.doc/t 512-2〜512-10内的及閘514_2〜514-10的第一輸入端皆耦接 至前一個計數電路512-1〜512-9内的D型正反器 516-1〜516-9的Q輸出端。舉例來說，計數電路512_2内 的及閘514-2之第一輸入端耦接至計數電路512_丨内的D 型正反器516-1之Q輸出端。 - 特別的是，計數電路512-10内的D型正反器516-10 . 更包括反Q輸出端，其反Q輸出端耦接所有及閘 5丨4"4〜514_10之第二輸入端。而計數電路512-1内的及閘 514-1的第一輸入端接收一致能電位Vh。 卜在本實施例中，重置電路510内的元件分為第丨個至 第N個計數電路，其中每一計數電路各自包括一及閘盘一 D型正反器。每個及閘包括第一輸入端、第二輸入端與輸 $端。每個D型正反器包括D輸人端、Q輸出端以及反向 時脈輸入端。而每個計數電路中的D型正反器之D輪入端 耦接至及閘的輸出端。每個計數電路中的D型正反=之反 (j 向日守脈輸入端接收該時脈信號。而第i+Ι個計數電路的及 閘之第一輸入端耦接第i個計數電路的D型正反器之卩輸 出端，最後一個（第N個)計數電路的D型正反器更包括反 Q輸出端耦接於第1個計數電路、第丨個計數電 一個^電路的及閘的第二輸人端，第！個計數電路的及 閘的第一輸入端接收一致能電位VH，其中。 由重置電路510内的麵接關係可推知，當重置電路H0 所接收到的時脈信號ScLK由一第一邏輯狀態轉換至一第 200816635 95-013 20314twf.doc/t j輯狀=次數到達—預設輝值)時，則致能重置信 :二=施::值=電:為高電位，第二邏 …… 預δ又值為10，並且計數電路512-1的及 1弟—輸入端所接收致能電位VH為-高電位。 也就是說，當重置電路51〇中的D型正反器別 =夺脈信號sGLK第—個週期的負緣觸發時，d。型正反= 购之Q輸出端將輸出致能 ： 出低電位(在此設定每個D型正反器服⑷㈣初始 的Q輸出端皆一低電位），D型 ° 端將輸出高電位。 反③购〇之反Q輪出 以此類推可得知，當重置電路51 至下-級 的D型正反器516_/之反個^ 9 期，重置電路510 後，去重詈雷收…，Q輪出為皆輸出-高電位。最[Embodiment] In the transmission interface of the eye-catching, the time required for the interruption of the request by the computer and the periphery is different, and the data is lost. Therefore, the present invention proposes a transmission interface interruption system and a data loss prevention method for the bus bar. The moon color is sufficient for the normal transmission interruption request of the computer, and at the same time, the loss of the data on the production line is prevented. 2 is a step/"L process diagram of the method for preventing data loss of the bus bar according to the embodiment of the present invention. First, the clock signal on the bus bar is counted (step S2 1〇). In this embodiment, the sink The row is, for example, a PS2 interface, and the bus bar includes, for example, a data signal line and a clock signal line. Thereafter, the number of times the current pulse signal changes from the first logic level to the second logic level reaches a preset value, and the transmission is prohibited. Interrupt request to the bus bar (step S220). In this embodiment, the preset value is, for example, 10, that is, when the 10th clock of the current pulse signal is switched from the first logic level to the second logic level, It is forbidden to send an interrupt request to the bus bar. Fig. 3 is a flow chart showing the steps of the method for preventing data loss of the bus bar according to an embodiment of the present invention. The meal test chart 3 'first' provides a handle blade unit, 9 200816635 95- 013 20314twf.doc/t is used to propose an interrupt request (step S31〇). In this embodiment, the cutter body unit of the chapter is included in the computer, and receives an instruction to control the chip in the computer to issue an interrupt request. Peripheral device through PS The interface starts to transfer data to the computer (step S32〇). At this time, the timing chart of the clock signal line and the resource line line included in the PS2 interface is as shown in the previous figure 1. ' After that, the receiving end receives The clock signal on the PS2 interface, and counts (" the period of the pulse signal (step S330). Next, the receiving end determines whether the number of times the clock signal is switched from the first logic level to the second logic level reaches one. The preset value (step S340). In this embodiment, the value is 1G, and the first logic level is the high potential of the pulse signal, and the first logic value is the low potential of the pulse signal. That is, in step S340, it is determined whether the clock signal reaches the first one clock cycle. Thereafter, if the number of times the day clock is changed from the first logic level to the second logic level, the number of times does not reach the preset value. Then, the Bosch unit is transmitted to the PS2 interface (step (10)); conversely, if the number of times the logic level is changed to the second logic level has reached the preset value, the interrupt request from the Weaver blade unit is blocked. Transfer to the PM interface (step: in this embodiment, the pulse signal arrives at the During the cycle, the interrupt request is transmitted to the PS2 interface to prevent data loss. Finally, when the interrupt request from the blade body unit is blocked, the blade body unit will be delayed - after a predetermined time, the interrupt is issued again. Requirement (step S370). In this embodiment, if the firmware unit 200816635 95-013 20314twf.doc/t does not issue a terminal request in the first clock cycle, step S370 may be omitted. It should be understood by those skilled in the art that the implementation of step S370 can also detect, for example, that after the interrupt request is issued, the device detects whether the interrupt request issued has been transmitted to the PS2 interface, and when the detected interrupt request is detected. When blocking, the interrupt request will continue to be issued until the interrupt request is detected and transmitted to the PS2 interface. It can be observed from the above-described embodiment that in the conventional pS2 interface, if the time required for the interruption is close to the rising edge of the 10th clock, data loss is liable to occur. However, embodiments of the present invention utilize blocking interrupt requests during partial clock cycles, and will be able to inhibit interrupt requests from being issued near the rising edge of the 10th clock, thereby preventing loss of data on the bus. 4 is a block diagram of a transmission interface interrupt system according to an embodiment of the present invention. Referring to FIG. 4, when the reset signal 41 receives the clock signal from a = one logic state to a second logic state, the number reaches a preset value. The daily code causes the reset signal sRST. When the logic circuit 43 receives the reset 乜唬SRST enable, the logic circuit 43 禁 disables the interrupt signal & to stop transmitting the interrupt request to the bus. FIG. 5 is a detailed circuit block diagram of a transmission interface interrupt system according to an embodiment of the present invention. In this embodiment, the bus bar is, for example, a PS2 interface, and the peripheral timing of the signal timing of the clock signal line and the data signal line on the PS2 interface is connected to the peripheral device shown in FIG. 1, for example, including a mouse and a keyboard. The transmission interface interrupt system includes a reset circuit 510, 200816635 95-013 20314twf.doc/t logic circuit 530 and a firmware unit 550. The reset circuit 51 receives one of the clock signals sCLK (the clock signal Sclk is as shown in FIG. 1) on the bus bar, and outputs a reset signal SRST. The firmware unit 550 is configured to provide a request to interrupt the t-number SIRq. The logic circuit 530 is connected to the reset circuit and the body unit 550, and receives the reset signal Srst and the request interrupt signal & call, and outputs an interrupt "number s". In this embodiment, the firmware unit 55〇 Receiving an instruction to control the chip in the computer to issue a request interrupt signal & call. The reset circuit 510 in FIG. 5 includes N counting circuits, and the value of n is equal to a preset value. In this embodiment, the value of N is, for example, 1 〇, that is, the reset power = 510 includes 10 counting circuits, and each counting circuit is not shown as 512-1~512-10 in the figure $. Each counting circuit ^孓丨~〗 12_1〇 Including a gate and gates 514-l~514-10 and a d-type flip-flop (D-typeFlipFlop) 5l6_i~516_1〇, and each gate includes a first input, a second input and a turn-out Each D-type flip-flop 1 516 10 includes a D input terminal, a Q output terminal, and a reverse clock input terminal. A reset circuit 51 〇 in the (7) counting circuits 512-1 to 512-10 The same part of the light-contact relationship is the input of the 〇-type flip-flop and the output of the horse-connected gates 514-1~514-10, and the d-type flip-flops 51=1~516-1 The reverse clock input terminal of 0 receives the pulse signal on the ps2 interface in the same way. Taking the counting circuit 5m as an example, the D-type flip-flop is white, the D wheel is lightly connected, and the output of the gate is i. And the reverse clock input terminal of the ^ type flip-flop 16 1 receives the clock signal. In addition to the counting circuit 512-1, other counting circuits 12 200816635 95-013 20314twf.doc/t 512-2~512 The first input terminals of the gates 514_2 to 514-10 in the -10 are coupled to the Q outputs of the D-type flip-flops 516-1 to 516-9 in the previous counting circuits 512-1 to 512-9. For example, the first input terminal of the AND gate 514-2 in the counting circuit 512_2 is coupled to the Q output terminal of the D-type flip-flop 516-1 in the counting circuit 512_丨. - In particular, the counting circuit 512 D-type flip-flop 516-10 in -10. Further includes an inverse Q output terminal, the anti-Q output terminal is coupled to all of the second input terminals of the gate 5丨4"4~514_10. The counting circuit is in the 512-1 The first input terminal of the AND gate 514-1 receives the uniform potential Vh. In the present embodiment, the components in the reset circuit 510 are divided into the second to the Nth counting circuits, wherein each of the counting circuits includes One gate A D-type flip-flop. Each gate includes a first input, a second input, and a $. Each D-type flip-flop includes a D input terminal, a Q output terminal, and a reverse clock input terminal. And the D wheel-in terminal of the D-type flip-flop in each counting circuit is coupled to the output end of the gate. The D-type positive and negative of each counting circuit is reversed (j is received from the clock-gated input terminal) Pulse signal. The first input end of the i+th counting circuit and the first input end of the gate are coupled to the output terminal of the D-type flip-flop of the i-th counting circuit, and the D-type flip-flop of the last (Nth) counting circuit is further The anti-Q output terminal is coupled to the first counting circuit, the second counting electric circuit, and the second input end of the gate, the first! The first input of the counting circuit and the gate receives the uniform potential VH, wherein. It can be inferred from the face-to-face relationship in the reset circuit 510 that the clock signal ScLK received by the reset circuit H0 is switched from a first logic state to a 200816635 95-013 20314twf.doc/tj album = number of times arrives - Preset glow value), then enable the reset letter: 2 = Shi:: Value = Electricity: is high, the second logic... Pre-δ is 10, and the counting circuit 512-1 and 1 brother - The enable potential VH received at the input is - high. That is to say, when the D-type flip-flop in the reset circuit 51〇=the negative edge of the first cycle of the pulse-receiving signal sGLK is triggered, d. Type positive and negative = purchased Q output will output enable: low potential (here, each D-type inverter (4) (four) initial Q output is low), D-type ° will output high potential. The anti-Q round of the anti-3 purchase can be learned by analogy, when the reset circuit 51 to the lower-stage D-type flip-flop 516_/ is reversed, the reset circuit 510 is reset. Receive..., Q round out is output - high potential. most
LifITJ sCLK,^ 10 ，重置電路的D型正反器㈣之反q = 位轉為低電位’也就是致能了重置信號 當邏輯電路530接收到的f φ ^ ^ 雷路4ΠΠ肱枯Ab山“ 置佗號SRST致能時’邏輯 號SI。也就是說邏輯電路觸接 電路別求中斷信號Sirq同時致能時，邏輯 亚不曹依據中斷錢S而致能中斷信號SI，也 200816635 95-013 20314twf.doc/t 就月b夠停止1¾送中fe/f要求至匯流排。而在本實施例中，邏 輯電路為一及閘532，而及閘532之第一輸入端接收重置 信號SRST，及閘532之第二輸入端接收要求中斷信號SiRQ， 其輸出端輸出中斷信號Si。 當韌體單元550所發出的要求中斷信號被邏輯電 路530阻擂時，將會持續致能要求中斷信號&叫直到重置 信號sRST失能。也就是說，當韌體單元55〇發出要求中斷 仏號SIRQ後，將偵測所發出的中斷要求是否有順利地被傳 送至匯流排。當偵測出所發出的要求中斷信號&叫被邏輯 電路530阻擋時，韌體單元55〇將會持續致能要求中斷信 號SIRQ直到所發出的中斷要求順利地被傳送至匯流排。然 本領域具通常知識者應當知道，tt赠單元別所發出的 要求中斷信號SIRQ被邏輯電路53〇阻擋時，韌體單元55〇 也可延遲-段時間後(也就是當重置信號、失能時），再 次發出要求中斷信號SIRQ。 在本實施例中，當邏輯電路53〇致能中斷信號&後， 允許電腦發出巾斷要求至PS2介面，將時脈信號設於低電 位-段時帽如觸㈣’以告知週邊I置停止傳輸資料， 並要求鍵鮮待接收資料或指令。並且，由上述之傳輸介 面中斷系統可知，此系統防止電腦發出中斷要求的時間在 接近時脈錢的第H)個之上升邊緣，也就能夠確保電 腦與週邊裝置判定發出巾斷要求的時間—致，並防止發出 中斷要求時資料的遺失。 15 200816635 95-013 20314twf.doc/t 圖6為本發明另一實施例之傳輪介面中斷系統的詳細 ^方塊圖。請參考圖6，本實施例與圖5之實施例不同 之处在於邏輯電路63()更包含鎖器糾。此關器幻4 之^輸入_接至及閘632之輸出端，其D輸入端接收一 致月b電位VH ’其q輸出端輪出中斷信號&。在本實施例 中門鎖為634之L輸入端例如為一致能輸入#，而當及 間632輸出為一高邏輯準位時，由問鎖器、634之〇輸入端 接收的致能電位Vh，將致使問鎖器㈣直接致能中斷信號 & ’並拾鎖住及632所輸出的高邏輯準位，以允許電腦 發出中斷要求至PS2介面。 —雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何本領域具有通常知識者，在不脫離本發 明之精神和範_，當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示為習知技術中個人系統二型(PS2)介面上之 時脈信號與資料訊號的時序圖。 0 2為本發明實施例之防止匯流排之資料遺失方法的 步驟流程圖。 圖3為本發明實施例之防止匯流排之資料遺失方法的 詳細步驟流程圖。 圖4為本發明實施例之傳輸介面中斷系統方塊圖。 圖5為本發明實施例之傳輸介面中斷系統的詳細電路 方塊圖。 16 200816635 95-013 20314twf.doc/t 圖6為本發明另一實施例之傳輸介面中斷系統的詳細 電路方塊圖。 【主要元件符號說明】 S210〜S220、S310〜S370 :本發明實施例之步驟 410、510 :重置電路 430、530、630 ··邏輯電路 512-1〜512-10 :計數電路 514-1 〜514-10、632 :及閘 516-1〜516-10 : D型正反器 550 :韌體單元 634 :閂鎖器（latch)LifITJ sCLK, ^ 10, reset circuit D-type flip-flop (4) reverse q = bit turns to low potential 'that is, enable reset signal when logic circuit 530 receives f φ ^ ^ Ab Mountain "When the SRST is enabled" logic number SI. That is to say, when the logic circuit is connected to the circuit and the interrupt signal Sirq is simultaneously enabled, the logic sub-cause enables the interrupt signal SI according to the interrupt money S, also 200816635 95-013 20314twf.doc/t The monthly b is enough to stop the feeding of the fe/f request to the bus. In this embodiment, the logic circuit is a gate 532, and the first input of the gate 532 receives the weight. The signal SRST is applied, and the second input terminal of the gate 532 receives the interrupt request signal SiRQ, and the output terminal outputs the interrupt signal Si. When the request interrupt signal issued by the firmware unit 550 is blocked by the logic circuit 530, the signal is continuously enabled. The interrupt signal & call is requested until the reset signal sRST is disabled. That is, after the firmware unit 55 sends the request interrupt semaphore SIRQ, it will detect whether the interrupt request issued is successfully transmitted to the bus. When detecting the requested interrupt signal & When the circuit 530 is blocked, the firmware unit 55〇 will continue to enable the interrupt signal SIRQ until the interrupt request is successfully transmitted to the bus. However, those skilled in the art should know that the tt gift unit sends out When the interrupt signal SIRQ is requested to be blocked by the logic circuit 53, the firmware unit 55 can also delay the time period (that is, when the reset signal is disabled), and issue the request interrupt signal SIRQ again. In this embodiment, After the logic circuit 53 enables the interrupt signal &, the computer is allowed to issue a towel request to the PS2 interface, and the clock signal is set to the low potential-segment when the cap is touched (four)' to inform the peripheral I to stop transmitting the data, and request The key is not ready to receive data or instructions. Moreover, it can be seen from the above-mentioned transmission interface interruption system that the system prevents the time required for the computer to issue an interrupt to be close to the rising edge of the H) of the clock money, thereby ensuring the computer and the peripheral device. Determining the time required to issue the toweling request and preventing the loss of data when the request for interruption is issued. 15 200816635 95-013 20314twf.doc/t FIG. 6 is another embodiment of the present invention The detailed block diagram of the transmission interface interrupt system. Please refer to FIG. 6. The difference between the embodiment and the embodiment of FIG. 5 is that the logic circuit 63() further includes a lock correction. Connected to the output of the gate 632, the D input terminal receives the coincident monthly b potential VH 'the q output end of the interrupt signal & in the embodiment, the L input of the gate lock is 634, for example, the uniform input # When the output of the 632 is a high logic level, the enable potential Vh received by the input latch of the interrogator and the 634 will cause the interrogator (4) to directly enable the interrupt signal & And the high logic level output by 632 to allow the computer to issue an interrupt request to the PS2 interface. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention, and any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a timing diagram of clock signals and data signals on a personal system type 2 (PS2) interface in the prior art. 0 2 is a flow chart of the steps of the method for preventing data loss of the bus bar according to the embodiment of the present invention. 3 is a flow chart showing the detailed steps of a method for preventing data loss of a bus bar according to an embodiment of the present invention. 4 is a block diagram of a transmission interface interrupt system according to an embodiment of the present invention. FIG. 5 is a detailed circuit block diagram of a transmission interface interrupt system according to an embodiment of the present invention. 16 200816635 95-013 20314twf.doc/t FIG. 6 is a detailed circuit block diagram of a transmission interface interrupt system according to another embodiment of the present invention. [Description of Main Component Symbols] S210 to S220, S310 to S370: Steps 410 and 510 of the embodiment of the present invention: reset circuits 430, 530, and 630. - Logic circuits 512-1 to 512-10: Counting circuit 514-1~ 514-10, 632: and gates 516-1 to 516-10: D-type flip-flop 550: firmware unit 634: latch (latch)
ScLK ·時脈彳吕万虎 sRST :重置信號 S!:中斷信號 SIRQ :中斷信號 VH :致能電位 17ScLK · Clock 彳 Lu Wanhu sRST : Reset signal S!: Interrupt signal SIRQ : Interrupt signal VH : Enable potential 17