200816117 、九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種彳吕號驅動電路及方法，特別是 有關於影像顯示系統中的#號驅動電路以及驅動顯示元 件的方法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and method for a singular horn, and more particularly to a # driving circuit and a method for driving a display element in an image display system. [Prior Art]
一個影像顯不糸統中的顯τκ面板，如tft-LCD面 板，通常包括有一個顯示元件，且顯示元件中有一個具 有複數晝素的二維晝素陣列。這些晝素可藉由複數條資 料線以及複數條閘極信號線來控制。由數個串接之移位 暫存器（shift register，SR)組成的驅動電路則用來提供對 應的驅動信號使這些閘極信號線可以依序被啟動。 一般而言，每個移位暫存器（SR)包括有一個輸入 端、-個輸出端、-電源端以及數個時脈訊號端。移位 暫存器的輸出端連接到LCD陣列的—條閘極信號線，並 且每個間極信號線連接到晝素的一列。當驅動電路中的 第-個移位暫存器’第-移位暫存器，接收到一個起始 脈衝（start pulse)信號時，第一移位暫存器根據接收到的 時脈訊號，產生一個輸出脈衝信號〇UTl糾楚一 玉』乐一閘極信 號線。輸出脈衝信號OUT1也接到下〜個移位暫存哭、 第二移位暫存器’當作第二移位暫存器的起始信 號。弟一移位暫存器接著根據^一反向時脈訊號，產生 個輸出脈衝信號OUT2到第二閘極信說線。輸出脈衝作 0773-Α31994TWF;P2005127;jasonkung 6 200816117 ^ 號OUT2也接到下一個移位暫存器，第三移位暫存器， 當作第三移位暫存器的起始觸發信號，使其根據接收到 的時脈信號產生一第三輸出脈衝信號OUT3送到下一級 的移位暫存器。換言之，驅動電路中每一級移位暫存器 接收來自前一級移位暫存器的輸出脈衝信號當作其起始 脈衝信號，接著再根據接收到的時脈信號產生一個對應 的輸出脈衝信號到對應的閘極信號線，並將產生的輸出 脈衝信號送到次一級的移位暫存器。因此，每個移位暫 • 存器將依序產生輸出脈衝信號，使得對應的閘極信號線 可以依序地被啟動。 第1圖顯示一習知的移位暫存器的電路示意圖。如 圖所示，移位暫存器20A以及20B分別具有一個輸入端 IN、一個輸出端OUT以及兩個時脈信號端CK、XCK， 並且時脈信號端CK與XCK分別接到兩個相位差180度 的時脈信號。當前一級(N-1)移位暫存器20A輸出端的輸 出信號OUT1為高電壓準位時，PMOS電晶體21因為接 ® 收到移位暫存器20A中一反相器31A的輸出低電壓準位 而被導通，使得電容器23開始充電，NMOS電晶體22 的閘極的電壓準位因此往上提升，此時，NMOS電晶體 22的閘極接收PMOS電晶體21導通時移位暫存器20A 的輸出信號高電壓準位，因此NMOS電晶體22亦為導 通。當XCK為高電壓準位時，第N級移位暫存器20B 的輸出信號為高電壓準位，此時NMOS電晶體22的閘極 的電壓準位因為電容器23會再向上提升（bootstrap)。此 0773-A31994TWF;P2005127 ;jasonkung 7 200816117 外’由於NMOS電晶體24的閘極與nm〇s電 閘極_ ’因此NMOS電晶體24亦為導通。I C ? 電壓準位時，NMOS電晶體26 二 ， 2〇A中反相器31A的輪出高電壓$接收到私位暫存器 ^體28與29也接著被導通，電容器23開始放電到0j 個低電壓準位，此時第N級移位暫存器綱的輪出」An τκ panel in an image display system, such as a tft-LCD panel, typically includes a display element, and the display element has a two-dimensional array of pixels having a plurality of elements. These elements can be controlled by a plurality of data lines and a plurality of gate signal lines. A drive circuit consisting of a plurality of serial shift registers (SR) is used to provide corresponding drive signals so that the gate signal lines can be sequentially activated. In general, each shift register (SR) includes an input, an output, a power supply, and a plurality of clock signals. The output of the shift register is connected to the gate signal line of the LCD array, and each interpole signal line is connected to a column of the pixel. When the first shift register of the drive circuit, the first shift register, receives a start pulse signal, the first shift register is based on the received clock signal. Produce an output pulse signal 〇UTl 纠楚一玉』乐一闸极信号线. The output pulse signal OUT1 is also connected to the next shift shift, and the second shift register is regarded as the start signal of the second shift register. The shift-displacer then generates an output pulse signal OUT2 to the second gate signal line according to the inverse clock signal. The output pulse is 0773-Α31994TWF; P2005127; jasonkung 6 200816117 ^ OUT2 is also connected to the next shift register, the third shift register, as the start trigger signal of the third shift register, so that It generates a third output pulse signal OUT3 according to the received clock signal and sends it to the shift register of the next stage. In other words, each stage shift register in the drive circuit receives the output pulse signal from the previous stage shift register as its start pulse signal, and then generates a corresponding output pulse signal according to the received clock signal to Corresponding gate signal line, and the generated output pulse signal is sent to the shift register of the next stage. Therefore, each shift register will sequentially generate an output pulse signal so that the corresponding gate signal lines can be sequentially activated. Figure 1 shows a schematic circuit diagram of a conventional shift register. As shown, the shift registers 20A and 20B respectively have an input terminal IN, an output terminal OUT, and two clock signal terminals CK, XCK, and the clock signal terminals CK and XCK are respectively connected to two phase differences. 180 degree clock signal. When the output signal OUT1 of the output of the current stage (N-1) shift register 20A is at the high voltage level, the PMOS transistor 21 receives the output low voltage of an inverter 31A in the shift register 20A because of the connection. When the level is turned on, the capacitor 23 starts to be charged, and the voltage level of the gate of the NMOS transistor 22 is thus raised upward. At this time, the gate of the NMOS transistor 22 receives the PMOS transistor 21 when it is turned on. The output signal of 20A is at a high voltage level, so the NMOS transistor 22 is also turned on. When XCK is at a high voltage level, the output signal of the Nth stage shift register 20B is at a high voltage level, and at this time, the voltage level of the gate of the NMOS transistor 22 is boosted upward by the capacitor 23 (bootstrap). . This 0773-A31994TWF; P2005127; jasonkung 7 200816117 outer NMOS transistor 24 is also turned on due to the gate of NMOS transistor 24 and the nm 〇s gate _ '. When the IC is at the voltage level, the high voltage $ of the inverter 31A of the NMOS transistor 26, 2〇A is received, and the latches 28 and 29 are also turned on, and the capacitor 23 starts to discharge to 0j. Low voltage level, at this time, the Nth shift register is rounded out"
為低電壓準位。因此，移位暫存器遞的輸出^ 出一個起始脈衝信號到次一級的移位暫存器中。鵠輸 然而，當NMOS電晶體22導通且XCK為高 準位時，NMOS電晶體22的閘極的電壓因為電容器 充屯的關係’會被-直向上提升。假設高電壓準俊 V、DD，NMOS電晶體22與PMOS電晶體21的臨界電壓 =別為Vtn與Vtp時，當NM〇s電晶體22的閘極的電 壓準位超過(VDD+Vtp)，使得應該被關閉的pM〇s電^ 體21可能會被導通而造成了漏電流。為了避免PM〇s電 晶體21意外被導通，因此NM〇s電晶體22的閘極的電 壓準位必須限制不可超過(VDD+Vtp)。假設NMOS電晶 體22的臨界電壓vtn又大於PMOS電晶體21的臨界電 壓Vtp時，則XCK的高電壓準位可能沒辦法全部通過 NMOS電晶體22傳送出去。 此外，由於NMOS電晶體22的閘極耦接至NM〇s 電晶體28的汲極，當NMOS電晶體22導通且XCK為高 電壓準位時，倘若因為製程變異的關係造成NM〇S電晶 體28的臨界電壓vtn變小，即使NMOS電晶體28的閉 0773-A31994TWF;P2005127;jasonkung 8 200816117 . 極與源極間的電位差Vgs為0且NMOS電晶體28為關 閉，NMOS電晶體22的閘極的電壓準位也會因為NMOS 電晶體28的漏電流而降低。如此可能使通過NMOS電晶 體22的信號的電壓準位也到影響而失真。此時，在其中 一級的移位暫存器動作完成後，NMOS電晶體28的閘極 的電壓準位，因為漏電流的關係，可能變成不確定狀態。 同樣地，若NMOS電晶體27的臨界電壓Vtn也變小， 也會導致一些漏電流使NMOS電晶體28的閘極電壓準位 • 更加降低。當NMOS電晶體28的閘極電壓降低至一低電 壓準位時，NMOS電晶體22的閘極就可能產生電壓準位 不明確的浮接節點（floating node)，如第1圖中的節點 F1-F3,使得NMOS電晶體22的閘極容易與XCK耦合而 造成耦合雜訊。這些電壓準位不確定的浮接節點可能造 成NMOS電晶體22的閘極電壓信號失真，無法維持一段 時間的足夠電壓準位，使得輸出信號可能沒辦法提供給 下一級移位暫存器使用。 【發明内容】 有鑑於此，本發明之目的之一即在於提供一種影像 顯示系統中信號的驅動電路及其顯示方法，可以解決上 述的漏電流與浮接節點的問題。 . 基於上述目的，本發明提供一種影像顯示系統，影 像顯示系統包括一種信號驅動電路。其中，信號驅動電 路包括複數串接之移位暫存器，其係由一第一時脈信號 0773-A31994TWF;P2005127;jasonkung 9 200816117 與-第二時脈信號所控制’用以根據一 依序產生對應的驅動信號。每—移=暫1 =-第-時脈輸入端、一輸入端、一 2::ΓΓ輸入端用以接收第一與第二時脈信號 '、 者，輸入端接收一第一脈衝訊號，輸出端用以 ί二；：出信號，驅動端根據接收之時脈信號產生-驅 U用以驅動次-級之移位暫存器。其_，輸It is a low voltage level. Therefore, the output of the shift register outputs a start pulse signal to the shift register of the next stage. However, when the NMOS transistor 22 is turned on and XCK is at the high level, the voltage of the gate of the NMOS transistor 22 is lifted straight up by the relationship of the capacitor charging. Assuming that the high voltage quasi-junction V, DD, the threshold voltage of the NMOS transistor 22 and the PMOS transistor 21 are other than Vtn and Vtp, when the voltage level of the gate of the NM〇s transistor 22 exceeds (VDD+Vtp), The pM〇s body 21, which should be turned off, may be turned on to cause leakage current. In order to prevent the PM〇s transistor 21 from being accidentally turned on, the voltage level of the gate of the NM〇s transistor 22 must be limited to not exceed (VDD + Vtp). Assuming that the threshold voltage vtn of the NMOS transistor 22 is again greater than the threshold voltage Vtp of the PMOS transistor 21, the high voltage level of XCK may not be completely transmitted through the NMOS transistor 22. In addition, since the gate of the NMOS transistor 22 is coupled to the drain of the NM〇s transistor 28, when the NMOS transistor 22 is turned on and the XCK is at a high voltage level, the NM〇S transistor is caused by the process variation. The threshold voltage vtn of 28 becomes smaller even if the NMOS transistor 28 is closed 0773-A31994TWF; P2005127; jasonkung 8 200816117. The potential difference Vgs between the pole and the source is 0 and the NMOS transistor 28 is turned off, and the gate of the NMOS transistor 22 is turned off. The voltage level is also lowered by the leakage current of the NMOS transistor 28. This makes it possible to distort the voltage level of the signal passing through the NMOS transistor 22 as well. At this time, after the shift register operation of one of the stages is completed, the voltage level of the gate of the NMOS transistor 28 may become an indeterminate state due to the relationship of the leak current. Similarly, if the threshold voltage Vtn of the NMOS transistor 27 is also small, some leakage current will cause the gate voltage level of the NMOS transistor 28 to be further lowered. When the gate voltage of the NMOS transistor 28 is lowered to a low voltage level, the gate of the NMOS transistor 22 may generate a floating node whose voltage level is not clear, such as the node F1 in FIG. -F3 causes the gate of the NMOS transistor 22 to be easily coupled to the XCK to cause coupling noise. These floating nodes with uncertain voltage levels may cause the gate voltage signal distortion of the NMOS transistor 22 to maintain a sufficient voltage level for a period of time, so that the output signal may not be available to the next stage shift register. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a driving circuit for a signal in an image display system and a display method thereof, which can solve the above problems of leakage current and floating node. Based on the above objects, the present invention provides an image display system including a signal driving circuit. Wherein, the signal driving circuit comprises a plurality of serially connected shift registers, which are controlled by a first clock signal 0773-A31994TWF; P2005127; jasonkung 9 200816117 and - second clock signal are used according to a sequence A corresponding drive signal is generated. Each shift = temporary 1 = - first - clock input, one input, a 2:: input is used to receive the first and second clock signals ', and the input receives a first pulse signal, The output terminal is used for ί2;: the signal is output, and the driver terminal generates a drive-discharge according to the received clock signal to drive the sub-stage shift register. Its _, lose
舁驅動，號係於不同時段產生之兩信號。其中，當該J 位暫存器為第一級移位暫存器時，第一脈：：起 始脈衝訊號。 玎矶现馬起 本發明也提供-翻動顯示元件的方法。盆中 ㈣驅動電路，信號驅動電路包括複數串、 !一:，以及-第-脈衝訊號給-目標移二ί 益中目標移位暫存㈣上述複 號為十時脈信號或-第二二號 m :夕位暫存讀據提供之該時脈信號以及該第 生輸出㈣。其次，該目標移位暫存 =的㈣準位拉高至大於一既定電屢準 严…t ’虽第一節點的電壓準位被拉高至大於既定電 :守，目標移位暫存器輸出-驅動信號。最後，根 ，此驅動信號’驅動目標移位暫存器之次—級移位暫存 :八中冑幻^與驅動信號係於不同時段產生之兩 1吕说。 〇773.A31994TWF;P2005127；jasonkung 10 200816117 . 為使本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉出較佳實施例，並配合所附圖式， 作詳細說明如下。 【實施方式】 第2圖為根據本發明之一實施例的信號驅動電路示 意圖。信號驅動電路200中包括了三個串接之移位暫存 器··第一移位暫存器SR1、第二移位暫存器SR2以及第 * 三移位暫存器SR3。第一移位暫存器SR1與第三移位暫 存器SR3接到一個第一時脈信號CLK1，第二移位暫存器 SR2則接到一個第二時脈信號CLK2。其中，第一時脈信 號CLK1與第二時脈信號CLK2為具有一相位差之兩時脈 信號，且其輸出信號的週期具有一特定週期比（duty cycle)。每個移位暫存器分別具有一時脈輸入端CLK、一 輸入端IN、一輸出端OUT以及一驅動端NEXT，如第3 圖所示。第3圖為第2圖中的其中一級移位暫存器300 的示意圖。時脈輸入端CLK用以接收一個時脈信號 CLKx，輸入端IN接收一起始脈衝訊號，輸出端OUT產 生一輸出信號OUTx，驅動端NEXT則根據接收之時脈信 號CLKx產生一驅動信號NEXTx。值得注意的是，實施 例的信號驅動電路中移位暫存器個數為三，只是為了方 便說明，實際上移位暫存器個數可以依照應用的需求而 0773-A31994TWF;P2005127;jasonkung 11 200816117 做馮整’並不受限於此。假設信號驅 位暫存器《 π移位暫存器表示，偶數 ㈣产移位暫存器表示的話，N,h … 端將_第-時脈信號⑽，(:：=輪入 ::輸入端將耦接至第二時脈信號⑽並=: 暫存器之《動端係輕接至(喻 N:位 Φ 用―移位暫存器之起始脈衝訊號"’ 舉例來說’請參考第2圖，奇數級移 移位暫存器SR1的時脈輪 。。弟一 η士喊认山 > 〆、弟—移位暫存器SR3的 Γ ⑽接到第—時脈信號cLK1，偶數級移位暫存 …移位暫存器SR2的時脈輸入端則_到 信號⑽。第-移位暫存器SR1的輸入端_ 一㈣始 脈衝“號STV，其驅動端輕接 ° 輸入端。第二移位暫存哭H 存器SR2的 暫存為SR2的驅動端轉接到第三移位 p禮3的輸入端。其中，第—移位暫存器s 號驅動電路雇裡的第—級移位暫存器，因此其次一級 移位暫存益為下一串接级繁-兹： 甲獲、及弟—移位暫存器如。地， ^二移位暫存器如的次一級移位暫存器為下-串接級 弟二移位暫存斋SR3。因此，第—移位暫存器§幻的驅 動端的輸出信細XT1將㈣：移位暫存器聊的輸入 端所接收，第二移位暫存器SR2的驅動端的輸出信號 0773-A31994TWF;P2005127；jasonkung 12 200816117 NEXT2將由第三移位暫存器SR3的輸入端IN所接收。 換言之，除了第一級之外，每一級移位暫存器將由前一 級的移位暫存器的驅動端產生的輸出信號NEXTx來啟 動，並非經由其輸出端的輸出信號OUTx來啟動。 第4圖為根據本發明實施例之其中一級移位暫存器 SR的電路圖。移位暫存器SR包括了六個開關元件：第 一開關元件T1〜第六開關元件T6、兩個反相器：第一反 相器XI與第二反相器X2、一傳輸閘X3以及一邏輯元件 X4。第一開關元件T1的第一端耦接至一第一電源信號 VDD，第二端耦接至一第一節點N4，其控制端則耦接至 移位暫存器SR之輸入端IN。第二開關元件T2的第一端 耦接至移位暫存器SR之輸出端OUT，第二端耦接至一 第二節點N5，其控制端耦接至第一節點N4。第三開關 元件T3的第一端耦接至第二節點N5，第二端耦接至一 第三節點N1，其控制端耦接至移位暫存器SR之輸出端 OUT。第四開關元件T4的第一端耦接至移位暫存器SR 之時脈輸入端CLK，第二端與第六開關元件T6的第一端 耦接至移位暫存器SR之驅動端NEXT，控制端耦接至第 三節點N1。第五開關元件T5的第一端耦接至第三節點 N1，第二端耦接至邏輯元件X4的第二輸入端與移位暫 存器SR的驅動端NEXT，控制端與第六開關元件T6的 0773-A31994TWF;P2005127;j asonkung 13 200816117 — 控制端耦接至一第四節點N3。第六開關元件T6的第二 端耦接至一第二電源信號VSS。邏輯元件Χ4的第一輸入 端耦接至移位暫存器SR之輸入端IN，其輸出端耦接至 第四節點N3。第一反相器XI的輸入端耦接至移位暫存 器SR之輸入端IN，其輸出端耦接至一傳輸閘X3的第二 端。第二反相器X2的輸入端耦接至第一節點N4，其輸 出端耦接至第三開關元件之控制端與移位暫存器SR之 瞻 輸出端OUT。傳輸閘X3的第一端耦接至移位暫存器SR 之輸入端IN，其輸入端耦接至移位暫存器SR之時脈輸 入端CLK，其輸出端搞接至第一節點N4與第一開關元件 T1的第二端。其中，傳輸閘X3可用兩個不同導電型態 之開關元件組成，用以決定節點N4的電壓準位。 當移位暫存器SR之輸入端IN為低電壓準位時，傳 輸閘X3的第一端與第二端的開關元件皆關閉，即傳輸閘 _ X3為關閉狀態，因此輸入端的時脈信號CLKx不會傳到 節點N4,而第一電晶體T1因接收到移位暫存器SR之輸 入端IN的低電壓準位被導通，因此節點N4的電位等於 高電壓準位VDD。當移位暫存器SR之輸入端IN為高電 壓準位時，第一電晶體T1因接收到移位暫存器SR之輸 入端IN的高電壓準位被關閉，而傳輸閘X3的第一端與 第二端的開關元件被導通，即傳輸閘X3為導通狀態，因 0773-A31994TWF;P2005127;jasonkung 14 200816117 此輸入端的時脈信號CLKx傳到節點则 位等於時脈信號CLKx的電壓準位。 U N4的電 於此實::】中’所有開關元件皆採用金氣半_) 电日日體，尤其弟一開關元件T2以及 用不同導電型態的金氧半電晶體。其中,：件Τ 3採 也可採用薄膜電晶體_。舉例來說 開^件 ::了電晶體，第，元件， 日日體。此外，邏輯元件為N〇R閘，第一 電壓準位信號VDD，第二電 〜5旎為一高 vss主〜 --源域為-低電壓準位信號 VSS。為間化說明，以下將以第一電晶體τι表示第一門 關兀件T卜其控制端即為閑極，第一端與第二端則可: 是源極或汲極，其他開關元件的表示以此類推。 外為了更清楚說明第2圖與第4圖的電路運作，請參 考第5圖。第5圖為根據第2圖與第4圖所示電路之一 時序圖。以下以第-移位暫存器SR1的電路運作來做說 明’其他級移位暫存器的運作可以此類推。對第—移位 暫存益SR1而言’由於其為信號驅動電路中的第一 級移位暫存器，因此起始脈衝信號STV會送到第一移位 暫存器SR1的輸入端IN當作脈衝信號，並且第—移位暫 存器SR1的時脈端CLK輕接到第一時脈信號clki，其 對應的輸出信號與驅動信號分別為圖中的〇υτΐ與 0773-Α31994TWF；P2〇〇5127；jasonkung 15 200816117 _ ΝΕΧΤ1。 在時間tl時，當起始脈衝信號STV開始送出，時 脈信號CLK1為低電壓準位，起始脈衝信號STV為高電 壓準位，傳輸閘X3因高電壓準位的起始脈衝信號STV 而導通，第一電晶體T1則為關閉，因此第一移位暫存器 SR1透過第二反相器X2輸出高電壓準位的輸出信號 OUT1。於是，第一移位暫存器SR1裡的第二電晶體T2 • 因接收低電壓準位的時脈信號CLK1被導通，第三電晶 體T3因.接收高電壓準位的輸出信號OUT1被導通，此時 NOR閘X4因接收高電壓準位的起始脈衝信號STV而輸 出低電壓準位，使得節點N3為低電壓準位，節點N1的 電位則因第二電晶體T2與第三電晶體T3導通時傳送過 來的高電壓準位的輸出信號OUT1拉高到接近 (VDD-Vtn)，如圖示的A點準位。第五電晶體T5與第六 • 電晶體T6因節點N3的低電壓準位而關閉，第四電晶體 T4則因節點N1的高電壓準位而導通，使得時脈信號 CLK1的低電壓準位輸出到輸出端NEXT，因此驅動信號 NEXT1為低電壓準位。 在時間t2時，時脈信號CLK1變為高電壓準位，輸 入端IN所接收到的起始脈衝信號STV為低電壓準位， 使得第一電晶體T1被導通，傳輸閘X3被關閉，輸出端 0773-A31994TWF;P2005127;j asonkung 16 200816117 .OUT的輸出信號OUT1透過第二反相器X2變為低電壓 準位，節點N4也因通過第一電晶體T1的電源信號VDD 變為高電壓準位。因此，第二電晶體T2與第三電晶體 T3被關閉。第四電晶體T4因節點N1的高電壓準位而維 持導通，其源/汲極與閘極之間形成電容耦合，使得節點 N1的電壓變成一個較高的電壓準位Vb，如圖示的B點 準位。一般而言，此較高的電壓準位Vb會大於 ⑩ （VDD+Vtn)，因此，高電位準位的CLK1可完全通過第四 電晶體T4傳送到驅動端NEXT ’使得驅動端NEXT的驅 動信號NEXT1為高電壓準位。 在時間t3時，CLK1回到低電壓準位，輸出端OUT 的輸出信號OUT1與輸入端IN所接收到的起始脈衝信號 STV都是低電壓準位，使得傳輪閘X3、第二電晶體T2 與第三電晶體T3都被關閉，第一電晶體T1為導通。驅 • 動信號NEXT1因CLK1變為低電壓準位，NOR閘X4因 接收低電壓準位的STV與驅動端NEXT的低電壓準位驅 動信號NEXT1而輸出一個高電壓準位，因此節點N3回 到高電壓準位。同時，第五電晶體T5與第六電晶體T6 因節點N3為高電壓準位而被導通，使得節點N1透過第 五電晶體T5與第六電晶體T6而放電到一個低電壓準 位。於是，驅動端NEXT輸出此驅動信號NEXT1到下一 0773-A31994TWF;P2005127;jasonkung 17 200816117 ， 級移位暫存器的輸入端當作脈衝信號。同樣地，下一級 的移位暫存器也會如同上述過程一般，將其電路中的對 應節點ΝΓ拉高至一既定電壓準位，並根據時脈信號 CLK2輸出一個驅動信號NEXT2。 由第5圖可知，當時脈信號CLK1位於低電壓準位 時，在時間tl時，第一移位暫存器SR1產生輸出信號 OUT1。接著，當時脈信號CLK1變為高電壓準位後，在 _ 時間t2時，才產生驅動信號NEXT1。因此，輸出信號 OUT1與驅動信號NEXT1為不同時段產生之兩信號，並 且驅動信號NEXT1產生於輸出信號OUT1之後。 於此實施例中，加上了一個第三電晶體T3位在第二 電晶體T2與第四電晶體T4之間。如第5圖所示，在時 間t2時，因為節點N5維持原來的高電壓準位，而第三 電晶體T3的閘極的電壓保持在一個低電壓準位，使得第 • 三電晶體T3的閘極與源極間的電位差Vgs為很大的負電 壓，因此第三電晶體T3可被完全關閉，節點N1也可以 耦合到一個較高電壓準位Vb，使得電位保持在第1圖中 的B點準位，而不受第二電晶體T2的限制。 另外，如果因為製程變異的關係，使得臨界電壓Vtn 變小，導致第三電晶體T3與第五電晶體T5產生漏電流， 節點N1的電位就可能沒辦法維持在Vb的電壓準位。因 0773-A31994TWF;P2005127;jasonkung 18 200816117 . 此，第五電晶體T5與第三電晶體T3的源極分別耦接到 驅動端NEXT與節點Ν5。在時間t2時，節點Ν3為低電 壓準位，而驅動端NEXT為高電壓準位。此時，第五電 晶體T5的閘極接收NOR閘X4的輸出低電壓準位，第五 電晶體T5的源極接收驅動端的輸出高電壓準位，使得第 五電晶體T5的閘極與源極間的電位差Vgs等於一個負電 壓準位-VDD，因此第五電晶體T5可被完全關閉，使得 瞻 漏電流減小許多。此外，輸出端OUT回到低電壓準位且 節點N4為高電壓準位，第二電晶體T2因而被關閉，因 此節點N5可維持在一個高電壓準位。因此，第三電晶體 T3的閘極接收輸出端的輸出低電壓準位，第三電晶體T3 的源極與節點N5因第二電晶體T2關閉而保持在高電壓 準位，使得第三電晶體T3的閘極與源極間的電位差Vgs 也是負電壓，使得漏電流也減小許多。 • 舉例來說，如果VDD為10V，則節點N1的電位可 能被提升到17V，第三電晶體T3的閘極與源極間的電位 差Vgs可能為-9〜-10V，因此第三電晶體T3可被完全關 閉，節點N1的電位不會因漏電流而降低。相較於習知的 移位暫存器電路，本發明的移位暫存器電路即使在製程 變異的情況下，造成電晶體的閘極與源極間的電位差Vgs 降到0V，也可以保持輸出驅動信號的完整，不會因漏電 0773-Α31994TWF;P2005127;j asonkung 19 200816117 . 流的影響而失真，因此在製程上有較佳的容忍度。 再者，即使移位暫存器於不運作時，因為NOR閘 X4在節點N3上輸出一個高電壓準位，第五電晶體T5與 第六電晶體T6被導通，節點N1的電位透過第五電晶體 T5與第六電晶體T6而為低電壓準位，因此，直到移位 暫存器SR下一次運作前，節點N1都可以維持一個低電 壓準位，節點N1不可能是一個浮接節點。同樣地，節點 _ N4則因通過第一電晶體T1的電源信號VDD為高電壓準 位。因此，可避免耦接到時脈信號CLK所造成的耦合雜 訊。 第6圖為根據本發明之另一實施例的移位暫存器電 路圖。第6圖的移位暫存器SR包括了六個開關元件：第 一開關元件T1〜第六開關元件T6、兩個反相器：第一反 相器XI與第二反相器X2、一傳輸閘X3以及一邏輯元件 • X4。第一開關元件T1的第一端耦接至一第一電源信號 VSS，第二端耦接至一移位暫存器SR之輸出端OUT，其 控制端則耦接至移位暫存器SR之輸入端IN。第二開關 元件T2的第一端耦接至第一節點N4，第二端耦接至一 第二節點N5，其控制端耦接至移位暫存器SR之輸出端 OUT。第三開關元件T3的第一端耦接至第二節點N5， 第二端耦接至一第三節點N1，其控制端耦接至第一節點 0773-A31994TWF;P2005127;jasonkung 20 200816117 .N4。第四開關元件T4的第一端耦接至移位暫存器SR之 時脈輸入端CLK，第二端與第六開關元件T6的第一端耦 接至移位暫存器SR之驅動端NEXT，其控制端耦接至第 三節點N1。第五開關元件T5的第一端耦接至第三節點 N1，第二端耦接至邏輯元件X4的第二輸入端與移位暫 存器SR的驅動端NEXT，其控制端與第六開關元件T6 的控制端耦接至一第四節點N3。第六開關元件T6的第 _ 二端耦接至一第二電源信號VDD。邏輯元件X4的第一 輸入端耦接至移位暫存器SR之輸入端IN，其輸出端耦 接至第四節點N3。第一反相器XI的輸入端耦接至移位 暫存器SR之輸入端IN，其輸出端耦接至一傳輸閘X3的 第二端。第二反相器X2的輸入端耦接至移位暫存器SR 之輸出端OUT，其輸出端耦接至第三開關元件之控制端 與第一節點N4。傳輸閘X3的第一端耦接至移位暫存器 • SR之輸入端IN，傳輸閘X3的輸入端耦接至移位暫存器 SR之時脈輸入端CLK，其輸出端耦接至移位暫存器SR 之輸出端OUT與第一開關元件T1的第二端。其中，傳 輸閘X3之功用類似第4圖的傳輸閘，可用兩個不同導電 型態之開關元件組成，用以決定移位暫存器SR之輸出端 OUT的電壓準位。 第6圖類似於第4圖，最大的差別在於第二開關元 0773-A31994TWF;P2005127;jasonkung 21 200816117舁 Drive, the two signals generated in different time periods. Wherein, when the J-bit register is the first-stage shift register, the first pulse:: the start pulse signal. The present invention also provides a method of flipping a display element. In the basin (four) drive circuit, the signal drive circuit includes a plurality of strings, a:, and - the first - pulse signal to - the target shifts two in the target shift temporary storage (four) the above number is the ten-clock signal or - the second two No. m: the clock signal provided by the data storage and the first output (4). Secondly, the target shift temporary storage = (four) level is pulled up to be greater than a predetermined power. The voltage level of the first node is pulled higher than the established power: the target shift register Output-drive signal. Finally, the root, the drive signal 'drives the target shift register's sub-stage shift temporary storage: the eight middle 胄 ^ ^ and the drive signal are generated in different time periods. The above and other objects, features, and advantages of the present invention will become more apparent and understood from the <RTIgt; </RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; as follows. [Embodiment] Fig. 2 is a diagram showing a signal driving circuit according to an embodiment of the present invention. The signal driving circuit 200 includes three serially shifted shift registers, a first shift register SR1, a second shift register SR2, and a third shift register SR3. The first shift register SR1 and the third shift register SR3 are connected to a first clock signal CLK1, and the second shift register SR2 is coupled to a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are two clock signals having a phase difference, and the period of the output signal has a specific duty cycle. Each shift register has a clock input terminal CLK, an input terminal IN, an output terminal OUT, and a driving terminal NEXT, as shown in FIG. Fig. 3 is a schematic diagram of the first stage shift register 300 in Fig. 2. The clock input terminal CLK is used to receive a clock signal CLKx, the input terminal IN receives a start pulse signal, the output terminal OUT generates an output signal OUTx, and the drive terminal NEXT generates a drive signal NEXTx according to the received clock signal CLKx. It should be noted that the number of shift registers in the signal driving circuit of the embodiment is three, just for convenience of description, in fact, the number of shift registers can be 0773-A31994TWF according to the application requirements; P2005127; jasonkung 11 200816117 Doing Feng is not limited to this. Assume that the signal drive register "π shift register indicates that the even (four) production shift register is represented, N, h ... will be _ first - clock signal (10), (:: = round:: input The terminal will be coupled to the second clock signal (10) and =: the "moving end of the register is lightly connected (Y: N: bit Φ with the start pulse signal of the "shift register" "for example" Please refer to Fig. 2, the odd-number shift shift register SR1 clock wheel. The younger brothers yells the mountain> 〆, brother-shift register SR3 Γ (10) receives the first-clock signal cLK1, even-stage shift temporary storage... The clock input terminal of the shift register SR2 is _ to the signal (10). The input terminal of the first-shift register SR1 _ one (four) start pulse "No. STV, its driving end is light Connected to the input terminal. The second shift temporarily stores the temporary storage of the cryo-reservoir SR2 as the drive end of the SR2 is transferred to the input of the third shift p3. Among them, the first shift register s-number drive The circuit-employed first-stage shift register, so the next-level shift temporary storage benefits for the next series of cascades - A: A, the brother - shift register such as: ground, ^ two shift Temporary shifter The lower-serial-level two-stage shift is temporarily stored in the SR3. Therefore, the output signal of the first shift register singular drive XT1 will be (4): the input of the shift register is received, the first The output signal of the drive end of the second shift register SR2 is 0773-A31994TWF; P2005127; jasonkung 12 200816117 NEXT2 will be received by the input IN of the third shift register SR3. In other words, in addition to the first stage, each stage shift The bit register will be activated by the output signal NEXTx generated by the drive terminal of the shift register of the previous stage, not by the output signal OUTx of its output terminal. FIG. 4 is a first shift of the first embodiment of the present invention. The circuit diagram of the register SR. The shift register SR includes six switching elements: a first switching element T1 to a sixth switching element T6, and two inverters: a first inverter XI and a second inverter X2 The first switching terminal T1 is coupled to a first power signal VDD, the second terminal is coupled to a first node N4, and the control terminal is coupled to the shifting terminal. The input terminal IN of the bit register SR. The second switching element T2 The terminal is coupled to the output terminal OUT of the shift register SR, the second end is coupled to a second node N5, and the control end is coupled to the first node N4. The first end of the third switching element T3 is coupled to The second node N5 is coupled to the third node N1, and the control end is coupled to the output terminal OUT of the shift register SR. The first end of the fourth switching element T4 is coupled to the shift register. The clock terminal CLK of the device SR is coupled to the first terminal of the sixth switching device T6 to the driving terminal NEXT of the shift register SR, and the control terminal is coupled to the third node N1. The first end of the fifth switching element T5 is coupled to the third node N1, and the second end is coupled to the second input end of the logic element X4 and the driving end NEXT of the shift register SR, the control end and the sixth switching element T6, 0773-A31994TWF; P2005127; j asonkung 13 200816117 - The control terminal is coupled to a fourth node N3. The second end of the sixth switching element T6 is coupled to a second power signal VSS. The first input terminal of the logic device Χ4 is coupled to the input terminal IN of the shift register SR, and the output terminal thereof is coupled to the fourth node N3. The input end of the first inverter XI is coupled to the input terminal IN of the shift register SR, and the output end thereof is coupled to the second end of a transfer gate X3. The input end of the second inverter X2 is coupled to the first node N4, and the output end thereof is coupled to the control terminal of the third switching element and the output terminal OUT of the shift register SR. The first end of the transmission gate X3 is coupled to the input terminal IN of the shift register SR, the input end of which is coupled to the clock input terminal CLK of the shift register SR, and the output end thereof is connected to the first node N4. And a second end of the first switching element T1. The transmission gate X3 can be composed of two switching elements of different conductivity types for determining the voltage level of the node N4. When the input terminal IN of the shift register SR is at a low voltage level, the switching elements of the first end and the second end of the transfer gate X3 are all turned off, that is, the transfer gate_X3 is turned off, so the clock signal CLKx of the input terminal is The node N4 is not turned on, and the first transistor T1 is turned on by receiving the low voltage level of the input terminal IN of the shift register SR, so the potential of the node N4 is equal to the high voltage level VDD. When the input terminal IN of the shift register SR is at a high voltage level, the first transistor T1 is turned off by receiving the high voltage level of the input terminal IN of the shift register SR, and the first gate of the transmission gate X3 is turned off. The switching element of one end and the second end is turned on, that is, the transmission gate X3 is turned on, because 0773-A31994TWF; P2005127; jasonkung 14 200816117 The clock signal CLKx of this input is transmitted to the node, and the bit is equal to the voltage level of the clock signal CLKx. . The power of U N4 is as follows::] All the switching elements are made of gold gas half _) electric Japanese body, especially the second switching element T2 and the gold-oxygen semi-transistor with different conductivity types. Among them, the film 电 3 can also be used. For example, the opening of the piece :: the transistor, the first, the component, the sun and the body. In addition, the logic element is N〇R gate, the first voltage level signal VDD, the second voltage ~5旎 is a high vss main ~ - source field is - low voltage level signal VSS. For the description of the interval, the first gate member T will be denoted by the first transistor τι, and the control terminal thereof will be the idle pole, and the first terminal and the second terminal may be: the source or the drain, other switching components. And so on. In order to more clearly illustrate the operation of the circuits in Figures 2 and 4, please refer to Figure 5. Fig. 5 is a timing chart of one of the circuits shown in Figs. 2 and 4. The following is explained by the circuit operation of the first shift register SR1. The operation of the other stage shift register can be deduced. For the first shift temporary storage SR1 'because it is the first stage shift register in the signal driving circuit, the start pulse signal STV is sent to the input terminal IN of the first shift register SR1 As a pulse signal, the clock terminal CLK of the first shift register SR1 is lightly connected to the first clock signal clki, and the corresponding output signal and the driving signal are respectively 〇υτΐ and 0773-Α31994TWF in the figure; P2 〇〇5127; jasonkung 15 200816117 _ ΝΕΧΤ1. At time t1, when the start pulse signal STV starts to be sent, the clock signal CLK1 is at a low voltage level, the start pulse signal STV is at a high voltage level, and the transfer gate X3 is due to a high voltage level start pulse signal STV. When the first transistor T1 is turned off, the first shift register SR1 outputs the output signal OUT1 of the high voltage level through the second inverter X2. Then, the second transistor T2 in the first shift register SR1 is turned on by the clock signal CLK1 receiving the low voltage level, and the third transistor T3 is turned on because the output signal OUT1 receiving the high voltage level is turned on. At this time, the NOR gate X4 outputs a low voltage level due to receiving the initial pulse signal STV of the high voltage level, so that the node N3 is at a low voltage level, and the potential of the node N1 is due to the second transistor T2 and the third transistor. The output signal OUT1 of the high voltage level transmitted when T3 is turned on is pulled up to near (VDD-Vtn), as shown in point A of the point. The fifth transistor T5 and the sixth transistor T6 are turned off due to the low voltage level of the node N3, and the fourth transistor T4 is turned on due to the high voltage level of the node N1, so that the low voltage level of the clock signal CLK1 is turned on. Output to the output terminal NEXT, so the drive signal NEXT1 is at a low voltage level. At time t2, the clock signal CLK1 becomes a high voltage level, and the start pulse signal STV received by the input terminal IN is at a low voltage level, so that the first transistor T1 is turned on, the transfer gate X3 is turned off, and the output is turned off. Terminal 0773-A31994TWF; P2005127; j asonkung 16 200816117. The output signal OUT1 of OUT becomes a low voltage level through the second inverter X2, and the node N4 also becomes a high voltage level due to the power supply signal VDD passing through the first transistor T1. Bit. Therefore, the second transistor T2 and the third transistor T3 are turned off. The fourth transistor T4 maintains conduction due to the high voltage level of the node N1, and a capacitive coupling is formed between the source/drain and the gate, so that the voltage of the node N1 becomes a higher voltage level Vb, as shown in the figure. Point B. In general, the higher voltage level Vb will be greater than 10 (VDD+Vtn). Therefore, the CLK1 of the high potential level can be completely transmitted to the driving terminal NEXT through the fourth transistor T4 to make the driving signal of the driving terminal NEXT. NEXT1 is a high voltage level. At time t3, CLK1 returns to the low voltage level, and the output signal OUT1 of the output terminal OUT and the start pulse signal STV received by the input terminal IN are both at a low voltage level, so that the transfer gate X3 and the second transistor are Both T2 and the third transistor T3 are turned off, and the first transistor T1 is turned on. Drive signal NEXT1 becomes low voltage level due to CLK1, NOT gate X4 outputs a high voltage level due to receiving the low voltage level STV and the driver terminal NEXT low voltage level drive signal NEXT1, so node N3 returns High voltage level. At the same time, the fifth transistor T5 and the sixth transistor T6 are turned on because the node N3 is at a high voltage level, so that the node N1 is discharged to a low voltage level through the fifth transistor T5 and the sixth transistor T6. Thus, the driver terminal NEXT outputs the drive signal NEXT1 to the next 0773-A31994TWF; P2005127; jasonkung 17 200816117, the input of the stage shift register acts as a pulse signal. Similarly, the shift register of the next stage will also pull the corresponding node in its circuit to a predetermined voltage level as in the above process, and output a drive signal NEXT2 according to the clock signal CLK2. As can be seen from Fig. 5, when the pulse signal CLK1 is at the low voltage level, the first shift register SR1 generates the output signal OUT1 at time t1. Then, after the pulse signal CLK1 becomes the high voltage level, the drive signal NEXT1 is generated at the time _ time t2. Therefore, the output signal OUT1 and the drive signal NEXT1 are two signals generated in different periods, and the drive signal NEXT1 is generated after the output signal OUT1. In this embodiment, a third transistor T3 is added between the second transistor T2 and the fourth transistor T4. As shown in FIG. 5, at time t2, since the node N5 maintains the original high voltage level, and the voltage of the gate of the third transistor T3 is maintained at a low voltage level, the third transistor T3 is The potential difference Vgs between the gate and the source is a large negative voltage, so that the third transistor T3 can be completely turned off, and the node N1 can also be coupled to a higher voltage level Vb, so that the potential remains in FIG. Point B is not limited by the second transistor T2. In addition, if the threshold voltage Vtn becomes smaller due to the variation of the process, the leakage current is generated by the third transistor T3 and the fifth transistor T5, and the potential of the node N1 may not be maintained at the voltage level of Vb. The source of the fifth transistor T5 and the third transistor T3 are coupled to the driving terminal NEXT and the node Ν5, respectively, according to 0773-A31994TWF; P2005127; jasonkung 18 200816117. At time t2, node Ν3 is at a low voltage level and drive terminal NEXT is at a high voltage level. At this time, the gate of the fifth transistor T5 receives the output low voltage level of the NOR gate X4, and the source of the fifth transistor T5 receives the output high voltage level of the driving terminal, so that the gate and the source of the fifth transistor T5 The potential difference Vgs between the poles is equal to a negative voltage level - VDD, so that the fifth transistor T5 can be completely turned off, so that the leakage current is much reduced. In addition, the output terminal OUT returns to the low voltage level and the node N4 is at the high voltage level, and the second transistor T2 is thus turned off, so the node N5 can be maintained at a high voltage level. Therefore, the gate of the third transistor T3 receives the output low voltage level of the output terminal, and the source of the third transistor T3 and the node N5 are maintained at a high voltage level due to the second transistor T2 being turned off, so that the third transistor The potential difference Vgs between the gate and the source of T3 is also a negative voltage, so that the leakage current is also much reduced. • For example, if VDD is 10V, the potential of node N1 may be raised to 17V, and the potential difference Vgs between the gate and source of the third transistor T3 may be -9~-10V, so the third transistor T3 Can be completely turned off, the potential of node N1 will not be reduced due to leakage current. Compared with the conventional shift register circuit, the shift register circuit of the present invention can maintain the potential difference Vgs between the gate and the source of the transistor down to 0V even in the case of process variation. The integrity of the output drive signal will not be distorted by the leakage of the 0773-Α31994TWF; P2005127; j asonkung 19 200816117 . Therefore, there is better tolerance in the process. Moreover, even if the shift register is not in operation, since the NOR gate X4 outputs a high voltage level on the node N3, the fifth transistor T5 and the sixth transistor T6 are turned on, and the potential of the node N1 passes through the fifth. The transistor T5 and the sixth transistor T6 are at a low voltage level. Therefore, the node N1 can maintain a low voltage level until the next operation of the shift register SR, and the node N1 cannot be a floating node. . Similarly, node_N4 is at a high voltage level due to the power supply signal VDD passing through the first transistor T1. Therefore, coupling noise caused by the clock signal CLK can be avoided. Figure 6 is a circuit diagram of a shift register in accordance with another embodiment of the present invention. The shift register SR of FIG. 6 includes six switching elements: a first switching element T1 to a sixth switching element T6, and two inverters: a first inverter XI and a second inverter X2. Transfer gate X3 and a logic component • X4. The first end of the first switching element T1 is coupled to a first power signal VSS, the second end is coupled to the output terminal OUT of a shift register SR, and the control end is coupled to the shift register SR. Input IN. The first end of the second switching element T2 is coupled to the first node N4, the second end is coupled to a second node N5, and the control end is coupled to the output terminal OUT of the shift register SR. The first end of the third switching element T3 is coupled to the second node N5, the second end is coupled to a third node N1, and the control end is coupled to the first node 0773-A31994TWF; P2005127; jasonkung 20 200816117 .N4. The first end of the fourth switching element T4 is coupled to the clock input terminal CLK of the shift register SR, and the second end is coupled to the first end of the sixth switching element T6 to the driving end of the shift register SR NEXT, whose control end is coupled to the third node N1. The first end of the fifth switching element T5 is coupled to the third node N1, and the second end is coupled to the second input end of the logic element X4 and the driving end NEXT of the shift register SR, and the control end and the sixth switch The control end of the component T6 is coupled to a fourth node N3. The second terminal of the sixth switching element T6 is coupled to a second power signal VDD. The first input terminal of the logic component X4 is coupled to the input terminal IN of the shift register SR, and the output terminal thereof is coupled to the fourth node N3. The input end of the first inverter XI is coupled to the input terminal IN of the shift register SR, and the output end thereof is coupled to the second end of a transfer gate X3. The input end of the second inverter X2 is coupled to the output terminal OUT of the shift register SR, and the output end thereof is coupled to the control end of the third switching element and the first node N4. The first end of the transfer gate X3 is coupled to the input terminal IN of the shift register. The input end of the transfer gate X3 is coupled to the clock input terminal CLK of the shift register SR, and the output end thereof is coupled to The output terminal OUT of the shift register SR and the second end of the first switching element T1. Among them, the function of the transmission gate X3 is similar to that of the transmission diagram of FIG. 4, and can be composed of two switching elements of different conductivity types for determining the voltage level of the output terminal OUT of the shift register SR. Figure 6 is similar to Figure 4, the biggest difference is the second switch element 0773-A31994TWF; P2005127; jasonkung 21 200816117
件T2為NM〇s電晶體、第三開關元件Τ3為電晶 體、邏輯元件X4為NAND閘，第_電源信號為—低電 塵準位^ #b VSS ’第二電源信號為—高電壓準位信號 VM，其他開關元件則採用與第4圖的實施例相反導電 型態的MOS電晶體。輸入的信號與第4圖的實施例正好 相反，但是輸出信號OUT1〜〇UT3仍是相同。換言之， 第6圖所不電路恰為第4圖所示電路之等效電路，其運 :可由熟悉此技藝人士參考前述第4圖之說明得知:、細 即不在此f述。第7圖為根據第2圖與第6圖所示電路 之一時序圖。第7圖中的節點N1的電位初始在一個高電 壓準位。在時間U時，節點犯的電位被下拉到臨界電 壓Vtp，如圖示的D點進4- n± nn 町·、、，占旱位。在時間t2時，因第四電晶 體T4的源極與閘極之間形成電容輕合，使得節點N1的 電屢降到-個較低的電壓準位Vb，，如圖示的〇點準位。 因此’可於第三電晶體T3與第三電晶體τ5的閘極與源 極間提供-個正電麈準位電位差來防止漏電流。第7圖 之工作原理也與第5圖之工作原理大致相同，可參考上 述第5圖之說明，細節不在此贅述。 在本實施例中，影像顯示系統可包括顯示 ^ ^ ^ ΟΠΠ. ^ Ο ^ 或電子I置900。第8圖顯示妒媸士政叫 — / 口頌不根據本發明之一實施例之影 像顯不糸統。如第8圖所+瓶一 n 0 口所不顯不面板800包括上述第2 圖之"^號驅動電路2〇〇、一 Jm ms - - /»l 〇 i 個顯不7C件8 10以及時序控制 〇773-A31994TWF;P2005127;jasonkung 22 200816117 态820。顯示面板800中的顯示元件820，例如LCD元 件，係耦接至信號驅動電路2〇〇。信號驅動電路2〇〇依序 輸出複數個驅動脈衝信號以驅動顯示元件81〇。時序控制 為820用以產生上述的時脈信號以及起始脈衝信號給信 唬驅動電路200。其中，顯示元件81〇也包括了電漿顯示 元件、有機發光二極體（OLED)顯示元件以及冷陰極管顯 示元件。The T2 is an NM〇s transistor, the third switching element Τ3 is a transistor, the logic element X4 is a NAND gate, and the _th power signal is a low electric dust level ^b VSS 'the second power signal is a high voltage standard The bit signal VM, other switching elements, uses a MOS transistor of the opposite conductivity type as the embodiment of Fig. 4. The input signal is exactly the opposite of the embodiment of Figure 4, but the output signals OUT1~〇UT3 are still the same. In other words, the circuit shown in Fig. 6 is exactly the equivalent circuit of the circuit shown in Fig. 4, which can be referred to by those skilled in the art with reference to the description of Fig. 4 above, and is not described herein. Fig. 7 is a timing chart of the circuit shown in Figs. 2 and 6. The potential of the node N1 in Fig. 7 is initially at a high voltage level. At time U, the potential of the node is pulled down to the critical voltage Vtp, as shown in point D, 4-n± nn, and the dry position. At time t2, due to the formation of a capacitive junction between the source and the gate of the fourth transistor T4, the power of the node N1 is repeatedly dropped to a lower voltage level Vb, as shown in the figure. Bit. Therefore, a positive electric potential difference can be provided between the gate and the source of the third transistor T3 and the third transistor τ5 to prevent leakage current. The working principle of Fig. 7 is also substantially the same as that of Fig. 5. Refer to the description of Fig. 5 above, and the details are not described here. In this embodiment, the image display system may include displaying ^ ^ ^ ΟΠΠ. ^ Ο ^ or electronically setting 900. Figure 8 shows the image of a gentleman who is not according to an embodiment of the present invention. As shown in Fig. 8, the bottle-n0 port does not show that the panel 800 includes the above-mentioned second figure "^ number drive circuit 2〇〇, a Jm ms - - /»l 〇i display 7C pieces 8 10 And timing control 〇 773-A31994TWF; P2005127; jasonkung 22 200816117 state 820. A display element 820, such as an LCD element, in display panel 800 is coupled to signal drive circuit 2A. The signal driving circuit 2 sequentially outputs a plurality of driving pulse signals to drive the display elements 81A. Timing control 820 is used to generate the above-mentioned clock signal and the start pulse signal to the signal driving circuit 200. Among them, the display element 81A also includes a plasma display element, an organic light emitting diode (OLED) display element, and a cold cathode tube display element.
第9圖顯不根據本發明之另一實施例之影像顯示系 統900,顯示面板800可以是電子裝置之一部分（例如： 電子裝置9H))，一般電子裝置91〇包括顯示面板_和 -直流/直流轉換器920，甚者，直流/直流轉換器92〇耦 接至顯示面板800以提供電能至顯示面板8〇〇，電子裝置 可以是：手機、數位相機、個人數位助理、筆記型電腦、 桌上型電腦、電視、或可攜式DVD放影機。 此外’本發明也提供—種驅動顯示元件的方法。其 中’顯示元件包括一信號驅動電路，信號驅動電路包括 複數串接之私位暫存态。驅動顯示元件的方法包括：首 先’提供—時脈錢以及—第—脈衝訊號給-目標移位 暫存器’其巾目標移位暫存㈣上述複 其中-者，時脈信號為-第-時脈信號或一第二時脈: L ’目標移位暫存器根據提供之該時脈信號以及 ^一脈衝訊號’產生一輪出信號。其次，言亥目標移位 存盗m點的電|準位拉高至大於-既定電壓 〇773-A31994TWF;P2005127;jason]amg 200816117 準位。接著m點的電_位被拉高至大於既定 電壓準位時，目標移位暫存器輸出—驅動信號。最後， 根據此驅動信號，驅動目標移位暫存器之次—級移位暫 存器。其中，輸出信號與驅動信號為不同時段產生之兩 信號。 上述說明提供數種不同實施例或助本發明之不同 特性的實施例。實例中的料元件以及方法係用以幫助 闡釋本發明之主要精神及目的，當然本發明不限於此。 因此，雖然本發明已以較佳實施例揭露如上，然其 亚非用以限定本發明，任何所屬技術領域中具有通常知 識者，在不麟本發明之精神和範圍内，#可做些許更 ，與潤飾’因此本發明之保護範圍當視後附之中請專利 範圍所界定者為準。 【圖式簡單說明】 ，1圖顯示一f知的移位暫存器的電路示意圖。 第2圖顯示根據本發明之一實施例的信號驅動電路 示意圖。 第3圖顯示第2圖中的其中—級移位暫存器的示意 圖。 第4圖顯錄據本發明實_之其巾—級移位暫存 裔的電路圖。 第5圖顯不根據第2圖與第4圖所示電路之一時序 0773-A31994TWF;P2005127;jasonkung 24 200816117 ^ 圖。 第6圖顯示根據本發明之另一實施例的移位暫存器 電路圖。 第7圖顯示根據第2圖與第6圖所示電路之一時序 圖。 第8圖顯示根據本發明之一實施例之影像顯示系 第9圖顯示根據本發明之另一實施例之影像顯示系 • 統。 【主要元件符號說明】 SR〜移位暫存器； OUTx〜輸出脈衝信號； 20A、20B〜移位暫存器；21〜PMOS電晶體； 31A〜反相器； IN〜輸入端； OUT〜輸出端； CK、XCK〜時脈信號端；； 22、24、27、28、29〜NMOS 電晶體； 23〜電容器； Vtn、Vtp〜臨界電壓； VDD、VSS〜電壓準位；Figure 9 shows an image display system 900 according to another embodiment of the present invention. The display panel 800 may be part of an electronic device (e.g., electronic device 9H). The general electronic device 91 includes a display panel _ and - DC / The DC converter 920, in other words, the DC/DC converter 92 is coupled to the display panel 800 to provide power to the display panel 8. The electronic device can be: a mobile phone, a digital camera, a personal digital assistant, a notebook computer, a table. A laptop, TV, or portable DVD player. Further, the present invention also provides a method of driving a display element. The 'display element' includes a signal driving circuit, and the signal driving circuit includes a plurality of private bit buffers. The method for driving the display component includes: firstly providing - clock money and - first - pulse signal to - target shift register - its towel target shift temporary storage (four) of the above -, the clock signal is - - The clock signal or a second clock: L 'the target shift register generates a round out signal according to the clock signal and the pulse signal provided. Secondly, the target shift of the target is stored at the m point of the thief. The level is raised to be greater than - the established voltage 〇 773-A31994TWF; P2005127; jason] amg 200816117. The target shift register output-drive signal is then asserted when the electrical_bit at point m is pulled high above a predetermined voltage level. Finally, based on the drive signal, the sub-stage shift register of the target shift register is driven. Wherein, the output signal and the driving signal are two signals generated in different time periods. The above description provides several different embodiments or embodiments that facilitate different features of the invention. The material elements and methods in the examples are used to help explain the main spirit and purpose of the invention, although the invention is not limited thereto. Therefore, although the present invention has been disclosed in the above preferred embodiments, the invention is not intended to limit the invention, and any one of ordinary skill in the art may, within the spirit and scope of the invention, , and retouching 'Therefore, the scope of protection of the present invention is subject to the definition of patent scope. [Simple description of the diagram], 1 shows a schematic circuit diagram of a shift register. Fig. 2 is a view showing a signal driving circuit according to an embodiment of the present invention. Figure 3 shows a schematic diagram of the in-stage shift register in Figure 2. Fig. 4 is a circuit diagram showing the state of the towel-level shifting temporary storage according to the present invention. Figure 5 shows the timing of one of the circuits shown in Figures 2 and 4 0773-A31994TWF; P2005127; jasonkung 24 200816117 ^ Figure. Fig. 6 is a circuit diagram showing a shift register in accordance with another embodiment of the present invention. Figure 7 shows a timing diagram of the circuit shown in Figures 2 and 6. Fig. 8 shows an image display system according to an embodiment of the present invention. Fig. 9 shows an image display system according to another embodiment of the present invention. [Main component symbol description] SR~Shift register; OUTx~ output pulse signal; 20A, 20B~shift register; 21~PMOS transistor; 31A~inverter; IN~ input; OUT~ output CK, XCK~clock signal terminal; 22, 24, 27, 28, 29~ NMOS transistor; 23~ capacitor; Vtn, Vtp~ threshold voltage; VDD, VSS~ voltage level;
Vgs〜閘極與源極間的電位差； 200〜信號驅動電路； SRI、SR2、SR3〜移位暫存器； CLIU、CLK2、CLKx〜時脈信號； CLK〜時脈輸入端； IN〜輸入端； OUT〜輸出端； NEXT〜驅動端； 0773-A31994TWF;P2005127;jasonkung 25 200816117 • OUTx〜輸出信號； NEXTx〜驅動信號；Vgs ~ potential difference between the gate and the source; 200 ~ signal drive circuit; SRI, SR2, SR3 ~ shift register; CLIU, CLK2, CLKx ~ clock signal; CLK ~ clock input; IN ~ input ; OUT ~ output; NEXT ~ drive; 0773-A31994TWF; P2005127; jasonkung 25 200816117 • OUTx ~ output signal; NEXTx ~ drive signal;
Nth、(N+l)th〜移位暫存器； T1-T6〜開關元件； XI、X2〜反相器； X3〜傳輸閘； X4〜邏輯元件； N1-N5〜節點； STV〜起始脈衝信號； tl、t2〜時間； Vb、Vb’〜電壓準位； 800〜顯示面板； 810〜顯示元件； 820〜時序控制器； 900〜影像顯示系統； _ 910〜電子裝置； 920〜直流/直流轉換器 0773-A31994TWF;P2005127;jasonkung 26Nth, (N+l)th~shift register; T1-T6~switching element; XI, X2~inverter; X3~transmission gate; X4~ logic element; N1-N5~ node; STV~start Pulse signal; tl, t2~ time; Vb, Vb'~ voltage level; 800~ display panel; 810~ display element; 820~ timing controller; 900~ image display system; _ 910~ electronic device; 920~DC/ DC converter 0773-A31994TWF; P2005127; jasonkung 26