200814326 九、發明說明： 【發明所屬之技術領域】 本=係關於—種薄膜電晶體液晶顯示面板及其製造 一士 、種可p牛低儲存電容之佈局面積以提高開口率 同日可可降低薄膜電晶體臨界電壓’並減輕寄生電容及衍 不良衫響之液晶面板及其製造方法。 【先前技術】 • -LC二弟十圖所不，揭示有一薄膜電晶體液晶顯示器(TFT 的。等效電路圖，主要係令—掃猫驅動器（⑺、資 次=動為（71)輸出端分別連接複數的掃描 二=广：），該掃描線（72。）及資料、線（71。）係作 膜電晶體ΤΠ·，各薄膜電晶體TFT的、及：：广有-涛 存命六r Ώ 的汲極上分別連接一儲 該二電=一由薄膜電晶體TFT控制 •料心 液晶電“-充放電’當面板要顯示資 二二Γ1^72)即送出電壓訊號料打開掃描線 /上的母一薄膜電晶體TFT，而資料驅動器 貝,达出每個晝素電極所f要的灰階電壓 (:非晶樓電晶體T…型通道元件，其= th)大約在卜2V，要打開該薄膜電晶冑tf )充电毛、流’須在閉極施加10~20v的正電壓 版電晶體TFT並使其維持最小 流， 二， 加約5〜1C)V的負電壓。 彳要在閘極上施 如前揭所述，薄膜電晶體TFT決定儲存電容Cst與液 200814326 j電容一的充放電，當-晝素上的薄膜電晶體TFT導通 時：該《即寫入該晝素，而薄膜電晶體丁叮關閉時，則 二谷維持舄入該晝素的訊號，使該晝素維持原來的 减不狀恶’並等待下-次驅動。而在此技術領域中，提高 的電容值是經常被討論的主題，但先前技術卜 電容的電容值，即必須加大儲存電容在晝素内的 师局面％ ’如此一來將寻彡塑 ”晝素的開口率，進而影響其亮 :，：透過加大儲存電容佈局面積方式以提高電容值之作 ' 不衫響開口率的前提下是顯然不可行的。 報公…8彻6號「薄膜電晶體液晶顯 二:,储存爸容及其製造方法」發明專利案，其宣稱揭露 =加储存電容之儲存電荷卻不影響晝素開口率之方 ;〇〇 2佳貫施例係如其第1A~1C圖所示，係先在-基板 ^◦0表面以_第一 安 1π〇 ，木化至屬層施作薄膜電晶體1 1 0的閘 m，又W形成—覆蓋基板100及其上間極102的絕緣層 ^緣層104上形成橫跨Μ極1〇2的通道層106 /汲極1。=圖，屬層製作薄膜電晶體”。的源 及儲存電谷的下電極1 1 2。 下電=成2:膜電晶體11°的源麟108及儲存電容的 卜即在基板1〇〇上形成-介電層114，並去 層’使下電極112上方的介電層厚度較薄而 極Γι介心極間介電層，令該電極間介電層厚度小於除電 -導^ ^外的介面層厚度；接著在介電層114上形成 ’ θ ’該導體層部分經由預先製作的開口 122與薄膜 200814326 笔日日體1 1 0的 >及極連接，部八丨、士 上電極118。 W義為健存電容12。的 相較於傳統技術，前述專利案所稱的介面層實 傳統液晶面板上的保護層（passivation τ… 、丄、士 y } 表面上，前 …案令介電層位於儲存電容上/下電極間的電極間介 電層厚度低於以外的介面層厚度，令儲存電容的 _ 得以^高，實際上卻有實施困難或根本無法實施的問題㈣ • 前述專利之第一實施例係一 bottom Gate Type，其中 ，儲存電容係由第二圖案化金屬^ (下電極）、介電層（ 實際上A passivation laye「）及一導體層（應為透^極 )所構成，其中導體層係透過開口 122與薄膜電晶體二〇 的汲極連接，至於下電極如何與該汲極、Vc〇m信號連接 則未具體揭示，再者，由第二圖案化金屬層所形U成的 common line必須與資料線（data |jne)平行如此一來 common iine為了達到與外部訊號溝通之目的，勢必2項 • 透過該導體層（丨丁〇）將comm〇n line與第—圖案化金屬層 搞接，從而造成common line走線過長、以導體層〇丁〇曰) 耦接之阻抗過高而導致嚴重的延遲（RC de|ay)問題，由此 可見，丽述專利案在設計與製程上的存在明顯的困難與複 雜度，從而衍生製程與製造原物料成本提高。 ^ 【發明内容】 由上述可知，現有技術雖對提高儲存電容，但不使開 率變小提出相應的技術方案，然而該等技術在實現上明 200814326 顯《礙難行，故待謀求具體可行的解決方案。 示面板，=要目的在提供一種薄膜電晶體液晶顯 、低寄生電容^高儲存電容且開口率大、低臨界電塵 * 了生电谷、低RC延遲外，且在製程上具體 不虞大幅提高製程與原料成本。 且 為達成前述目的採取的主要技術手段係令 之一面上包括有： 敬肖基板 弟一金屬層，係形成於玻璃基板之一面上， 薄膜電：體之閑極、儲存電容下電極及掃描線等，。括 屬層絕緣層，係形成於玻璃基板上，並位於第-金 膜電:體：’係位於前述第-絕緣層上且對應於前述薄 一 汲極摻雜區，係位於前述主動區的兩側； 第一金屬層，係位於前述泝士 緣層上層，包括有薄膜電晶體=:Γ雜區及第-絕 户干 ％日日之/原極電極、汲極電極、儲 辱笔容上電極及資料線等； -保護層’係位於前述第二金屬層之上層， 有一開口； 乂 一畫素電極，係於前述保謹声卜廿 血广“ 層上亚透過其上的開口 、/寻膜電晶體的 >及極電極電連接；其中： 該第一絕緣層於對應前述 、健存電容下.電極及掃描線/ 極搞離層、源/汲極隔離層、 閘極、源極電極、汲極電極 資料線交叉處分別定義出閘 儲存電容介電層及線隔離層 200814326 等；其中，儲存電容介電層之戸择 層之&度小於源/¾:極隔離屏、 線隔離層’惟與晝素電極τ方的第—絕緣層厚度相同/ 二前述的液晶顯示面板構造’因儲存電容之介電層尸 度較薄，因此可有效縮小儲存電容 予 、 雨仔包谷的佈局面積，提高開口 率。且由於源/汲極隔離層依麸相 队…'不目對較厚，故可減少 效應。 前述第-絕緣層之閑極隔離層厚度小於源Ά極隔離 層、線隔離層’由於閘極隔離層亦較薄1而薄膜 將有較低的臨界電μ ’而可使用低壓之駆動元件，、二 省成本之效益。 Ρ 此外’晝素電極下方之第一絕緣層厚度較薄，因此可 有效提高光穿透率，達到較高之光利用率。 本發明次-目的在提供一種薄膜電晶體液晶顯示面板 的製造方法，其包括下列步驟： 準備一玻璃基板； 在玻璃基板之一面上形成經圖案化的第一金屬層，而 分別定義出薄膜電晶體之閘極、儲存電容之下電極及掃描 線等； 在第一金屬層上形成一第一絕緣層，並使第一絕緣層 於對應前述閘極、下電極及掃描線處分別定義出不同層厚 在第一絕緣層上連續沈積一非晶矽（a_S|·)層與一 ν型 摻雜非晶矽（|sj+a-Si)層，經圖案化構成一島狀半導體層； 在月i述基板上形成一全面覆蓋的第二金屬層，經圖案 8 200814326 化分別定義出薄膜電晶體之源極電極、沒極電 容之上電極及資料線等； t $ 利用圖案化後的第二金屬層對前述非 N型摻雜非晶釋+a_Si)層進行餘刻，其^型: 石夕（N+a_s丨)層將斷開而構成源/汲極摻雜區，另進L = 非晶作-s丨)層進行背通道㈣（Bce)以構成主動區/ 在前述第二金屬層上形成一保護層. 在前侧層上形成一晝素電：，並令晝素電極透過 預先形成於層間之開口與汲極電極電連接。 前述第一絕緣層係透過下列步驟定義出不同的層厚： 在基板上形成第一金屬層，並以一光罩宕羞t 掃描線；先罩疋義出閘極與 在前述閉極與掃描線上形成第'絕緣層，並 光罩在對應閘極、湄炻雨煸、n 4 Xh ’、本$極、汲極電極、儲存電容下電極 =4/陶交叉處分別定義出不同層厚的間極隔離 3盆' 及極離層、儲存電容介電層及線隔離層等； 1中，前述•存電容介電層之厚度小於源/沒極隔離 丨、.泉⑽層’惟與畫素電極下方的第一絕緣層厚度相同 :月'J述弟一絕緣層亦可透過下列步驟定義出不同的層厚 在基板上形成第一 、， 極 乐金屬層，亚以一第一光罩定義出 減存電容下泰 I極與掃描線； 在前述基板形备 v成一絕緣薄膜，並以一第二光罩定義t 200814326 一下絕緣層’該下絕緣岸 日叫孤源極电極、汲極電極及掃描 線/負料線父又處； 在前述基板上形成-上絕緣層，其中 將在對應源極電極、汲極. 晶 拉电極及知祂線/資料線交叉處重 $以構成一較厚之層厚區七· ^ ^ 或，而僅為上絕緣層覆蓋的閘極 、儲存电谷下電極處則為較薄之層厚區域。 φ 【實施方式】 關於本發明之一較传奋A加 、， 罕乂仫Μ %例，百先請參閱第一圖所示 ，主要係在-玻璃基板（10)的—面上形成第—金屬層， 邊第-金屬層係經過圖案化而分別定義出薄膜電晶體之閉 極（21)、儲存電容之下電極（川及掃描線（川等. !著形成一第一絕緣層㈠”而覆蓋在第-金屬層上（如 弟二圖所示），該第一絕緣層（11)於對應前述閘極（21 )、下電極（31)及掃描線（41)處分料義出不同層厚 ♦〖如第三圖所示），而不同的層厚可由一道灰階光罩:別 定義出，另亦可透過兩道鍍膜配合一道光 的層厚；本實施例中係採用灰階光罩在第—絕緣層（Μ) 的不同位置定義出不同膜厚。 接著如第四圖所示，係在第一絕緣層（1彳）上連續沈 積一非晶碎（a-Si)層（201)與一 Ν型摻雜非晶矽（ν+二200814326 IX. Description of the invention: [Technical field of invention] This is a type of thin film transistor liquid crystal display panel and its manufacturing area, which can increase the aperture ratio of cocoa and reduce the film power. A liquid crystal panel having a crystal critical voltage' and mitigating parasitic capacitance and poor squeaking, and a method of manufacturing the same. [Prior Art] • -LC second brother ten map does not reveal a thin film transistor liquid crystal display (TFT's equivalent circuit diagram, the main system - sweeping cat driver ((7), capital = moving to (71) output respectively The connection of the complex scan 2 = wide:), the scan line (72.) and the data, the line (71.) is used as a film transistor ,, the thin film transistor TFT, and:: Guang You-Tao Cangming Liu r Ώ The bungee is connected to a second storage = one is controlled by a thin film transistor TFT. • The center of the liquid crystal is charged. - When the panel is to be displayed, the voltage signal is sent to the scan line/on. The mother-film TFT, and the data driver, to reach the gray-scale voltage of each elemental electrode (the amorphous floor transistor T... type channel element, its = th) is about 2V, Turn on the thin film transistor tf) charge the hair, flow 'must apply a 10~20v positive voltage plate transistor TFT at the closed end and keep it to a minimum flow, and add a negative voltage of about 5~1C)V. As described above, the thin film transistor TFT determines the charge of the storage capacitor Cst and the liquid 200814326 j capacitor Discharge, when the thin film transistor TFT on the halogen is turned on: the "writing of the halogen", while the thin film transistor is turned off, the second valley maintains the signal of the halogen, so that the element is maintained The original subtraction does not wait for the next-time drive. In this technical field, the increased capacitance value is a subject that is often discussed, but the capacitance value of the prior art capacitor must increase the storage capacitor in the morpheme. Within the division of the teacher's situation, 'so that it will find the opening ratio of the element, which in turn affects its brightness:: By increasing the storage area of the storage capacitor to increase the capacitance value It is obviously not feasible. Reporting the public...8th No.6 "Thin-film transistor liquid crystal display two: storage dad capacity and its manufacturing method" invention patent case, which claims to expose = storage capacitor storage charge does not affect the aperture ratio of the element; 2 The best example is as shown in Fig. 1A~1C, which is first applied to the surface of the substrate 以0 with _1 安1π〇, and then ligated to the genus layer to act as the gate m of the thin film transistor 1 10 , W is formed—the insulating layer layer 104 covering the substrate 100 and the upper interposer 102 is formed with a channel layer 106/drain 1 across the drain 1〇2. =Fig., the layer is made of thin film transistor. The source and the lower electrode of the storage valley are 1 1 2 . Power down = 2: The source transistor 108 of the film transistor 11 and the storage capacitor are on the substrate 1 Forming a dielectric layer 114 thereon, and removing the layer to make the dielectric layer above the lower electrode 112 thinner than the dielectric layer of the dielectric layer, so that the thickness of the dielectric layer between the electrodes is smaller than the power-conducting Interface layer thickness; then forming a 'θ' on the dielectric layer 114. The conductor layer portion is connected to the film 200814326 pen day body 1 1 0 via the pre-made opening 122, and the upper electrode and the upper electrode 118. W is the storage capacitor 12. Compared with the conventional technology, the above-mentioned patents refer to the interface layer on the traditional liquid crystal panel (passivation τ..., 丄, 士 y } on the surface, the former ... The thickness of the dielectric layer between the electrodes on the upper/lower electrodes of the storage capacitor is lower than the thickness of the interface layer, so that the storage capacitor _ is high, but there are actually problems that are difficult or impossible to implement (4). The first embodiment of the patent is a bottom gate type, wherein The system is composed of a second patterned metal (lower electrode), a dielectric layer (actually A passivation laye ") and a conductor layer (which should be a transparent electrode), wherein the conductor layer is transmitted through the opening 122 and the thin film transistor The second pole connection is not specifically disclosed as to how the lower electrode is connected to the drain and Vc〇m signals. Furthermore, the common line formed by the second patterned metal layer must be connected to the data line (data | Jne) Parallel to this, common iine in order to achieve the purpose of communication with external signals, it is bound to 2 items • Through the conductor layer (Kenting 〇) to connect the comm〇n line with the first - patterned metal layer, resulting in a common line The line is too long, the conductor layer is too high, and the impedance of the coupling is too high, resulting in serious delay (RC de|ay). It can be seen that the design and process of the Lisz patent case is obviously difficult. The complexity, and thus the cost of the derivative process and the manufacturing raw material increase. ^ [Summary of the Invention] As can be seen from the above, the prior art proposes a corresponding technical solution for improving the storage capacitance, but does not make the opening rate small. However, the technologies are implemented. Ming 2 00814326 It is difficult to implement, so it is necessary to seek a concrete and feasible solution. The display panel, = the purpose is to provide a thin film transistor liquid crystal display, low parasitic capacitance ^ high storage capacitance and large aperture ratio, low critical electric dust * electricity generation Valley, low RC delay, and in the process of the specific process does not significantly increase the process and raw material costs. And the main technical means to achieve the above-mentioned purposes, one of the main aspects include: 敬肖, the substrate, a metal layer, formed in the glass On one side of the substrate, the film is electrically: the idle electrode of the body, the lower electrode of the storage capacitor, and the scanning line. The insulating layer is formed on the glass substrate and is located on the first-gold film: the body is located on the first insulating layer and corresponds to the thin-drain-doped region, and is located in the active region. Both sides; the first metal layer is located on the upper layer of the above-mentioned tracer layer, including the thin film transistor =: noisy area and the first - the majority of the household dry / the original electrode, the bungee electrode, the burnt pen The upper electrode and the data line, etc.; - the protective layer is located on the upper layer of the second metal layer, and has an opening; the first pixel electrode is attached to the opening through the upper layer of the layer of the above-mentioned / film-seeking transistor > and electrode electrical connection; wherein: the first insulating layer corresponds to the aforementioned, the storage capacitor. The electrode and the scan line / pole separation layer, source / drain isolation layer, gate, The gate electrode storage capacitor dielectric layer and the line isolation layer 200814326 are respectively defined at the intersections of the source electrode and the drain electrode data line; wherein the selection layer of the storage capacitor dielectric layer is less than the source/3⁄4: pole isolation screen , the line isolation layer 'only with the thickness of the first insulating layer of the halogen electrode τ side / The above-mentioned liquid crystal display panel structure 'Since the dielectric layer of the storage capacitor is thinner, it can effectively reduce the storage capacitance, the layout area of the rain and the valley, and increase the aperture ratio. And since the source/drain isolation layer is bran The team...'s not thicker, so the effect can be reduced. The thickness of the idler isolation layer of the first-insulation layer is smaller than that of the source-drain isolation layer and the line isolation layer' because the gate isolation layer is also thinner and the film will have The lower critical electric μ' can use the low-voltage swaying component, and the cost of the two provinces. Ρ In addition, the thickness of the first insulating layer under the 昼-electrode electrode is thin, so it can effectively improve the light transmittance and achieve higher light. The present invention provides a method for fabricating a thin film transistor liquid crystal display panel comprising the steps of: preparing a glass substrate; forming a patterned first metal layer on one side of the glass substrate, and defining respectively Forming a gate of the thin film transistor, a lower electrode of the storage capacitor, a scan line, and the like; forming a first insulating layer on the first metal layer, and causing the first insulating layer to correspond to the gate, A layer of amorphous germanium (a_S|·) and a layer of doped v-doped amorphous germanium (|sj+a-Si) are successively deposited on the first insulating layer with different layer thicknesses at the lower electrode and the scanning line, respectively. Patterning to form an island-shaped semiconductor layer; forming a second covering of the second metal layer on the substrate, and defining the source electrode of the thin film transistor, the electrode of the electrodeless capacitor and the data line by pattern 8 200814326 Etching; t $ using the patterned second metal layer to etch the aforementioned non-N-doped amorphous release + a_Si) layer, the type: the stone (N+a_s丨) layer will be broken to form a source a /tano doped region, another L = amorphous -s丨 layer carries the back channel (4) (Bce) to form the active region / forms a protective layer on the second metal layer. Forms a layer on the front side layer The halogen electrode: and the halogen electrode is electrically connected to the drain electrode through an opening formed in advance between the layers. The first insulating layer defines different layer thicknesses by the following steps: forming a first metal layer on the substrate, and shaming the scan line with a mask; first covering the gate and the above-mentioned closed-pole and scanning Forming a 'insulation layer on the line, and the reticle defines different layer thicknesses at the corresponding gate, the rain, the n 4 Xh ', the $ pole, the drain electrode, the storage capacitor lower electrode = 4 / the ceramic intersection respectively Inter-electrode isolation 3 pots' and pole separation layer, storage capacitor dielectric layer and line isolation layer; 1 , the thickness of the above-mentioned storage capacitor dielectric layer is less than the source / no-pole isolation 丨, .泉(10) layer 'only and painting The thickness of the first insulating layer under the element electrode is the same: the moon's insulating layer can also define different layer thicknesses on the substrate by forming the first layer, the bliss metal layer, and the first photomask. Defining the capacitor and the scan line under the storage capacitor; forming an insulating film on the substrate, and defining a second mask as a second mask. The insulating layer is called the source electrode. The electrode and the scan line/negative line are again in the parent; forming an upper insulation on the aforementioned substrate a layer in which the corresponding source electrode, the drain electrode, the crystal pull electrode, and the knowing line/data line are overlapped to form a thicker layer thick region VII ^ ^ or only for the upper insulating layer The gate and the lower electrode of the storage valley are thinner thick regions. φ [Embodiment] Regarding one of the present inventions, it is more important to express A plus, and rare. For example, please refer to the first figure, mainly on the -surface of the glass substrate (10). The metal layer, the edge-metal layer is patterned to define the closed electrode (21) of the thin film transistor and the lower electrode of the storage capacitor (Chuan and scanning lines (Chuan et al. form a first insulating layer (1)" And covering the first metal layer (as shown in FIG. 2), the first insulating layer (11) is different in the corresponding materials corresponding to the gate (21), the lower electrode (31) and the scanning line (41). Layer thickness ♦ [as shown in the third figure), and different layer thicknesses can be defined by a gray-scale mask: not defined, but also through two coatings to match the layer thickness of a light; in this embodiment, gray scale is used. The mask defines different film thicknesses at different positions of the first insulating layer (Μ). Next, as shown in the fourth figure, an amorphous (a-Si) layer is continuously deposited on the first insulating layer (1彳). (201) with a Ν-type doped amorphous 矽 (ν+二
Si)層（202)，經圖案化構成一島狀半導體層（如第五圖 所示）；N型摻雜非晶矽（N+ a-Si) 接著在前述基板（10 )上形成„全面覆蓋的第4 10 200814326 屬層’經圖案化分別定義出薄膜電晶體之源極電極（24) 、㈣電極（25)、儲存電容之上電極（32)&資料線（ 42 )等（如第六圖所示）； " 利用圖案化後的第二金屬層對前述非晶矽（a_s丨）層（ 201)與n型摻雜非晶石夕（N+ a_Si)層（2〇2)進行钱刻， 乂 N型摻雜非晶石夕(一)層（2〇2)將斷開而構成源 /沒極摻雜區（23) ’另進—步對非晶外層（2〇1) 進^背通道姓刻（BCE)以構成主動區（22)(如第七圖所 不）。 至此吾人將位於第二金屬層下方的第一絕緣層（11) 分別定義為閘極隔離層（112)、源，汲極隔離層（”” 、儲存電容介電層（113)及線隔離層（114)，而第一絕 緣層（11)在前述以外的部位則定義為隔離層（115)， ^騎示’該閘極隔離層（112)較源7汲極隔離層（川 為缚，該源/汲極隔離層（””較儲存電容介電層（ 113)厚，該儲存電容介電層（113)又較線隔離層 為溥，惟儲存電容介電層（113)貝,m隔離層（115)為 相同厚度’其因不同層厚產生的不同特性容後料。 另如弟八圖所不，該第二金屬層上又形成一保護層（ 2 ) ’於本實施例中，該保護層（12 )為一鈍化層 :aSSIVati〇n —r);該保護層（12)上又形成-由透明 電=叩〇)構成的晝素電極（13,(如第九圖所示），該晝 、° ( 3)並透過一預先形成於層間的開口與薄膜電晶 體的汲極電極（25)電連接。 200814326 由上述說明可瞭解本發明製作 葙，士义π a ”、、貝不面板之主要流 釦由則述可知，本發明係將第一 對卢+ μ # π 巴、、象層在特定元件的相 =疋我成不同㈣厚，藉此可兼顧料電容、開口率、 光牙透率、薄膜電晶體臨界電壓及 的特性功效詳如以下所述： 。…-寺問題’具體 緣層（⑴在儲存電容上，下電極間所定義 同=:谷：電層（113)厚度較薄’如此十可在相 .局面知下具有較高的電容值，由 值被提高，卻未增加佈局面積，因而可相對加大7口之二 又因位於薄膜電晶體閘極（21)與源，汲極電極（24 η、、（ 25)之間的源/汲極隔離層（111 )相對較厚，故 ::咸少寄生效應β χ閘極隔離層（112)厚度相對於源/ 界電墨叫而 因而缚膜電晶體將有較低的臨 而可使用低壓之驅動元件，具有節省成本之 效益。 _ 另> 因位於晝素電極（1 3 )下方之第一絕緣層（彳彳）厚 季交镜 ，TO " _ 可有效提咼光穿透率，達到較高之光利用率 卜_、十、π Μ 处可知’本發明係透過第一絕緣層在不同位置定 ^出不同的層厚，使儲存電容之介電層厚度較薄，而可有 政綠小儲农+ h 一 兩仔毛各的佈局面積，提高開口率。又因源/汲極 /v.., 曰^ ;、、、'相對較厚，故可減少寄生效應。而對前述第一 絕緣舞 6、' 3疋義出不同層厚的技術，除前述實施例所揭露以灰 階先i + 之以外，亦可利用下列步驟達成： 12 200814326 在土板上形成第一金屬層，並以一第一光罩定義出閑 極、儲存電容下電極與掃描線； 一=述基板形成一絕緣薄膜，並以一第二光罩定義出 下、、’巴緣層’该下絕緣層涵蓋源極電極、汲極電極及掃描 線/資料線交又處； 田又土板上形成一上絕緣層，其巾，上/下絕緣犀 重疊處為一較戽夕s❹ 日a Si) layer (202) patterned to form an island-shaped semiconductor layer (as shown in FIG. 5); an N-type doped amorphous germanium (N+ a-Si) is then formed on the substrate (10) The 4th 10th 200814326 genus layer is patterned to define the source electrode (24), (4) electrode (25), storage capacitor upper electrode (32) & data line (42) of the thin film transistor, etc. (Fig. 6); " using the patterned second metal layer to perform the aforementioned amorphous germanium (a_s) layer (201) and n-type doped amorphous stone (N+ a_Si) layer (2〇2) Money engraved, 乂N-doped amorphous austenite (1) layer (2〇2) will be broken to form a source/depolarized doped region (23) 'Another step-to-amorphous outer layer (2〇1) Entering the back channel name (BCE) to form the active area (22) (as shown in the seventh figure). So far, we have defined the first insulating layer (11) under the second metal layer as the gate isolation layer ( 112), a source, a drain isolation layer ("", a storage capacitor dielectric layer (113), and a line isolation layer (114), and the first insulation layer (11) is defined as an isolation layer (115) outside the foregoing , ^ riding The gate isolation layer (112) is thicker than the source 7 drain isolation layer (the source/drain isolation layer ("" is thicker than the storage capacitor dielectric layer (113), and the storage capacitor dielectric layer (113) The line isolation layer is 溥, but the storage capacitor dielectric layer (113) is shelled, and the m isolation layer (115) is of the same thickness 'the different characteristics of the layer thickness due to different layer thicknesses. A protective layer (2) is formed on the second metal layer. In the embodiment, the protective layer (12) is a passivation layer: aSSIVati〇n-r); the protective layer (12) is formed again-by a transparent electrode (叩〇) consisting of a halogen electrode (13, as shown in FIG. 9), the 昼, ° (3) and passing through a pre-formed opening between the layers and the gate electrode of the thin film transistor (25) Electrical connection. 200814326 It can be understood from the above description that the main flow fastener of the present invention is the same as that of the panel, and the present invention is the first pair of Lu + μ # π巴, and the image layer. In the phase of the specific component = 疋 I become different (four) thick, which can take into account the material capacitance, aperture ratio, optical tooth penetration, thin film transistor threshold voltage and The effect is as follows: ....-Temple problem' specific edge layer ((1) on the storage capacitor, the same as defined between the lower electrodes =: valley: the electrical layer (113) is thinner than the thickness of the body. The lower the capacitance value, the value is increased, but the layout area is not increased, so it can be relatively increased by 7 ports and also because of the thin film transistor gate (21) and the source, the drain electrode (24 η, The source/drain isolation layer (111) between (25) is relatively thick, so:: salty parasitic effect β χ gate isolation layer (112) thickness relative to the source/boundary ink and thus the bonding film transistor There will be lower cost and low voltage drive components for cost savings. _OTHER> Because the first insulating layer (彳彳) is located below the halogen electrode (1 3 ), the TO " _ can effectively improve the light transmittance and achieve a higher light utilization rate. It can be seen from π ' that the present invention sets different layer thicknesses at different positions through the first insulating layer, so that the thickness of the dielectric layer of the storage capacitor is thin, Each layout area increases the aperture ratio. Because the source / bungee / v.., 曰 ^ ; , , , ' relatively thick, it can reduce parasitic effects. For the foregoing first insulating dance 6, the technology of different layer thicknesses can be achieved by using the following steps in addition to the gray scale first i + disclosed in the foregoing embodiment: 12 200814326 Forming on the soil board a metal layer, and a first photomask defines a dummy electrode, a storage capacitor lower electrode and a scan line; a substrate is formed as an insulating film, and a second mask is used to define a lower, 'bar edge layer' The lower insulating layer covers the source electrode, the drain electrode and the scanning line/data line intersection; the upper and lower earth plate form an upper insulating layer, and the towel, the upper/lower insulating rhinoceros overlap is a 戽 ❹ ❹ day
之層厗&域，該較厚之層厚區域係對應 :極笔極、沒極電極及掃描線/資料線交叉處；： :'毒層亚未與下絕緣層重疊者即-較薄之層厚區域，兮α 薄之！：區域係對應於閘極、儲存電容下電極。、較 猎則返方式對第—絕緣層分別定義出不同的層厚 達成降低儲存電容的佈局面積、薄膜電 / 並減少寄生電容及其衍生的負面影響等目的。％， 【圖式簡單說明】 第一至九圖：係本發明之製程示意圖。 第十圖：係已知薄膜電晶體液晶顯示器之等效⑯ (11 )第一絕緣層 (1 3 )晝素電極 【主要元件符號說明 (1 〇)玻璃基板 (1 2 )保護層 儲存電容介電層 隔離層 (1 1 1 )源/沒極隔離層 (1 12 )閘極隔離層 (彳7 3 ) (1 14 )線隔離層 (彳15 ) 13 200814326 (20)非晶矽層 （201 )非晶矽（a-Si)層 (202) N型摻雜非晶矽（N+ a-Si)層 （21 )閘極 (22)主動區 (23)源/汲極摻雜區 (24)源極電極 (25)汲極電極 (31 )下電極 (32 )上電極 (41 )掃描線 (42)資料線 14The layer 厗 & field, the thicker layer thickness region corresponds to: the pole pole, the electrode of the pole and the intersection of the scan line/data line;: : 'The toxic layer is not overlapped with the lower insulation layer - that is thinner The thick layer of the layer, 兮α thin! : The area corresponds to the gate and the storage capacitor lower electrode. Compared with the hunting method, different thicknesses are defined for the first insulating layer to achieve a reduction in the layout area of the storage capacitor, thin film power / and reduce the parasitic capacitance and its negative effects. %, [Simple description of the drawings] First to Nineth drawings: A schematic diagram of the process of the present invention. Figure 10: Equivalent to a known thin film transistor liquid crystal display 16 (11) First insulating layer (1 3 ) Alizarin electrode [Main component symbol description (1 〇) Glass substrate (1 2 ) Protective layer storage capacitor Electrical layer isolation layer (1 1 1 ) source/no-polar isolation layer (1 12) gate isolation layer (彳7 3 ) (1 14 ) line isolation layer (彳15) 13 200814326 (20) amorphous germanium layer (201) Amorphous germanium (a-Si) layer (202) N-type doped amorphous germanium (N+ a-Si) layer (21) gate (22) active region (23) source/drain doped region (24) Source electrode (25) drain electrode (31) lower electrode (32) upper electrode (41) scan line (42) data line 14