TW200814081A - Memory control circuit and method - Google Patents

Memory control circuit and method Download PDF

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Publication number
TW200814081A
TW200814081A TW095132912A TW95132912A TW200814081A TW 200814081 A TW200814081 A TW 200814081A TW 095132912 A TW095132912 A TW 095132912A TW 95132912 A TW95132912 A TW 95132912A TW 200814081 A TW200814081 A TW 200814081A
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data
signal
delay
odd
phase difference
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TW095132912A
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Chinese (zh)
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TWI302318B (en
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Wen-Chang Cheng
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Nanya Technology Corp
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Priority to TW095132912A priority Critical patent/TWI302318B/en
Priority to US11/618,937 priority patent/US7580301B2/en
Priority to DE102007005701.8A priority patent/DE102007005701B4/en
Priority to KR1020070033218A priority patent/KR100832013B1/en
Priority to JP2007102555A priority patent/JP4589356B2/en
Publication of TW200814081A publication Critical patent/TW200814081A/en
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Publication of TWI302318B publication Critical patent/TWI302318B/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)

Abstract

A memory control circuit includes: a phase detection module for detecting a phase difference between a data strobe signal and a clock signal; a control module, coupled to the phase detection module, for generating a set of control signals according to the phase difference, where the set of control signals are corresponding to the phase difference; a latch module for latching write data carried by a data signal according to rising/falling edges of the data strobe signal; an odd/even data separator, coupled to the latch module, for performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and an adjustable delay line module, coupled to the odd/even data separator and the control module, for adjusting the odd/even data's delay according to the control signals, where the delay amount of the odd/even data is corresponding to the control signals.

Description

200814081 九、發明說明： _ 【發明所屬之技術領域】 本發明係有關於隨機存取記憶體（random access memory’RAM)之控制’尤指―觀舰㈣電路與方法。 【先前技術】 I1 現著貝减業的蓬勃發展，半導體元件之相關技術亦日益精 • 進。為I提升隨機存取記憶體（randGm繼ss mem()ry，RAM)於 寫入八貝取貝料的速度’遂出現了雙倍速資料傳輸（d〇uWe她 rate,DDR)技術的應用。應用這種技術之隨機存取記憶體即為所 謂的雙倍速隨機存取記憶體（DDRRam)。 傳統的隨機存取記憶體之資料存取係對應於時脈訊號的複數 個週期中每—週期之—特定邊緣，例如：上升緣（rising edge)。 由於雙倍舰機存取記顏之#料存取鑛應於時脈訊號的複數 籲個週期中每-週期之上升緣與下降緣（觸呢_)，所以若使用 相同頻率之日植訊餅為運作基準，職倍速隨機存取記憶體之 資料存取速度為傳統的隨機存取記憶體之資料存取速度的兩倍。 雙倍速賴存取記憶體係應用了有別於時脈訊號之資料頻閃 ( — strobe)訊號作為存取資料的依據，而上述之資料頻閃訊號 也就是所謂的DQS訊號，其訊號格式係為同業所熟知。如第ι ^ .所示，當一寫入命令㈣皮輸出時，資料頻閃訊號DQS應該於進 7 200814081 ^ 低位準之後丨現複數彳轉期性咖ί;這些週#雅脈衝之上升 •緣/、下IV緣可作為資料訊號Dq所載（。卿）之D〇、〇1、、 D3···等資料被寫入記憶體中的記憶單元（mem〇rycdl)的依據。 另外，資料頻閃訊號DQS中出現在這些週期性脈狀前的這個低 位準的部分係稱為前文（p職We)，如第i圖所示。此外，時脈 Λ遽^CLK於寫人命令徽下達時的上升緣至資料頻閃訊號DQs =别文之後的第—個上升緣之間的時間間距“me」耐⑴係 _ 疋義為Tdqss。 g在某些情況下，例如：當時脈峨VCLK的鮮被提高了、 但，電路系統中有些部份的訊號延遲未被妥善處理時，便無法轉 保貝料頻Ifl^DQS符合特定規格。—旦時關^τ_不符合 ^述之特疋規格所絲的範圍’便無法雜資料訊號dq所載之 資料最終可被正確地寫入記憶單元。 ► 【發明内容】 口此本U之目的之-在於提供—種記憶體控制電路與方 法，以解決上述問題。 本發明之—祕實施射提供—種記，隨控制電路。該記憶體 控制電路包含有：-相位_模組，用來偵測一資料頻閃（她 strobe)訊餘-時脈減之間之她差；—控鑛組，触至該 相位偵測模組，用來依據該相位差來產生一組控制訊號，盆中該 8 200814081 組控制訊號係對應於該相位差；一閂鎖（latch)模組，用來依據 . 該#料_訊號之上升緣/下降緣來_-詩訊號所載（carry) 之寫入資料；-奇偶資料分離器，耗接至朗鎖模組，用來對該 寫入資料進行奇偶資料分雜理，以產生料分雜號，其中 該資料分離訊號載有對應於該寫入資料之奇/偶資料；以及一可 调延遲線（adjustable delay line)模組，耦接至該奇偶資料分離器 以及該控繼組，时依獅組控制峨_魏㈣分離訊號 鲁所載之奇/偶資料的延遲，其中該奇//偶資料之延遲量係對應於 該組控制訊號。 本發明於提供上述之記憶體控制電路之同時，亦對應地提供一 種記憶體控财法。該記紐控制方法包含有：躺—資料頻閃 城與-時脈訊號之間之她差；依據該相位差來產生一組控制 聰’其中触鋪纖俩應驗她差；雜該資料頻閃訊 號之上升緣/下轉來閱_資料魏所載之寫人資料;對該寫 • ^資料進行奇偶資料分離處理，以產生—魏分離訊號，其中該 資料刀離號載有對應於該寫入資料之奇/偶資料；以及依據該 組控制訊絲織該雜分離減所載之奇/偶雜的延遲，其 中該可/偶資料之延遲量係對應於該組控制訊號。 【實施方式】 • 杯考第2圖，第2圖為本發明一較佳實施例所提供之記憶體 控制電路1GG的示意圖，其中記憶體控制電路應包含有一相位 200814081 • 偵測模組110、一控制模組120、-閃鎖〇atch)模组132、一緩 衝模組134、一奇偶資料分離器' 136、一可調延遲線(adjustable她y …line)模組142、一緩衝模組144、以及一劇模組，其中該開關 模組於本實施例中係為XY開關模組146。如第2圖所示，相位偵 測模組11〇包含有兩接收單元112_〗與112_2、一延遲吻合控制器 114、以及一相位偵測器116，其中延遲吻合控制器114包含有至 少一延遲線（delayline);於本實施例中，延遲吻合控制器1Μ包 含有延遲線114-1與114-2，每一延遲線包含有複數個延遲單元(未 顯示）。 相位侧模組110可侧上述之資料頻間（data str〇be)訊號 DQS與上述之時脈訊號VCLK之間之相位差。於第2圖所示之相 '位 =敗组no中，兩接收單元112β1與112_2分別接收時脈訊號 vvXK與資料頻閃訊號DQS，而廷遲吻合控制器m則可控制延 遲線ιΐ4_ι來延遲時脈訊號VCLK，並可控制延遲線114_2來延遲 ⑩ 胃料頻閃訊號DQS ;藉由延遲吻合控制器114之控制，時脈訊號 VCLK與資料頻閃訊號DqS之間的延遲量可被妥善地控制在一特 疋範圍内。如此，延遲吻合控制器114進行延遲吻合控制之後所 輸出之時脈訊號VCLK與資料頻閃訊號DQS可作為相位侧器 U6之偵測依據。於是，相位偵測器116便依據延遲吻合控制器 114所輪出之時脈訊號VCLK與資料頻閃訊號DQS來偵測該相位 差。 200814081 a 卜控制模、、且120依據該相位差來產生-組控制訊號Ctrl， .其中控制訊號㈤係對應於該相位差。依據本實施例’控制模組 120係為-解碼器，並可依據該相位差來進行解碼以產生控制訊號 Ctrl。此外，關模組132可依據資料頻閃訊號吻之上升緣/ 1降緣來_資料訊號Dq所載（c卿）之寫入資料，以供緩衝 模組134進行緩衝處理。於是，奇偶資料分離器136對緩衝處理 後之該寫人·進行奇㈣料分離處理，以產生—資料分離訊號 SRWD ’其中資料分離訊號SRWD載有對應於該寫入資料之奇/ 偶資料。 、 依據本發明’可調延遲線模組142依據控制訊號ari來調整資 料分離訊號SRWD所載之奇/偶資料的延遲，其中該奇/偶資料 之延遲里係對應於控制訊號Ctrl。如前面所述，控制訊號⑶係 對駿卿位差，所以該奇/偶資料之延遲量亦對應於該相位 差。藉由上述之可調延遲控制機制，可調延遲線模組142輸出延 • 遲調整後之資料分離訊號SRWD—adj，其中延遲調整後之資料分離 訊號SRWD一adj係對應於資料分離訊號SRWD，且載有延遲後之 奇/偶資料。於是，延遲調整後之資料分離訊號SRWD—adj被輸 入至緩衝模組144以供緩衝處理。 如第2圖所示，緩衝模組144依據奇偶資料寫入致能（enable) 訊號SRWDWREN對延遲後之奇/偶資料進行緩衝控制；當奇偶 • 資料寫入致能訊號SRWDWREN處於一致能狀態時，緩衝模組144 200814081 . 可將該延遲後之奇/偶資料輸出至XY開關模組146。於是，χγ 開關模組140可依據至少一選擇訊號XY-SW來輪出該延遲後之 可/偶寅料’以供寫入記憶體之記憶早元。上述之奇偶資料寫入 致能訊號SRWDWREN與選擇訊號ΧΥ一SW均為同業所熟知，故 不在此贅述其細節。 依據本實施例，第2圖所示之一部份元件之實施細節係如第3 圖所示。閂鎖模組132包含有複數個閂鎖132_0、132-1、···、與 馨 132-15,分別對應資料訊號Dq之複數個位元dq⑼、DQ⑴、+、 與dq(15)，其中每一閃鎖咖〇 = 〇小…、15)依據資料頻 閃訊號DQS來閂鎖資料訊號DQ之一個位元DQ(i)。閃鎖132_〇、 132-1、···、與丨必丨5所閂鎖之資料訊號dq之位元DQ⑼、 DQ(1)、··.、與DQ(15)分別透過緩衝模組134中對應的緩衝器 134-0、134-i、…、與134_15被輸击至奇偶資料分離器Β6，以進 行奇偶資料分離處理。奇偶資料分離處理後之資料分離訊號 _ SRWD 具有複數個位元 SRWD(〇)、SRWD(l)、..，SRWD(3i)。 如第3圖所示，可調延遲線模組142包含有複數個可調延遲線 142-0、142-1、…、與142-31，分別對應於資料分離訊號SRWd 之複數個位元SRWD(O)、SRWD(l)、…、與SRWD(31)，其中之 每一可調延遲線142J (j = 0、i、···、31)包含有複數個延遲單元 (未顯示）。依據本實施例，每一可調延遲線142_j藉由選擇其複 • 數個延遲單元中對應控制訊號Ctrl之延遲單元的輸出，即可施加 200814081 -(_y)職控觀號Ctrl之延遲量於龍分離減SRWD之- • 恤几SRWD® ’作為延遲調整後之資料分離訊f虎SRWD_adj當 中對應之位元SRWD_adj①。 本發明的好處之-是’本發明可解決習知技術巾、當資料頻閃 Λ號DQS中之時間間距Tdqss不符規格時無法確保資料訊號 所載之資料可被正確地寫入記憶單元之問題。 鲁 #由本發明所提供之相位差债測機制以及對資料分離訊號 SRWD之可調延遲控制’龍_訊號Dqs丨論處於訊號領先之 狀況献!〖懿_肢，本發明之峨健概路與方法可將 貝料分離訊號SRWD對應地調整，使得延遲調整後之資料分離訊 號SRWD_adj所載之奇/偶資料出現的時間區間維持一致；也就 是說，本糾可轉挺遲雜後之資料分離雛娜&坤之 資料分離訊號窗（SRWDwindow)的大小，不受資料頻閃訊號卿 修 係處於訊號領先之狀況或是訊號落後的狀況之影響。因此，延遲 調整後之資料分離訊號SRWD_adj所載之奇/财料可被正常地 透過緩衝模組144與XY開關模組146寫入記憶體中之記憶單元。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 巳 13 200814081 f圖式簡單說明】 第1圖為習知之資料頻閃訊號與資料訊號的示意圖。 第2圖為本發日狀—實酬聰供之記憶酿_路 第3圖為第2圖所示之一部Α Ά W圖 刀兀件之貝施細節的示意圖。 【主要元件符號說明】200814081 IX. Description of the invention: _ Technical field to which the invention pertains The present invention relates to the control of random access memory (RAM), especially to the ship-to-ship (four) circuit and method. [Prior Art] I1 is now booming in the industry, and the related technologies of semiconductor components are becoming more and more sophisticated. For I to improve the random access memory (randGm followed by ss mem () ry, RAM) in the speed of writing eight shells to take the material '遂 遂 appeared double double data transmission (d〇uWe her rate, DDR) technology application. The random access memory using this technology is called double-speed random access memory (DDRRam). The data access system of the conventional random access memory corresponds to a specific edge of each cycle of the clock signal, for example, a rising edge. Since the double-ship access to the material is stored in the complex pulse of the clock signal, the rising edge and the falling edge of each cycle (touch _), so if the same frequency is used The bread is the operational benchmark, and the data access speed of the double-speed random access memory is twice that of the conventional random access memory. The double-speed-on-access memory system uses a strobe signal that is different from the clock signal as the basis for accessing data. The above-mentioned data strobe signal is also called DQS signal, and its signal format is Well known in the industry. As shown in the first ι ^ ., when a write command (four) skin output, the data strobe signal DQS should be after the 7 200814081 ^ low level, the current number of 彳 性 性 ;; The edge / and the lower IV edge can be used as the basis of the memory unit (mem〇rycdl) in which the data such as D〇, 〇1, D3··· are contained in the data signal Dq. In addition, the low-order portion of the data strobe signal DQS that appears before these periodic pulses is called the former (p job We), as shown in Figure i. In addition, the clock Λ遽^CLK is in the rising edge of the write command symbol to the data strobe signal DQs = the time interval between the first rising edge after the text "me" resistance (1) system _ 疋 meaning for Tdqss . g In some cases, for example, when the VCLK of the pulse is increased, but the signal delay of some parts of the circuit system is not properly handled, it cannot be guaranteed that the bee frequency Ifl^DQS meets certain specifications. - Once the time ^τ_ does not meet the scope of the specification of the specification, the data contained in the data signal dq cannot be correctly written into the memory unit. ► [Summary] The purpose of this U is to provide a memory control circuit and method to solve the above problems. The present invention is a secret implementation of the radiation supply type, followed by a control circuit. The memory control circuit comprises: a phase_module for detecting a difference between a data strobe and a clock-reduction; - the ore control group, touching the phase detection mode a group for generating a set of control signals according to the phase difference, wherein the 8 200814081 group control signals correspond to the phase difference; and a latch module is used for the rise of the #料_信号The edge/falling edge comes _-the data written by the poetry signal (carry); the parity data separator is used to connect to the lock module to perform parity data partitioning on the written data to generate the material score. a data, wherein the data separation signal carries odd/even data corresponding to the written data; and an adjustable delay line module coupled to the parity data separator and the control group, At the time of the lion group control 魏 _ Wei (four) separate the delay of the odd/even data contained in the signal ru, wherein the delay amount of the odd//even data corresponds to the group of control signals. The present invention provides a memory control method correspondingly while providing the above memory control circuit. The control method includes: a difference between the lying data strobe city and the clock signal; according to the phase difference, a set of control cocks is generated, wherein the touch paving fiber meets her difference; the data is strobed. The rising edge of the signal/down is to read the data of the writer contained in the data wei; the parity data is separated from the written data to generate the Wei separation signal, wherein the data knife is separated from the number corresponding to the write The odd/even data of the data input; and the odd/even delay of the impurity separation according to the control wire, wherein the delay amount of the identifiable data corresponds to the set of control signals. [Embodiment] FIG. 2 is a schematic diagram of a memory control circuit 1GG according to a preferred embodiment of the present invention. The memory control circuit should include a phase 200814081. a control module 120, a flash lock 模组atch module 132, a buffer module 134, a parity data separator 136, an adjustable delay line (adjustable her y ... line) module 142, a buffer module 144. A drama module, wherein the switch module is an XY switch module 146 in this embodiment. As shown in FIG. 2, the phase detecting module 11 includes two receiving units 112_〗 and 112_2, a delay matching controller 114, and a phase detector 116, wherein the delay matching controller 114 includes at least one delay. In the present embodiment, the delay-matching controller 1A includes delay lines 114-1 and 114-2, each of which includes a plurality of delay units (not shown). The phase side module 110 can side the phase difference between the data track signal DQS and the clock signal VCLK. In the phase 'bit=missing group no shown in FIG. 2, the two receiving units 112β1 and 112_2 respectively receive the clock signal vvXK and the data strobe signal DQS, and the delay matching controller m can control the delay line ιΐ4_ι to delay The clock signal VCLK can control the delay line 114_2 to delay the gastric strobe signal DQS. By delaying the control of the controller 114, the delay between the clock signal VCLK and the data strobe signal DqS can be properly Control is within a special range. In this way, the clock signal VCLK and the data strobe signal DQS outputted by the delay matching controller 114 after the delay matching control can be used as the detection basis of the phase side device U6. Then, the phase detector 116 detects the phase difference according to the clock signal VCLK and the data strobe signal DQS which are rotated by the delay matching controller 114. 200814081 a control mode, and 120 generates a group control signal Ctrl according to the phase difference, wherein the control signal (f) corresponds to the phase difference. According to this embodiment, the control module 120 is a decoder, and can decode according to the phase difference to generate a control signal Ctrl. In addition, the module 132 can be used to buffer the data stored in the data signal Dq according to the rising edge of the data strobe signal/1. Then, the parity data separator 136 performs an odd (four) material separation process on the buffered memory to generate a data separation signal SRWD' wherein the data separation signal SRWD carries odd/even data corresponding to the write data. According to the present invention, the adjustable delay line module 142 adjusts the delay of the odd/even data contained in the data separation signal SRWD according to the control signal ari, wherein the delay of the odd/even data corresponds to the control signal Ctrl. As described above, the control signal (3) is a difference to the Chunqing, so the delay amount of the odd/even data also corresponds to the phase difference. The adjustable delay line module 142 outputs the delay-adjusted data separation signal SRWD_adj, wherein the delay-adjusted data separation signal SRWD-adj corresponds to the data separation signal SRWD. And carries the odd/even data after the delay. Thus, the delayed adjusted data separation signal SRWD_adj is input to the buffer module 144 for buffer processing. As shown in FIG. 2, the buffer module 144 buffers the delayed odd/even data according to the parity write enable signal SRWDWREN; when the parity/data write enable signal SRWDWREN is in the consistent state The buffer module 144 200814081. The delayed odd/even data can be output to the XY switch module 146. Thus, the χ γ switch module 140 can rotate the delayed audible/difficulty ′ according to the at least one selection signal XY-SW for writing to the memory early memory of the memory. The above-mentioned parity data write enable signal SRWDWREN and the selection signal ΧΥ一SW are well known in the industry, so the details are not described here. According to this embodiment, the implementation details of some of the components shown in Fig. 2 are as shown in Fig. 3. The latch module 132 includes a plurality of latches 132_0, 132-1, . . . , and 132-15, respectively corresponding to the plurality of bits dq(9), DQ(1), +, and dq(15) of the data signal Dq, wherein Each flash lock 〇 = 〇 small ..., 15) according to the data strobe signal DQS to latch a bit DQ (i) of the data signal DQ. Flash locks 132_〇, 132-1, ···, and 丨必丨5 are latched by the data signal dq bits DQ(9), DQ(1),··., and DQ(15) respectively through the buffer module The corresponding buffers 134-0, 134-i, ..., and 134_15 in 134 are input to the parity data separator Β6 to perform parity data separation processing. The data separation signal after the parity data separation processing _SRWD has a plurality of bits SRWD(〇), SRWD(l), .., SRWD(3i). As shown in FIG. 3, the adjustable delay line module 142 includes a plurality of adjustable delay lines 142-0, 142-1, ..., and 142-31, which respectively correspond to a plurality of bits SRWD of the data separation signal SRWd. (O), SRWD(l), ..., and SRWD (31), each of which has a plurality of delay units (not shown) including each of the adjustable delay lines 142J (j = 0, i, ..., 31). According to this embodiment, each adjustable delay line 142_j can apply the delay of the 200814081 -(_y) job control view Ctrl by selecting the output of the delay unit corresponding to the control signal Ctrl in the plurality of delay units. The dragon is separated from the SRWD - • The couple of SRWD® 'as the delay adjusted data splits the corresponding bit SRWD_adj1 in the tiger SRWD_adj. The advantage of the present invention is that the present invention can solve the problem that the data contained in the data signal can be correctly written into the memory unit when the time interval Tdqss in the data strobe DQS does not conform to the specification. . Lu #The phase difference debt measurement mechanism provided by the present invention and the adjustable delay control of the data separation signal SRWD 'Dragon_Signal Dqs paradox are in the leading position of the signal! 〖懿_ limb, the invention is based on the road The method can adjust the bedding separation signal SRWD correspondingly, so that the time interval of the odd/even data appearing in the delay-adjusted data separation signal SRWD_adj is consistent; that is, the data can be separated after the correction The size of the data screen of the child's data is not affected by the situation in which the data strobe signal is in the leading position of the signal or the signal is backward. Therefore, the odd/defining material contained in the delayed data separation signal SRWD_adj can be normally written into the memory unit in the memory through the buffer module 144 and the XY switch module 146. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention.巳 13 200814081 f Brief description of the diagram] Figure 1 is a schematic diagram of the conventional data strobe signal and data signal. The second picture is the day-to-day-real-life Cong for the memory of the brewing _ road. Figure 3 is the one shown in Figure 2 Ά 图 图 图 示意图 示意图 示意图 示意图 示意图 示意图 。 。 。 。 。 。 。 [Main component symbol description]

200814081200814081

τ 時脈訊號之週期 WR 寫入命令 DQS 資料頻閃訊號 Tdqss 時間.間距 Ctrl 控制訊號 DQ 貧料訊號 DQ(0)，DQ(1)，···，DQ(15) 資料訊號之複數個位元 D0，D1，D2，D3 寫入資料 SRWD 資料分離訊號 SRWD(0)? SRWD(1)9... ? SRWD(3i) 資料分離訊號之複數個位元 SRWD—adj 延遲調整後之資料分離訊號 SRWD WREN 奇偶貢料寫入致能訊號 XYSW 選擇訊號 15τ clock signal cycle WR write command DQS data strobe signal Tdqss time. Spacing Ctrl control signal DQ poor material signal DQ (0), DQ (1), ···, DQ (15) multiple bits of data signal Element D0, D1, D2, D3 Write data SRWD Data separation signal SRWD(0)? SRWD(1)9... ? SRWD(3i) Multiple bits of data separation signal SRWD_adj Delayed adjustment of data separation Signal SRWD WREN parity feed write enable signal XYSW select signal 15

Claims (1)

200814081 ‘ 十、申請專利範圍： • L 一種記憶體控制電路，其包含有： 相位彳貞測模組，用來债測一資料頻閃（data strobe )訊號與 一時脈訊號之間之相位差； 一控制模組，耦接至該相位偵測模組，用來依據該相位差來 產生一組控制訊號，其中該組控制訊號係對應於該相位 差； _ 一閃鎖（latch)模組，用來依據該資料頻閃訊號之上升緣/ 下降緣來閂鎖一資料訊號所载（carry)之寫入資料； 可偶資料分離器，耦接至該閂鎖模組，用來對該寫入資料 進行奇偶資料分離處理，以產生一資料分離訊號，其中 該資料分離訊號載有對應於該寫入資料之奇/偶資 料；以及 一可調延遲線（adjustable delay line)模組，耦接至該奇偶資 料分離器以及該控制模組，用來依據該組控制訊號來調 整該資料分離訊號所載之奇/偶資料的延遲，其中該奇 /偶資料之延遲量係對應於該組控制訊號。 2·如申請專利範圍第1項所述之記憶體控制電路，其中該資料 訊就係為DQ訊號，而該資料頻閃訊號係為DQS訊號。 3·如申睛專利範圍第1項所述之記憶體控制電路，其中該相位 翁 4貞測板組包含有： 16 200814081 ‘ 祕收單元，分顧來接收該時脈訊號與該資料頻閃訊號； 以及 ' 1 -相位細in，祕至該兩接收單元，时細該相位差。 4.如申請專利範圍第3項所述之記憶體控制電路，其中該相位 偵測模組另包含有：^ 一延遲吻合控制器，耦接至該兩接收單元當中之至少一接收 #元，舰遲吻合控健包含敍少-賴線（delay line) ’用來延遲该時脈訊號及/或該資料頻閃訊號； 其中該她_||依_至少—輯線騎遲之料脈訊號 及/或該資料頻閃訊號來偵測該相位差。 5·如申請專利範圍第1項所述之記憶體控制電路，其中該控制 一係為解碼器，用來依據該相位差進行解碼以產生該組 控制訊號。 6·如申明專利範圍第1項所述之記憶體控制電路，其中該該閂 鎖杈組包含有複數朗鎖，分卿應該資料減之複數個位 元。 7·如申請專利範圍第1項所述之記憶體控制電路，其中該可調 延遲線模組包含有複數個可調延遲線，分別對應於該資料分 / 離訊號之複數個位元，以及每一可調延遲線施加（apply)對 17 200814081 • 應趣控舰號之·量_資料分離域之-個位元。 8 4利細第7項所述之記憶體控㈣路，其中該可調 線模組中之每—可調延遲線包含有複數鑛遲單元。 9 〜、、，/—專利範圍第1項所述之記憶體控制電路，其另包含有: 緩_組’输至射觀舰池，絲對延遲後之奇 % /偶資料進行緩衝控制。 =申請專利範圍第9項所述之記憶體控制電路，其另包含有： 開關模組，耦接至該緩衝模組，用來依據至少一選擇訊號 來輸出該延遲後之奇/偶資料。 種心體控制方法，其包含有： 偉/則一貧料頻閃（data str〇be )訊號與一時脈訊號之間之相位 •差； 依據該相位差來產生一組控制訊號，其中該組控制訊號係對 應於該相位差； 儀據该貧料頻閃訊號之上升緣/下降緣來閂鎖一資料訊號所 載（carry)之寫入資料； 斜該寫入資料進行奇偶資料分離處理，以產生一資料分離訊 ^ 號’其中該資料分離訊號載有對應於該寫入資料之奇/ 偶資料；以及 18 200814081 • 依據該組控制訊號來調整該資料分離訊號所載之奇/偶資料 . 的延遲，其中該奇/偶資料之延遲量係對應於該組控制 訊號。 12·如申請專利細帛η項所述之記憶體控制方法，其中該資料 訊號係為DQ訊號，而該資料頻閃訊號係為DQS訊號。 13·如申請專利範圍第11項所述之記憶體控制方法，其中债測該 ® 資料細όίΐ號與該時脈訊號之間之相位差之步驟另包含有： 分別接收該時脈訊號與該資料頻閃訊號； 利用⑽ize)至少一延遲線（delayline)來延遲該時脈訊號 及/或該資料頻閃訊號；以及 依據該至彡、-延麟觀叙該時脈訊餘/絲資料頻閃 訊號來偵測該相位差。 _ I1 2 3 4.如申請專利麵f n項所述之記憶體控制方法，其中依據該 相位差來產生該組控制訊號之步驟另包含有： 依據該相位差進行解碼以產生該組控制訊號。 19 1 5·如申睛專利範圍帛u項所述之記憶體控制方法，其中依據該 2 龍綱碱之上升緣/下降緣__龍訊朗载之寫 3 入資料之步驟另包含有·· 。 4 利用（utilize)複數個閃鎖來問鎖該資料峨所載之寫入資 200814081 料，其中該複數個閂鎖係分別對應該資料訊號之複數個 位元。 16·如申請專利範圍第11項所述之記憶體控制方法，其中依據該 組控制訊號來調整該資料分離訊號所載之奇/偶資料的延遲 之步驟另包含有： 利用（utilize)複數個可調延遲線（adjustabledelayline)來 調整該資料分離訊號所載之奇/偶資料的延遲，其中該 複數個可調延遲線係分別對應於該資料分離訊號之複 數個位元且母一可调延遲線施加（叩對應該組控 制訊號之延遲量於該資料分離訊號之一個位元。 17·如申請專利範圍帛16項所述之記憶體控制方法，其中每一可 調延遲線包含有複數個延遲單元。 _ 18·如申凊專利範圍第11項所述之記憶體控制方法，其另包含 有·· 對延遲後之奇/偶資料進行緩触制。 I9·如申凊專利耗圍第I8項所述之記憶體控制方法，其另包含有： 利用（utilize) i關模組以依據至少一選擇訊號來輸出該延 遲後之奇/偶資料。 20200814081 ' X. Patent application scope: • L A memory control circuit, comprising: a phase detection module for measuring the phase difference between a data strobe signal and a clock signal; a control module coupled to the phase detection module for generating a set of control signals according to the phase difference, wherein the set of control signals corresponds to the phase difference; _ a latch module The latch data of a data signal is latched according to the rising edge/falling edge of the data strobe signal; and the data separator is coupled to the latch module for writing the data The data is subjected to parity data separation processing to generate a data separation signal, wherein the data separation signal carries odd/even data corresponding to the written data; and an adjustable delay line module coupled to The parity data separator and the control module are configured to adjust a delay of the odd/even data carried by the data separation signal according to the group of control signals, where the delay amount of the odd/even data corresponds to Group control signal. 2. The memory control circuit of claim 1, wherein the data is a DQ signal and the data strobe signal is a DQS signal. 3. The memory control circuit according to claim 1, wherein the phase 4 test panel comprises: 16 200814081 ' The secret unit, the slave receives the clock signal and the data strobe Signal; and '1 - phase fine in, secret to the two receiving units, the phase difference. 4. The memory control circuit of claim 3, wherein the phase detection module further comprises: a delay matching controller coupled to at least one of the two receiving units, The ship's late coincidence control includes a delay line - used to delay the clock signal and / or the data strobe signal; wherein the _|| according to _ at least - the line of the late riding pulse signal And/or the data strobe signal to detect the phase difference. 5. The memory control circuit of claim 1, wherein the control is a decoder for decoding based on the phase difference to generate the set of control signals. 6. The memory control circuit of claim 1, wherein the latch group comprises a plurality of locks, and the branch data should be reduced by a plurality of bits. The memory control circuit of claim 1, wherein the adjustable delay line module comprises a plurality of adjustable delay lines respectively corresponding to a plurality of bits of the data separation/offsignation signal, and Each adjustable delay line is applied to 17 200814081. • The amount of the control ship number _ data separation field - one bit. 8 4 is a memory control (four) circuit as described in item 7, wherein each of the adjustable line modules includes a plurality of ore delay units. 9~,,,/—The memory control circuit described in item 1 of the patent scope further includes: a slow _ group' is transmitted to the shooting tank, and the wire buffers the delayed %/even data after the delay. The memory control circuit of claim 9, further comprising: a switch module coupled to the buffer module for outputting the delayed odd/even data according to the at least one selection signal. The method for controlling the heart body includes: a phase/difference between a data str〇be signal and a clock signal; generating a set of control signals according to the phase difference, wherein the group The control signal corresponds to the phase difference; the instrument latches a write data carried by the data signal according to the rising edge/falling edge of the lean strobe signal; obliquely writing the data for parity data separation processing, Generating a data separation signal wherein the data separation signal carries odd/even data corresponding to the written data; and 18 200814081 • adjusting the odd/even data contained in the data separation signal according to the control signal of the group The delay of the odd/even data corresponds to the set of control signals. 12. The method of controlling a memory as described in the patent application, wherein the data signal is a DQ signal and the data strobe signal is a DQS signal. 13. The method of controlling a memory according to claim 11, wherein the step of measuring the phase difference between the data and the clock signal comprises: receiving the clock signal and the receiving Data strobe signal; using (10) ize) at least one delay line to delay the clock signal and/or the data strobe signal; and according to the 彡, - 延麟观 The clock signal/wire data frequency A flash signal to detect the phase difference. _I1 2 3 4. The memory control method according to claim n, wherein the step of generating the set of control signals according to the phase difference further comprises: decoding according to the phase difference to generate the set of control signals. 19 1 5· The method for controlling the memory according to the scope of the patent application ,u, wherein the step of writing the data according to the rising edge/falling edge of the 2 dragons is further included. · . 4 Utilize a plurality of flash locks to ask for the locks contained in the data, wherein the plurality of latches respectively correspond to a plurality of bits of the data signal. The memory control method according to claim 11, wherein the step of adjusting the delay of the odd/even data contained in the data separation signal according to the control signal further comprises: utilizing a plurality of Adjustable delay line (adjustable delay line) for adjusting the delay of the odd/even data contained in the data separation signal, wherein the plurality of adjustable delay lines respectively correspond to a plurality of bits of the data separation signal and the mother-adjustable delay Line application (叩 corresponds to the delay amount of the group control signal in one bit of the data separation signal. 17) The memory control method described in claim 16 wherein each adjustable delay line includes a plurality of The delay control unit _ 18. The memory control method according to claim 11 of the patent application scope, further comprising: delaying the odd/even data after the delay. The memory control method of item I8, further comprising: utilizing the i-off module to output the delayed odd/even data according to the at least one selection signal.
TW095132912A 2006-09-06 2006-09-06 Memory control circuit and method TWI302318B (en)

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US11/618,937 US7580301B2 (en) 2006-09-06 2007-01-02 Method control circuit performing adjustable data delay operation based upon phase difference between data strobe signal and clock signal, and associated method
DE102007005701.8A DE102007005701B4 (en) 2006-09-06 2007-02-05 Memory control circuit and method
KR1020070033218A KR100832013B1 (en) 2006-09-06 2007-04-04 Memory control circuit and method
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