200813854 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種用戶識別模組卡，特別係有關於 一種具有高容量及增加結構強度之用戶識別模組卡。 【先前技術】 省知之用戶識別模組卡（Subscriber Id邮出cati〇n -Module card ; SIM card)長期以來因受限於封裝電路板之尺 寸及線路佈局空間不足（單面線路），故僅能使用單一記憶 =2作為資料儲存（用，導致目前用戶識別模組卡之二‘ 谷ϊ 一直無法突破64kb，此外，因該封裝電路板之尺寸較 小，且非對稱組設於該用戶識別模組卡，故無法增加該用 戶識別模組卡整體之結構強度。 【發明内容】 本發明之主要目的倍:於据/α ^ ^ 幻你在於挺供一種高容量用戶識別 模組卡，m載板及_半導體封裝件，該半導體封裝 件係具有-承載器、一第一圖案化線路層、一第二圖案化 線路層及-記憶晶片與—控制晶片，該記憶晶片及該控制 晶片係設置於該第二圖案化線路層，以大幅提高用戶識別 模組卡之記憶容量，並且該半導體封裝件係具有一長度係 介於18毫米(mm)至24毫米(mm)之間及一寬度係介於ι〇 14‘5毫米（_)之間之尺寸以增加該用戶識 別模組卡整體之結構強度。 、依據本發明之-種高容量用戶識別模組卡，其包含一 載板及-半導體封裝件，該載板係具有—凹槽，該半導體 200813854 Ή件係置於該載板之該凹槽，該半導體封裝件係包含 豕載盗 帛—圖案化線路層、—第二圖案化線路 層、一記憶晶片、一控制晶片及一封膠體，該承載器係具 有一上表面、一下表面、一第一側邊、一第二側邊、一第 三側邊及—第四側邊，該下表面係朝向該凹槽，該第一側 邊與該第三側邊之垂直間距係定義為—長度，該第二側邊 與該第四侧邊之垂直間距係定義為一寬度，其中該長度係 介t 18毫米（mm)至24冑米（mm)之間，而該寬度係介於 各米（mm)至14.5笔米（mm)之間，該第一圖案化線路層 係形成於該承載器之該上表面，其具有一顯露面，該第二 圖案化線路層係形成於該承載器之該下表面，其定義有一 記憶晶片結合區及一控制晶片結合區，該記憶晶片係設置 於該記憶晶片結合區，該控制晶片係設置於該控制晶片結 合區，該封膠體係密封該記憶晶片與該控制晶片，其具有 一頂面，該頂面與該第一圖案化線路層之該顯露面之垂直 間距係定義為一厚度，其中該厚度係介於〇 35毫米（mm) 至0·8毫米（mm)之間。 【實施方式】 請餐閱第1及2圖，其係本發明之一較佳實施例，一 種高容量用戶識別模組卡20(Subscriber identification Module card ; SIM card)係包含有一載板μ及一半導體封 裝件22 ’該載板21係為一非導電材質且呈扁平片狀，該 載板21係具有一凹槽211及一斜切邊212,在本實施中該 凹槽211係形成於該載板2 1之中心位置，該斜切邊2 12 200813854 化線路層223、一記憶晶片 係形成於該載板21之一角隅，該半導體封裝件22係包含 有一承載裔221、一第一圖案化線路層222、一第二圖案 225以及一 224、一控制晶片 封膠體226,該承载器221係具有一上表面22ia、一下表 面221B、一第一側邊2211、一第二側邊2212、_第三側 邊2213及一第四側邊2214,該第一圖案化線路層222係 形成於該承載器221之該上表面2、21A，該第一^案化線 路層222係具有一顯露面222A及複數個金屬接點ha， 緣空f屬接點222B係可與一讀卡裝置（圖未繪出）電性接 觸，使該讀卡裝置能順利讀取該半導體封裝件22所儲存 之資料，該第二圖案化線路層223係形成於該承载器 之忒下表面221B，該第二圖案化線路層223係定義有一記 憶晶片結合區223A及一控制晶片結合區223B，該記憶晶 片224係設置於該記憶晶片結合區223 a，而該控制晶片 225係叹置於该控制晶片結合區223B，以提高該用戶識別 模、、且卡20之記憶容量，在本實施例中，該記憶晶片η# ”忒控制aa片225係可以覆晶方式（ρΗρ-(^ρ)或打線方式 (Wire-bond)與該第二圖案化線路層223電性連接，該封膠 體226係密封該記憶晶片224與該控制晶片225，以保護 -亥《己晶片224與該控制晶片225。請參閱第2及3圖， 在本貫施例中，該半導體封裝件22係以該承載器2 i i之 忒下表面221B朝向該凹槽211並設置於該載板21之該凹 槽21丨中，且該載板21之該凹槽211係顯露出該第一圖 案化線路層222之該顯露面222A，請參閱第4圖，在本 8 200813854 實施例中，該第一側邊22 11與該第三側邊22 1 3之垂直間 距係定義為一長度L，該第二側邊22 1 2與該第四側邊22 14 之垂直間距係定義為一寬度W，較佳地，該長度L係介於 18毫米（mm)至24亳米（mm)之間，而該寬度w係介於10 宅米（mm)至14.5毫米（mm)之間，以增加該記憶晶片224 與該控制晶片225之緣路佈局空間，進而提高該用戶識別 模組卡20之記憶容量（最低有丨6Mb，最高可達2Gb)。在 本貫施例中’請參閱第4及5圖，該封膠體226係具有一 膠體長度X、一膠體寬度y及一膠體厚度z，較佳地，該 膠體長度X係介於15毫米（mm)至22毫米（mm)之間，該膠 體寬度y係介於8毫米（随）至13毫米之間，該膠體 厚度z係介於0·25毫米（咖）至〇·45毫米之間，且由 於該封膠體226係對稱設置於該半導體封裝件22上，因 此可使得該半導體封裝彳22有較佳之結構強度。此外， 該封膠體226係具有一頂面226八，該頂面226八與該第一 圖案化線路層222之該 心邊顯路面222A之垂直間距係定義為 厚度τ車乂佳地，該厚度τ係介於〇 毫米<_>至㈣ 毫米(mm)之間’以薄型化該半導體封裝件22。 —請再參閱第2及3圖，在本實施例中，該載板21係 二義有帛+ ^點C 1、該半導體封襄件22係定義有- 弟 '一中心點 C 2 舰 a a / ί多體226係定義有一第三中心點 C3，較佳地，該第二中 r ”、' 係與該第一中心點C1重疊， 以使該半導體封裝件2 2血兮| 4 午22與该載板21結合後有較佳之結構 強度，另外，该第三中點 .....占L3係可與該第二中心點C2重 200813854 豐，以使該封膠體226與該半導體封裝件22結合後有較 佳之結構強度。 乂 本發明之保護範圍當視後附之申請專利範圍所界定 :為準，任何熟知此項技藝者’在不脫離本發明之精神： 範圍内所作之任何變化與修&，均4於本發明之保護範 【圖式簡單說明】 第1圖：依據本發明之-較佳實施例，一種高容量用戶識 別模殂卡之立體分解圖w 第2圖：依據本發明之—較佳實施例，該高容量用戶識別 模組卡之立體視圖。 第3圖·依據本發明之_較佳實施例，該高容量用戶識別 模組卡之立體組合圖。 第4圖·依據本發明之一較佳實施例，一半導體封農件之 上視圖。 第5圖 依據本發明之一較佳實施例 側視圖。 該半導體封裝件之 【主要元件符號說明】 〇高容量用戶識別模組卡 21 載板 211 22 半導體封裝件 221 221B 下表面 2211 2213 第三側邊 2214 222 第一圖案化線路層 凹槽 承载器 弟一側邊 第四側邊 21 2 斜切邊 22 1A上表面 2212第二側邊 222A顯露面 10 200813854 222B 金屬接點 223 第二圖案化線路層 223A 記憶晶片 結合區 223B 控制晶片 結合區 224 記，憶晶片 225 控制晶片 226 封膠體 226A 頂面 L 長度 W 寬度 T 厚度 X 膠體長度 y 膠體寬度 Z 膠體厚度 Cl 第一中心 點 C2 第二中心點 C3 第三中心點 11200813854 IX. Description of the Invention: [Technical Field] The present invention relates to a subscriber identity module card, and more particularly to a subscriber identity module card having high capacity and increased structural strength. [Prior Art] The known user identification module card (Subscriber Id mailing out cati〇n -Module card; SIM card) has long been limited by the size of the packaged circuit board and the insufficient layout space (single-sided line), so only Can use a single memory = 2 as a data storage (used, resulting in the current user identification module card two ' Gu Yu has been unable to break through 64kb, in addition, because the package board is small in size, and asymmetrically set in the user identification The module card can not increase the structural strength of the user identification module card as a whole. [Summary of the Invention] The main purpose of the present invention is: according to /α ^ ^, you are in a high-capacity user identification module card, m a carrier and a semiconductor package, the semiconductor package having a carrier, a first patterned circuit layer, a second patterned circuit layer, and a memory chip and a control chip, the memory chip and the control chip Provided on the second patterned circuit layer to substantially increase the memory capacity of the user identification module card, and the semiconductor package has a length ranging from 18 millimeters (mm) to 24 millimeters (mm). The width and the width are between 〇 14'5 mm (_) to increase the structural strength of the user identification module card as a whole. According to the present invention, a high-capacity user identification module card includes a carrier and a semiconductor package having a recess, the semiconductor 200813854 being placed in the recess of the carrier, the semiconductor package comprising an armor-printed circuit layer, a second patterned circuit layer, a memory chip, a control wafer and a gel body, the carrier having an upper surface, a lower surface, a first side, a second side, a third side, and a fourth side, the lower surface is oriented toward the groove, and a vertical distance between the first side and the third side is defined as a length, and a vertical distance between the second side and the fourth side is Defined as a width, wherein the length is between 18 mm (mm) and 24 mm (mm), and the width is between meters (mm) and 14.5 pens (mm), the first a patterned circuit layer formed on the upper surface of the carrier, having a exposed surface, the second Forming a circuit layer formed on the lower surface of the carrier, defining a memory chip bonding region and a control wafer bonding region, the memory chip being disposed in the memory chip bonding region, the control chip being disposed on the control chip a bonding layer, the encapsulation system sealing the memory wafer and the control wafer, and having a top surface, the vertical spacing of the top surface and the exposed surface of the first patterned circuit layer is defined as a thickness, wherein the thickness is Between 35 mm (mm) and 0. 8 mm (mm). [Embodiment] Please refer to Figures 1 and 2, which are a high-capacity user identification module according to a preferred embodiment of the present invention. The card identification device (SIM card) includes a carrier board μ and a semiconductor package 22'. The carrier board 21 is a non-conductive material and has a flat sheet shape. The carrier board 21 has a recess 211. And a beveled edge 212. In the embodiment, the groove 211 is formed at a central position of the carrier 21, and the beveled edge 2 12 200813854 is formed on the circuit board 21 and a memory chip is formed on the carrier 21 a corner, the semiconductor package The 22 series includes a carrier 221, a first patterned circuit layer 222, a second pattern 225 and a 224, and a control wafer encapsulant 226. The carrier 221 has an upper surface 22ia, a lower surface 221B, and a first The first patterned circuit layer 222 is formed on the upper surface 2, 21A of the carrier 221, and the first patterned side layer 2212, the second side edge 2212, and the fourth side edge 2214. The first circuit layer 222 has a exposed surface 222A and a plurality of metal contacts ha, and the edge space 222B is electrically contactable with a card reading device (not shown) to enable the card reading. The device can smoothly read the data stored in the semiconductor package 22. The second patterned circuit layer 223 is formed on the lower surface 221B of the carrier, and the second patterned circuit layer 223 defines a memory chip bonding region. 223A and a control wafer bonding region 223B, the memory chip 224 is disposed in the memory wafer bonding region 223a, and the control wafer 225 is placed on the control wafer bonding region 223B to improve the user identification mode, and the card 20 memory capacity, in this embodiment, the record Recalling the wafer η# 忒 忒 control aa piece 225 can be electrically connected in a flip chip manner (ρΗρ-(^ρ) or wire-bonding (Wire-bond) to the second patterned circuit layer 223, the encapsulant 226 sealing the The memory wafer 224 and the control wafer 225 are protected to protect the wafer 224 from the control wafer 225. Referring to FIGS. 2 and 3 , in the present embodiment, the semiconductor package 22 faces the recess 211 of the carrier 2 ii toward the recess 211 and is disposed in the recess 21 of the carrier 21 . The groove 211 of the carrier 21 exposes the exposed surface 222A of the first patterned circuit layer 222. Referring to FIG. 4, in the embodiment of the present invention, the first side 22 11 The vertical spacing from the third side 22 1 3 is defined as a length L, and the vertical spacing of the second side 22 1 2 and the fourth side 22 14 is defined as a width W. Preferably, the The length L is between 18 millimeters (mm) and 24 millimeters (mm), and the width w is between 10 house meters (mm) and 14.5 millimeters (mm) to increase the memory wafer 224 and The layout space of the chip 225 is controlled to further improve the memory capacity of the user identification module card 20 (minimum M6Mb, up to 2Gb). In the present embodiment, please refer to Figures 4 and 5, the encapsulant 226 has a colloidal length X, a colloidal width y and a colloidal thickness z. Preferably, the colloidal length X is between 15 mm ( Between mm) and 22 mm (mm), the colloid width y is between 8 mm (s) and 13 mm, and the thickness of the colloid z is between 0. 25 mm (coffee) and 〇 45 mm. And because the encapsulant 226 is symmetrically disposed on the semiconductor package 22, the semiconductor package 22 can be made to have better structural strength. In addition, the encapsulant 226 has a top surface 226, and the vertical distance between the top surface 226 and the sidewall 222A of the first patterned circuit layer 222 is defined as a thickness τ, which is a thickness. The τ system is between 〇 mm <_> to (four) millimeters (mm) to thin the semiconductor package 22. - Please refer to Figures 2 and 3 again. In this embodiment, the carrier 21 is 二 帛 + ^ point C 1 , and the semiconductor package 22 is defined as - a 'center point C 2 ship aa / ί multibody 226 defines a third center point C3, preferably, the second middle r ′, ' is overlapped with the first center point C1, so that the semiconductor package 2 2 bloody | 4 noon 22 The combination of the carrier board 21 has a better structural strength. In addition, the third midpoint ....., the L3 system can be as heavy as the second center point C2, so that the encapsulant 226 and the semiconductor package </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Variations and repairs, both of which are in the protection of the present invention [Simplified description of the drawings] FIG. 1 is a perspective exploded view of a high-capacity user-recognition module, according to a preferred embodiment of the present invention. A perspective view of the high capacity subscriber identity module card in accordance with a preferred embodiment of the present invention. According to a preferred embodiment of the present invention, a three-dimensional combination diagram of the high-capacity subscriber identity module card. FIG. 4 is a top view of a semiconductor enclosure member according to a preferred embodiment of the present invention. A side view of a preferred embodiment of the present invention. [Main component symbol description] of the semiconductor package 〇 High-capacity user identification module card 21 Carrier board 211 22 Semiconductor package 221 221B Lower surface 2211 2213 Third side 2214 222 The first patterned circuit layer groove carrier is on one side of the fourth side edge 21 2 the beveled edge 22 1A the upper surface 2212 the second side 222A is exposed surface 10 200813854 222B metal contact 223 second patterned circuit layer 223A memory Wafer bonding region 223B controls wafer bonding region 224, memory wafer 225 control wafer 226 encapsulant 226A top surface L length W width T thickness X colloid length y colloid width Z colloid thickness Cl first center point C2 second center point C3 third Center point 11