200812080 九、發明說明： _ 【發明所屬之技術領域】 本發明係關於一種高耐壓之半導體裝置，特別是關於 使用在電源電路等之絕緣閘極型雙極電晶體 Insulated Gate Bipolar Transistor)。 【先前技術】 近年來，絕緣閘極型雙極電晶體由於具備具有閑極嗯 緣性之MOSFET、及具有大電流之開關特性之雙極的兩方 面之長處特性，因此係使周在電源電路等^ 就此種絕緣閘極型雙極電晶體之構造而言，如第3固 所示，在N型基極區域1之下側整面形成有與該n型基^ 區域1為相反導電型之P型集極區域5而構成之絕緣閑極 型雙極電晶體（以下稱第1絕緣閘極型雙極電晶體）係為公 知者。 #' 在前述第1絕緣閘極型雙極電晶體中，具有以下件 點··即使在高溫動作時，亦可獲得與低溫動作時同等之= 動時間tf、亦即絕緣閘極型雙極電晶體成為關斷狀態為2 之時間。在此，所謂絕緣閘極型雙極電晶體成為關斷狀態 為止之時間係定義為··絕緣閘極型雙極電晶體之集極電流 脈衝的振幅從最大振幅之10%(電晶體呈導通狀態）成為卯 %(電晶體呈關斷狀態）的時間。 ^ 然而，在高溫動作時，絕緣閘極型雙極電晶體呈導通 狀態時之Ν型基極區域的電阻値（R〇n)會增加，因而會有 動作電壓變大且集極-射極間飽和電壓Vce(sat)變大的問 319310 5 200812080 題。 再者，除了如前述第1絕緣閘極型雙極電晶體在]^型 基極區域1之下側整面形成與該N型基極區域i為相反導 電型之p型集極區域5之外，另外有—種形成肖特基阻障 電極的絕緣_型雙極電晶體（以τ稱第2絕緣閘極型雙 極電晶體）。 該第2絕緣閘極型雙極電晶體係與前述第丨絕緣閘極 ^雙極電晶體相比較’具有高溫動作時之Vee(sat)較小之 優點。另一方面，由於注入N型基極區域之多數電洞的消 ^需要時間，因此與第丨絕緣閘極型雙極電晶體相比較 日可’會有啓動時間tf變長之問題。 為了解決上述第1及第2絕緣閘極型雙極電晶體之缺 ，，如第4圖所示揭示有一種在N型基極區域i之下侧間 斷性形成P型集極區域1〇5，並在未形成有p型集極區域 1〇5之區域形成肖特基阻障電極（直接連接n型基極區域1 及集極電極8之區域1〇〇)的絕緣閘極型雙極電晶體（參照 例如專利文獻1)。 根據該絕緣閘極型雙極電晶體，形成有p型集極區域 105之裝置部分係發揮前述第1絕緣閘極型雙極電晶體之 功能’形成有肖特基阻障電極之裝置部分係發揮前述第2 絕緣閘極型雙極電晶體之功能。 因此’可實現一種同時具有第1及第2絕緣閘極型雙 極兒晶體之特性’高溫動作時之Vce(sat)較小且啓動時間 tf亦較短的纟巴緣閘極型雙極電晶體。 6 319310 200812080 .. - * k •(專利文獻1)日本特開2003-249654號公報 【發明内容】 (發明所欲解決之課題） 然而，前述專利文w記載之絕緣閘極型雙極電晶體 中，具有比較容易產生衝穿（punch thr〇ugh)之問題。 +亦即’在集極電極8與射極電極n之間，施加使射極 毛極11側之電位比集極區域105側之電位高的電壓之狀態 下，使閘極關斷時，形成在P型基極區域2與N型基極= 域1之界面的PN接合會朝相反方向偏移，西會由該^接 合產生空乏層並擴展至N型基極區域1。 牧 因此，施加至ΡΝ接合之電壓超過預定之電壓時，由 於k ΡΝ接合擴展之空乏層會到達肖特基阻障電極… 位阻障較低，因而會發生衝穿。 本發明係鑑於上述情事而研創者，其係提供一種高溫 動作％之集極一射極間飽和電壓Vce(sat)比習知例小，啓 動時間tf亦比習知例短，且更進一步良好地防止衝穿之發 生的絕緣閘極型雙極電晶體。 (解決課題之手段） —本發明之絕緣閘極型雙極電晶體的第丨態樣係具備： 第1導電型之第1半導體區域（例如實施形態之N型基極 區域1);形成在該第1半導體區域之一方主面側的第2導 電型之第2半導體區域（例如實施形態之p型基極區域2); 形成在該第2半導體區域内之表面之第1導電型之第3半 導體區域（例如實施形態之N型射極區域3);在前述第j 7 319310 200812080 -·半導體區域之另一方主面例 .1導電叙第4半導體以=切預定之深纽寬度的第 4).开4… 域(例如實施形態之N型緩衝區域 5半導體内之表面之第2導電型之第 缘= 形態之P型集極區域5);以隔介絕 、、彖fe(例如貫施形態之絕緣 、、 掛6夕古斗、/ 、 、6)與刖述弟2半導體區域相 7V 罨桎（例如貫施形態之閘極電極 7)，及形成在該第1半導妒 ^ ,- 、 區域之另一方主面側的集極電 極（例如貫施形態之集極電極 什筮4A 卞4电桂8)，刖述第1半導體區域、前 ^導^ 域及前述第5半導體區域係露出於前述第 + :體區域之另一方主面’且分別與前述集極電極接合。 -明之料閘極型雙極電晶體的第2態樣係具備·· =Ί之第i半導體區域（例如實施形態之N型基極 :二？’幵:成在5亥第1半導體區域之-方主面側的溝槽(例 ^施形態之溝槽9);形成在該溝槽之側壁之第2導電型 之第2半導體區域（例如實施形態之P型基極區域2A)，·形 成在該第2半導體區域内之表面之第1導電型之第3半導 f區域(例如實施形態之N型射極區域3A);在前述第工半 ‘體區域之另—方主面側形成有預定之深度及寬度的第1 V电型之第4半導體區域（例如實施形態之N型緩衝區域 句；形成在該第4半導體區域内之表面之第2導電型之第 半¥體區域（例如貫施形態之p型集極區域5”隔介絕緣 膜（例如實施形態之絕緣膜6A)而形成在前述溝槽内部的 閘極電極（例如實施形態之閘極電極7A);及形成在前述第 1半V體區域之另一方主面側的集極電極（例如實施形態之 8 319310 200812080 -.集極電極8);前述第〗半導體 -及前述第5半導體區域俜霖'昂4半導體區域 版L 糸路出於珂述第i 一方主面’且分別與前述集極電極接合。域之另 一般而言，前述第4及第5丰逡 電極形成電阻性接觸，且前述第 體：：與前述集極 形成與特基接觸。 、體區域與集極電極 較佳為，前述第5半導體區 體區域之另一太士品η , 人出於則述第1半導 區域方主面側”的部分’係由前述苐4半導體 第4 體之、%緣閘極型雙極電晶體’較佳為前述 二⑽比前述第1半導體區域更高之雜。 此外，較佳為前述第4半導妒巧妗 成複數個。 牛¥體£域係以預定之間隔形 (發明之效果） 缓衝㈣’根縣發明，可獲得町之效果：由 ㈣S域所包圍之集極區域部分係發揮習 果由 極型雙極電晶體的功能接弟1絕緣間 合之部分係發揮羽知”域直接與集極電極接 能，當對知極電^力=2 極型雙極電晶體的功 域經由電壓而設成導通狀態時，從集極區 極區域，產=導極電極直接將電洞供給至N型基 果。i生料度调憂，而可得導通電阻比習知小的效 第 再者’根據本發明，由於交互地形成習知之第1及 319310 9 200812080 2絕緣_型雙極電晶體，因此具相下之效果：同時具 者之特性」可獲得高溫動作時之集極—射極間飽和電 ^ ce(sat)與第2絕緣閘極型雙極電晶體同樣地小，且啓 動k間tf與第！絕緣閘極型雙極電晶體同樣短的特性。 之門：二根據本發明，由於在㈣基極區域與集極區域 巴二二衝區域而構成，因此在N型基極區域與集極 f:之間^加相反方向電屢的狀態下使電晶體關斷時，可 卩1形成在N型基極區域與集極區域之 伸，亦即抑制空乏層到達至集極電極’而可防止 4L ° ' 【實施方式】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage semiconductor device, and more particularly to an insulated gate bipolar transistor used in a power supply circuit or the like. [Prior Art] In recent years, an insulated gate type bipolar transistor has a long-term characteristic of two aspects of a MOSFET having a immersive edge and a switching characteristic having a large current, so that the power supply circuit is In the structure of the insulated gate type bipolar transistor, as shown in the third solid, the entire lower surface of the N-type base region 1 is formed to be opposite to the n-type base region 1 An insulated idle type bipolar transistor (hereinafter referred to as a first insulated gate type bipolar transistor) constituted by the P-type collector region 5 is known. #' In the first insulated gate type bipolar transistor, the following points are obtained. · Even at high temperature operation, the same dynamic time tf as in the low temperature operation, that is, the insulated gate type bipolar can be obtained. The transistor becomes the time when the off state is 2. Here, the time until the insulating gate type bipolar transistor is turned off is defined as: · The amplitude of the collector current pulse of the insulated gate type bipolar transistor is 10% of the maximum amplitude (the transistor is turned on) State) becomes the time of 卯% (the transistor is in the off state). ^ However, at high temperature operation, the resistance 値(R〇n) of the 基-type base region increases when the insulating gate-type bipolar transistor is turned on, and thus the operating voltage becomes large and the collector-emitter The problem that the inter-saturation voltage Vce(sat) becomes larger is 319310 5 200812080. Further, in addition to the first insulating gate type bipolar transistor, a p-type collector region 5 having a conductivity type opposite to the N-type base region i is formed on the lower surface of the base region 1 of the first type. In addition, there is an insulating _ type bipolar transistor (referred to as a second insulating gate bipolar transistor in τ) which forms a Schottky barrier electrode. The second insulated gate type bipolar crystal system has the advantage of having a small Vee (sat) when the high temperature operation is compared with the above-mentioned second insulating gate ^ bipolar transistor. On the other hand, since it takes time to inject a large number of holes in the N-type base region, there is a problem that the startup time tf becomes longer as compared with the second insulating gate type bipolar transistor. In order to solve the above-mentioned shortage of the first and second insulated gate type bipolar transistors, as shown in FIG. 4, there is disclosed a P-type collector region 1〇5 intermittently formed under the N-type base region i. And an insulating gate type bipolar which forms a Schottky barrier electrode (a region directly connected to the n-type base region 1 and the collector electrode 8) in a region where the p-type collector region 1〇5 is not formed. A transistor (see, for example, Patent Document 1). According to the insulated gate type bipolar transistor, the device portion in which the p-type collector region 105 is formed functions as the first insulating gate type bipolar transistor; the device portion in which the Schottky barrier electrode is formed is The function of the second insulated gate type bipolar transistor is exerted. Therefore, it is possible to realize a characteristic of the first and second insulated gate type bipolar crystals, which has a small Vce(sat) at a high temperature operation and a short start-up time tf. Crystal. 6 319310 200812080 .. - * k (Patent Document 1) Japanese Laid-Open Patent Publication No. 2003-249654 (Summary of the Invention) However, the insulating gate type bipolar transistor described in the above Patent Document w Among them, there is a problem that punching is relatively easy to occur. In other words, a state in which a potential higher than the potential of the collector region 105 side is applied between the collector electrode 8 and the emitter electrode n is applied, and the gate is turned off. The PN junction at the interface of the P-type base region 2 and the N-type base = domain 1 will be shifted in the opposite direction, and the west will generate a depletion layer and expand to the N-type base region 1. Therefore, when the voltage applied to the ΡΝ junction exceeds a predetermined voltage, the depletion layer extended by the k ΡΝ junction reaches the Schottky barrier electrode... The bit barrier is low, and thus the punch-through occurs. The present invention has been made in view of the above circumstances, and provides a collector-emitter saturation voltage Vce(sat) of a high-temperature operation % which is smaller than the conventional example, and the startup time tf is shorter than the conventional example, and is further improved. Insulated gate type bipolar transistor that prevents the occurrence of punch-through. (Means for Solving the Problem) - The first aspect of the insulated gate type bipolar transistor of the present invention includes: a first semiconductor region of a first conductivity type (for example, an N-type base region 1 of an embodiment); a second semiconductor region of a second conductivity type on one side of the first semiconductor region (for example, a p-type base region 2 of the embodiment); and a first conductivity type formed on a surface of the second semiconductor region 3 semiconductor region (for example, the N-type emitter region 3 of the embodiment); in the above-mentioned j 7 319310 200812080 - the other main surface of the semiconductor region. 1 conductive semiconductor 4 semiconductor = the predetermined deep-width width 4). Open 4... field (for example, the N-type buffer region 5 of the embodiment, the second edge of the second conductivity type of the surface in the semiconductor = the P-type collector region 5 of the form); Insulation of the form, hangs on the 6th eve, /, 6) and 7V 罨桎 of the semiconductor region of the 刖 弟 2 (for example, the gate electrode 7 of the form), and is formed in the first semi-conductor ^ , - , the collector electrode on the other main side of the region (for example, the collector electrode of the form) 4A 卞 4 Gui 8), cut off the feet of said first semiconductor region, the front guide ^ ^ domain and the fifth semiconductor region is exposed based on the first +: other principal surface 'body area and engage with the collector electrode. - The second aspect of the gate-type bipolar transistor of the Ming material has the i-th semiconductor region of the · = Ί (for example, the N-type base of the embodiment: two? '幵: into the first semiconductor region of 5 hai a trench on the main surface side (the trench 9 in the embodiment); a second semiconductor region of the second conductivity type formed on the sidewall of the trench (for example, the P-type base region 2A in the embodiment), a third semiconducting f region of the first conductivity type formed on the surface of the second semiconductor region (for example, the N-type emitter region 3A of the embodiment); and the other main surface side of the first working half body region Forming a fourth semiconductor region of the first V-type having a predetermined depth and width (for example, an N-type buffer region sentence of the embodiment; and a second-half body region of the second conductivity type formed on the surface of the fourth semiconductor region) (for example, a p-type collector region 5 of a continuous form) a gate electrode (for example, a gate electrode 7A of the embodiment) formed in the trench by a dielectric insulating film (for example, the insulating film 6A of the embodiment); a collector electrode on the other main surface side of the first half V body region (for example, embodiment 8 319310 200812080) - collector electrode 8); said semiconductor semiconductor - and said fifth semiconductor region 俜 ' 昂 4 semiconductor region plate L 糸 珂 珂 珂 珂 珂 珂 珂 珂 珂 珂 。 。 。 。 。 。 。 。 。 域 域 域 域Further, in general, the fourth and fifth radiant electrodes are in ohmic contact, and the first body: is in contact with the collector and the base; and the body region and the collector electrode are preferably the fifth Another stellite η of the semiconductor region region, the portion of the main surface side of the first semiconducting region is "the portion of the 苐4 semiconductor fourth body, the % edge gate type bipolar transistor" Preferably, the second (10) is higher than the first semiconductor region. Further, it is preferable that the fourth semi-conductor is formed into a plurality of blocks. The bovine body is formed at a predetermined interval (the effect of the invention) Buffering (4) 'Invented by the roots of the county, the effect of the town can be obtained: the part of the collector region surrounded by the (4) S-domain plays a role in the function of the pole-type bipolar transistor. "The field is directly connected to the collector electrode. When it is connected to the pole, it is the power of the 2-pole bipolar transistor. When the domain is turned on via the voltage, the hole is directly supplied from the collector region to the N-type base. The raw material is adjusted, and the on-resistance is smaller than conventionally. In addition, according to the present invention, since the first and third 319310 9 200812080 2 insulated _ type bipolar transistors are formed alternately, the effect of the phase is obtained: the characteristics of the same function can be obtained. The pole-emitter saturation electric s(sat) is as small as the second insulated gate bipolar transistor, and the k-th tf is the same as the second insulating gate bipolar transistor. According to the present invention, since it is constituted by the (b) base region and the collector region, the transistor is formed in a state in which the opposite direction is repeated between the N-type base region and the collector f: When turned off, the 卩1 can be formed in the extension of the N-type base region and the collector region, that is, the vacancy layer is prevented from reaching the collector electrode ′, and 4 L ° can be prevented. [Embodiment]
以下，說明本實施形態之絕緣閉極型雙極 (第1實施形態） 利用圖式說明本發明第 電晶體。第1圖係本發明第 笔日日體之剖面構造的概念圖 1實施形態之絕緣閘極型雙極 1實施形態之絕緣閘極型雙極 第圖中本貝化形恶之絕緣間極型雙極 具有Ν型基極區域hp型 孓基極區域2、射極區域3、缓衡 S域4及集極區域5之半導體基板所構成。 Ν型基極區域1係擴散有 坤等）之Ν型半導體區域（第^ Ρ型基極區域2係在上述 之主面側）擴散Ρ型雜質（例如 Ρ型半導體區域。 Ν型雜質（例如ρ ··磷或as ·· 導電型之半導體區域）。 N型基極區域1之上面（〆方 B ··硼等），而形成為條狀之 319310 10 200812080 •雜質：==係在上述p型基極區域2之上面擴散_ 才准貝而形成之N型半導體區域。 缓衝區域4係在N型基極區域1之下面（另一方主 側）擴散N型雜質而形成之N型半導體區域。 木極區域5係在上述緩衝區域4之下面擴散p型雜 而形成之P型半導體區域。 、 在上述半導體基板之上面亦即N型基極區域1之上 面’形成有藉由熱氧化或CVD(化學氣相沉積，叫牆a! or Dep〇sltlon)產生之矽氧化膜等之閘極絕緣胰$。 在上述閘極絕緣膜6上部形成有閘極電極7，在該閘 °電極7上藉由CVD等形成有層間絕緣膜1 〇。 射極電極U係形成在上述層間絕緣膜1〇、射極區域3 及P型基極區域2上部，並電性接合於射極區域 基極區域2。 & 在半導體基板之下面、亦即N型基極區域丨之另一主 面’形成有集極電極8。 P型基極區域2及射極區域3係露出於半導體基板之 上面，且貫通形成於層間絕緣膜10之開孔部2卜並電性 連接於射極電極11。 因此，P型基極區域2及射極區域3係因射極電極n 而短路’經常成為同電位之狀態。 在此，射極區域3係比N型基極區域1更高濃度地擴 政雜質而形成，亦即藉由低電阻接觸而與射極電極η接合 (亦即形成低電阻性之接合接點)，而形成良好之接合狀態。 319310 11 200812080 在此，由第1圖可得知，從與半導體基板之面垂直之 方，看之俯視t，射極區域3係形成於與p型基極區域2 重疊’且完全包含於P型基極區域2之位置，且形成為深 度亦比P型基極區域2淺之擴散層，並形成為底面及侧面 必定與P型基極區域2接合。 /再者，同樣地，P型基極區域2係高濃度地擴散雜質 而形成，亦即藉由低電阻接觸而與射極電極u接合（亦即 形成低包阻性之接合接點），而形成良好之接合狀態。 與間極電極7相對向。 ’外周緣部22係隔介閘極絕緣膜6 ,與閘極電極7相對向之P型基極區域2的外周緣部22 係成為通道形成區域，在對閘極電極7施加所設定之臨限 値電壓（threshold voltage)以上之電壓時，在閘極電極7 正下方形成有N型反轉層（通道）。 閘極電極7與射極電極u係藉由以psG(摻磷矽酸鹽 玻璃）、BPSG(摻硼磷矽酸鹽玻璃）或氮化矽膜等所構成之ς 間絕緣膜10進行電性絕緣。 本第1實施形態之絕緣閘極型電晶體中，係以從半導 體基板之上面侧俯視觀看日夺Ρ型基極區域2形成為帶狀或 條狀的情形加以說明。然而，Ρ型基極區域2之俯視觀看 時的形狀並不限定於帶狀或條狀，亦可形成為例如島狀 (island)、格子狀、網眼狀等。 如上所述，在半導體基板之下面形成有緩衝區域4及 集極區域5。 319310 12 200812080 :.在此’緩㈣縣極 -之下面擴散N型雜質而形 牛7基板） 出於N型基極區域^下品月文層者擴放層表面係露 “面，露出的表面以外的外周而在 卢型基極區域1所包圍（在接合之狀態下）而形成。，、 在^ 1 mu中’從半導體基板 看時，緩衝區域4及集極區㈣]俯視咸 然而，緩衝區域4之的=形成“狀或條狀。 條狀，亦可形成為例如限定於上述之帶狀或 ，狀、格子狀、網眼狀等。 再者，緩衝區域4筏势中友丄μ ，# 濃度更高之濃度而形成—υ區域1之雜質 ::，集極區域5係從緩衝區域4之下面擴 貝而形成為擴散層者，擴 1亦隹 側，露出之表 田放層表面係路出於集極電極8 合之狀態下）而形成。^面係由緩衝區域4所包圍（在接 看時，衝:t導體基板之下面側俯視觀 '、/、成衝區域4重疊，且形成為包含於 二=二部之形狀’且形狀係形成為與緩衝區域4之形 狀對應的帶狀或條狀。 ^ 亦可集極區域5之形狀係配合緩衝區域4之形狀， /成為例如島狀、格子狀、網眼狀等。 下面，二^域A及未形成有集極區域5之半導體基板的 路出有N型基極區域1。 區域導體基板之下面形成有集極電極8,緩衝 ^區域5及N型基極區域丨係電性連接於上述 319310 13 200812080 :.集極電極8。 緩衝區域4及集極區域5與集極電極8之接合中，係 藉由進行良好之低電阻接觸之雜質濃度而形成。〇 ’、 亦即，緩衝區域4及集極區域5係如以往所進行者， 分別以高雜質濃度(例如10%Μ，形成，而將與集極電極 8之電位轉薄薄地形成為可藉由穿隧效果使載體自由地 通過，以貫現與集極電極8之低電阻接觸。 另一方面，N型基極區域1之雜質濃度係比緩衝區域 4之雜質濃度低’例如為5χ1〇"至5χ1〇14〇μ_3…隹托 =極8之接合中，形成並非低電阻接觸而是肖特“二 5 )所致之肖特基電極1〇〇。亦即，在集極電極8盘N型基 極區域1之界面，形成具有多數 : 宵特基阻障。 ^生之Μ特性的 雔乂上所述，第1圖所示之第1實施形態的絕緣閘極型 二極笔晶體中，緩衝區域4及集極區域5與集極電極 合而形成之部分係發揮習知之第1 接 的功— ^. 乏弟1、、，巴緣閘極型雙極電晶體 及隹:「Γ 基極區域1之未形成緩衝區域4 及木㈣：5且與集極電極8接合而形成之部分係發揮羽 知之第2絕緣閘極型雙極電晶體的功能， ’、 白 亦即，在集極電極8與射極電極 電極8側之電位相對於射極施加使集極 並對間極電極7施加被Μ為使該 定臨限値電壓以上的電壓。 、、之包£的預 由此，絕緣閉極型雙極電晶體係呈導通狀態，而將電 319310 14 200812080 注入至N型基極區域1内。 N型基極區域1成為肖特 電極8將電洞注入n型基 洞從集極區域5經由緩衝區域4 再者，集極電極8係相對於 基阻障電極100。因此，從集極 極區域1内。 < m果，在N型基極區域！產生傳導度調變，可獲得導 通電阻小之絕緣閘極型雙極電晶體。 亦即，第1絕緣間極型雙極電晶體係形成在··與隼極 電極8連接之p型集極區域5、及介插在該集極區域^與 N型基極區域！之間的緩衝區么。 再者，第2絕緣閘極型雙極電晶體係形成在：集極電 極8與N型基極11域1的連接部之與肖特基電極1〇〇對應 口此與專利文獻1同樣地，形成交互配置有第1絕 緣閘極電晶體及第2絕緣閘極型雙極電晶體之構造，可實 現一種具備高溫動作時之Vce(sat)較小且啓動時間汀亦較 短之特性的絕緣閘極型雙極電晶體。 再者，本實施形態之絕緣閛極型雙極電晶體中，係形 成N型基極區域〗露出於半導體基板之下面且與集極電極 8連接’且N型之緩衝區域4由N型基極區域丨所包圍的 構造，而肖特基電極100係配置在比突出於N型基極區域 1内之緩衝區域4更遠離p型基極區域2的位置。 在絕緣閘極型雙極電晶體之動作中，在對形成在 基極^域1與P型基極區域2之PN接合施加反方向電壓 的狀態下，當絕緣閘極型電晶體呈關斷狀態時，空乏層係 319310 15 200812080 從上述PN接合朝集極電極8之方向延伸。 然而，在本實施形能φ， 域1之雜質、農产古& / 糟由雜質濃度比Ν型基極區 部延伸，而良好地抑制空乏乏層從上述接合 極恭托ΰ ^ 乏d到達肖特基電極100、即集 極“亟8，而難以產生衝穿(可防止衝穿)。 夂缓有效地抑制衝穿，週期性(間歇性)形成之 i缓衝(^4 隔⑷卩肖特基接合部之寬度）以依 質濃度、及施加在集…；N型基極區域1之雜 。4極電極11之間的電壓， 適日，调整並設定。上述間隔d較佳為深度0之1/2左右， 二如，米度設為6㈣時’則將間隔d設為3… (弟2貫施形態） 帝曰j用圖式#明本發明第2實施形態之絕緣閘極型雙極 包曰曰體。# 2圖係本發明第2實施形態之絕緣閘極型雙極 電日日體之剖面構造的概念圖。 •如第2圖所示，係形成為於溝槽内开）成有絕緣間極型 電晶體之溝渠開極構造，關於本發明特徵之—的周期性形 成之集極區域5、及在各集極區域5與N型基極區域丨之 間介插形成有緩衝區域4的構成，係與第丨實施形態相同， 對同樣之構成標記同一符號，並省略其說明。 與第1實施形態相同，N型基極區域1係擴散有1^型 雜質之N型半導體區域（第j導電型之半導體區域）。 P型基極區域2A係在上述ν型基極區域1之上面（一 方之主面側）擴散P型雜質，而形成為條狀之p型半導體區 16 319310 200812080 •.域0Hereinafter, the insulated closed-pole bipolar according to the present embodiment (first embodiment) will be described with reference to the drawings. 1 is a concept of a cross-sectional structure of a Japanese-Japanese body of the present invention. FIG. 1 is an insulating gate-type bipolar embodiment of an insulated gate type bipolar 1 embodiment of the present embodiment. The bipolar electrode is composed of a semiconductor substrate having a Ν-type base region hp-type germanium base region 2, an emitter region 3, a balanced S domain 4, and a collector region 5. The 基-type semiconductor region (the 基-type base region 2 is on the main surface side of the Ν-type base region 1) is diffused with a Ρ-type impurity (for example, a Ρ-type semiconductor region. ρ ·· Phosphorus or as ·· Conductive semiconductor region). The upper surface of the N-type base region 1 (〆B · · boron, etc.), and formed into strips 319310 10 200812080 • Impurities: == is above The upper surface of the p-type base region 2 is diffused to form an N-type semiconductor region. The buffer region 4 is an N-type formed by diffusing N-type impurities under the N-type base region 1 (the other main side). a semiconductor region. The wood region 5 is a P-type semiconductor region formed by diffusing a p-type impurity under the buffer region 4. The upper surface of the semiconductor substrate, that is, the upper surface of the N-type base region 1 is formed with heat. A gate insulating insulator of a ruthenium oxide film or the like which is produced by oxidation or CVD (chemical vapor deposition, called wall a! or Dep〇sltlon). A gate electrode 7 is formed on the upper portion of the gate insulating film 6, at the gate An interlayer insulating film 1 is formed on the electrode 7 by CVD or the like. The emitter electrode U is formed. The interlayer insulating film 1A, the emitter region 3, and the upper portion of the P-type base region 2 are electrically bonded to the emitter region base region 2. & Under the semiconductor substrate, that is, the N-type base region The other main surface 'the collector electrode 8 is formed. The P-type base region 2 and the emitter region 3 are exposed on the upper surface of the semiconductor substrate, and are formed through the opening portion 2 of the interlayer insulating film 10 and electrically connected thereto. Therefore, the P-type base region 2 and the emitter region 3 are short-circuited by the emitter electrode n and often have the same potential state. Here, the emitter region 3 is more than the N-type base region 1 It is formed by expanding the impurity at a high concentration, that is, by bonding with the emitter electrode η by low-resistance contact (that is, forming a low-resistance joint), thereby forming a good joint state. 319310 11 200812080 Here, As can be seen from Fig. 1, the emitter region 3 is formed to overlap the p-type base region 2 and is completely contained in the P-type base region 2 from the plane perpendicular to the surface of the semiconductor substrate. And forming a diffusion layer having a shallower depth than the P-type base region 2, and forming a bottom The surface and the side surface are necessarily bonded to the P-type base region 2. Further, similarly, the P-type base region 2 is formed by diffusing impurities at a high concentration, that is, bonding with the emitter electrode u by low-resistance contact ( That is, a low-resistance joint is formed, and a good joint state is formed. The anode electrode 7 is opposed to the inter-electrode electrode 7. The outer peripheral portion 22 is separated from the gate insulating film 6 and opposed to the gate electrode 7. The outer peripheral edge portion 22 of the P-type base region 2 is a channel formation region. When a voltage equal to or higher than a threshold voltage is applied to the gate electrode 7, a N is formed directly under the gate electrode 7. Type inversion layer (channel). The gate electrode 7 and the emitter electrode u are electrically connected by an interlayer insulating film 10 made of psG (phosphorus doped phosphate glass), BPSG (boron-doped phosphonium silicate glass) or tantalum nitride film. insulation. In the insulated gate type transistor of the first embodiment, the case where the day-old base region 2 is formed in a strip shape or a strip shape as viewed from the upper surface side of the semiconductor substrate will be described. However, the shape of the 基-type base region 2 in plan view is not limited to a strip shape or a strip shape, and may be formed, for example, in an island shape, a lattice shape, a mesh shape or the like. As described above, the buffer region 4 and the collector region 5 are formed on the lower surface of the semiconductor substrate. 319310 12 200812080 :. In this 'slow (four) county pole - below the diffusion of N-type impurities and the shape of the cattle 7 substrate) for the N-type base region ^ lower product layer of the layer of the expansion layer surface exposed "face, exposed surface It is formed by the outer circumference of the base type of the base of the base type (in the state of being joined). In the case of '1' mu, the buffer area 4 and the collector area (four) are viewed from the semiconductor substrate. The = of the buffer region 4 is formed in a "shape or strip shape". The strip shape may be formed, for example, in a strip shape or a shape, a lattice shape, a mesh shape or the like as described above. Further, in the buffer region 4, the concentration of the 丄μ,# concentration is higher, and the impurity of the υ region 1 is formed: the collector region 5 is expanded from the lower surface of the buffer region 4 to form a diffusion layer. The expansion 1 is also formed on the side, and the exposed surface of the surface layer is formed in the state of the collector electrode 8). The surface is surrounded by the buffer region 4 (when viewed, the punch is viewed from the lower side of the t-conductor substrate, /, the punched region 4 is overlapped, and is formed to be included in the shape of the two=two portions and the shape is It is formed in a strip shape or a strip shape corresponding to the shape of the buffer region 4. ^ The shape of the collector region 5 may be combined with the shape of the buffer region 4, and may be, for example, an island shape, a lattice shape, a mesh shape, or the like. The domain A and the semiconductor substrate on which the collector region 5 is not formed have an N-type base region 1. The collector electrode 8 is formed on the lower surface of the region conductor substrate, and the buffer region 5 and the N-type base region are electrically connected. It is connected to the above 319310 13 200812080: collector electrode 8. The buffer region 4 and the junction of the collector region 5 and the collector electrode 8 are formed by performing impurity concentration of good low resistance contact. In other words, the buffer region 4 and the collector region 5 are formed by a high impurity concentration (for example, 10% Μ), and the potential of the collector electrode 8 is thinned and formed to have a tunneling effect. Passing the carrier freely to achieve low resistance contact with the collector electrode 8 On the other hand, the impurity concentration of the N-type base region 1 is lower than the impurity concentration of the buffer region 4, for example, 5χ1〇" to 5χ1〇14〇μ_3...隹托=pole 8 bonding, forming a non-resistance contact It is a Schottky electrode 1 所致 caused by Schott “2 5”. That is, at the interface of the N-type base region 1 of the collector electrode 8 , a majority is formed: a 宵 基 block. In the insulating gate type dipole pen crystal according to the first embodiment shown in Fig. 1, the buffer region 4 and the collector region 5 are combined with the collector electrode to form a part. Knowing the first work of the joint - ^. The younger brother 1, the bar edge gate type bipolar transistor and the 隹: "Γ The base region 1 does not form the buffer region 4 and the wood (four): 5 and the collector electrode 8 The portion formed by the bonding functions as the second insulated gate type bipolar transistor of the well-known, and the white, that is, the potential on the side of the collector electrode 8 and the emitter electrode 8 is applied to the emitter. And applying a voltage to be applied to the interpole electrode 7 so as to be equal to or higher than the predetermined threshold voltage. The bipolar electro-crystalline system is in a conducting state, and the electric 319310 14 200812080 is injected into the N-type base region 1. The N-type base region 1 becomes the Schott electrode 8 and the hole is injected into the n-type hole from the collector region 5 Via the buffer region 4, the collector electrode 8 is also opposed to the base barrier electrode 100. Therefore, it is inside the collector pole region 1. < m fruit, conductivity modulation occurs in the N-type base region! An insulated gate type bipolar transistor having a small resistance. That is, the first inter-isopole bipolar electro-crystal system is formed in the p-type collector region 5 connected to the drain electrode 8, and interposed in the episode What is the buffer between the polar region ^ and the N-type base region! In addition, the second insulating gate type bipolar crystal system is formed in the connection portion between the collector electrode 8 and the N-type base 11 region 1 and the Schottky electrode 1A, and is similar to Patent Document 1 The structure in which the first insulating gate transistor and the second insulating gate type bipolar transistor are alternately arranged can realize a characteristic of having a small Vce(sat) and a short starting time when the high temperature operation is performed. Insulated gate type bipolar transistor. Further, in the insulated bipolar transistor of the present embodiment, the N-type base region is formed to be exposed on the lower surface of the semiconductor substrate and connected to the collector electrode 8, and the N-type buffer region 4 is made of an N-type base. The structure surrounded by the pole region ,, and the Schottky electrode 100 is disposed at a position farther from the p-type base region 2 than the buffer region 4 protruding in the N-type base region 1. In the operation of the insulated gate type bipolar transistor, when the reverse voltage is applied to the PN junction formed in the base region 1 and the P-type base region 2, when the insulated gate type transistor is turned off In the state, the depletion layer 319310 15 200812080 extends from the PN junction toward the collector electrode 8. However, in the present embodiment, the shape energy φ, the impurity of the domain 1, the agro-ancient & / the impurity is extended by the impurity concentration ratio than the Ν-type base region portion, and the vacant layer is well suppressed from the above-mentioned bonding pole ΰ ^ lack Arriving at the Schottky electrode 100, that is, the collector "亟8, it is difficult to cause punch-through (to prevent punch-through). Slowly and effectively suppress the punch-through, periodic (intermittent) formation of the i-buffer (^4 compartment (4) The width of the Schottky junction is adjusted and set according to the concentration of the material and the concentration of the N-type base region 1. The voltage between the four electrodes 11 is adjusted and set. It is about 1/2 of the depth of 0, and if the degree of rice is set to 6 (four), then the interval d is set to 3... (Different form of the second division) Gate-type bipolar package body. #2 is a conceptual diagram of a cross-sectional structure of an insulated gate type bipolar electric solar body according to a second embodiment of the present invention. a trench open-cell structure having an insulated interpole transistor, a periodically formed collector region 5 of the features of the present invention, and each collector region The configuration in which the buffer region 4 is interposed between the region 5 and the N-type base region , is the same as that of the first embodiment, and the same reference numerals will be given to the same components, and the description thereof will be omitted. Similarly to the first embodiment, N The base region 1 is an N-type semiconductor region (j-conductor-type semiconductor region) in which a type of impurity is diffused. The P-type base region 2A is on the upper surface of the ν-type base region 1 (one main surface side) a p-type semiconductor region that diffuses P-type impurities and is formed into strips. 319310 200812080 • Domain 0
射極區域3A係在上述P型基極區域2之上面擴散N 型雜質而形成之N型半導體區域。 在上述半導體基板之上面、亦即N型基極區域丨之上 面，以貫通P型基極區域2A及射極區域3A且到達N型 基極區域1之深度形成溝渠（溝槽）9。亦即，上述p型基極 區域2A及射極區域3A係與溝渠9之外周面接合而配置 者0 上述溝渠9之内周面，形成有藉由熱氧化或cvd產 生之矽氧化膜等閘極絕緣膜6A。The emitter region 3A is an N-type semiconductor region formed by diffusing N-type impurities on the P-type base region 2. On the upper surface of the semiconductor substrate, i.e., the N-type base region 丨, a trench (groove) 9 is formed to penetrate the P-type base region 2A and the emitter region 3A and reach the depth of the N-type base region 1. In other words, the p-type base region 2A and the emitter region 3A are joined to the outer peripheral surface of the trench 9, and the inner peripheral surface of the trench 9 is formed with a gate such as a tantalum oxide film by thermal oxidation or cvd. Pole insulating film 6A.
在溝木9内口卩，介插上述閘極絕緣膜6 A 電極7A’且在從該溝渠9露出之閉極電極从上部= C 等形成層間絕緣膜10A。 間絶緣膜1 〇 A、射極區 且電性接合於射極區域 射極電極11A係形成在上述層 域3A及p型基極區域2A上部， 3A及P型基極區域2A。 射極區域3A係形成有到達p型基極區域2八之溝槽 型基極_2A之—部分露出於半導體基板之上 形成於層間絕緣膜似之開孔部W，並與 ^極11A電性連接。因此，p型基極區域以及射極區 或係因射極電極ι1Α而短路，疏 在此，射極區域从係比=型·;It 位:"狀態。 擴散雜質 # '、 土 β區域1更咼濃度地 接人（亦即即藉由低電阻接觸而與射極電極11Α 接口（亦”成低電阻性之接合接點），而形成良好之接合 319310 17 200812080 狀態。 在此，由第2圖可得知，從與半導體基板之面垂直之 方觀看之俯視中，射極區域3A係與p型基極區域2a重 宜’且形成在完全包含於P型基極區域2A之位置，且形 成為深度亦比P型基極區域2A更淺之擴散層，並以除了 與溝渠9及射極電極丨丨a接合之面外必定與p型基極區域 2A接合之方式形成。 再者，同樣地P型基極區域2A係高濃度地擴散雜質 面形成，亦即藉由低電阻接觸西與射極電極UA接合（亦 即形成低屯阻性之接合接點），而形成良好之接合狀態。 p型基極區域2A中，外周緣部22係隔介閘極絕緣膜 6A與閘極電極7A相對向。 與閘極電極7A相對向之P型基極區域2A的外周緣部 22^係成為通道形成區域，在對閘極電極7a施加所設定 之臨限値電壓（threshold vohage)以上之電壓時，在與閘 極絶緣膜6A接合之區域形成有反轉層（通道卜 閘極電極7A與射極電極11A係藉由以pSG(接鱗石夕酸 鹽玻璃）、BPSG(摻麟石夕酸鹽玻璃）或氮化石夕膜等所構成之 層間絕緣膜1 〇 A進行電性絕緣。 、，本第2實施形態之絕緣閘極型雙極電晶體中，係以從 +導體基板之上面側俯視觀看時溝渠9及？型基極區域Μ 形成為帶狀或條狀的情形加以說明。然而，溝渠Up型 二極區域2A之俯視觀看時的形狀並不限定於帶 狀’亦可形成為例如島狀、格子狀、網眼狀等。 ' 319310 18 .200812080 如上所述’本€各日H sv >x月亦可適用在第2圖之第2實施形態 之溝^閘極構造的絕络 抑 表閘極型雙極電晶體。 【圖式間單說明】 弟1圖係本發明箸6 昂1貫施形態之絕緣閘極型電晶體之 剖面構造的概念圖。 第圖係本a月第2實施形態之絕緣閉極型電晶體之 剖面構造的概念圖。 弟3圖係習知你| > έ77 j之、、、巴緣閘極型電晶體之剖面構造的概 心圖0 之絕緣閘極型電晶體之剖面構造 第4圖係其他習知例 的概念圖。 【主要元件符號說明】 I N型基極區域 3、3A 射極區域 5 集極區域 7、7A 閘極電極 9 溝渠 II 11A 射極電極 21、21A開孔部 100 肖特基阻障電極 2、2A P型基極區域 4 缓衝區域 6、6A 閘極絕緣膜 8 集極電極 10、10A層間絕緣膜 !3 溝槽 U、22A外周緣部 319310 19The interlayer insulating film 10A is formed by inserting the gate insulating film 6 A electrode 7A' into the trench electrode 9 and inserting the gate electrode exposed from the trench 9 from the upper portion C or the like. The interlayer insulating film 1 〇 A and the emitter region are electrically connected to the emitter region. The emitter electrode 11A is formed on the upper portion of the layer 3A and the p-type base region 2A, and the 3A and P-type base region 2A. The emitter region 3A is formed with a trench-type base _2A reaching the p-type base region 2, and is partially exposed on the semiconductor substrate to form an opening insulating portion W like the interlayer insulating film, and is electrically connected to the gate electrode 11A. Sexual connection. Therefore, the p-type base region and the emitter region are short-circuited due to the emitter electrode ι1 ,, and the emitter region is the ratio = type·; It bit: " state. The diffusion impurity # ', the soil β region 1 is connected at a higher concentration (that is, the interface with the emitter electrode 11 ( through the low-resistance contact (also forming a low-resistance joint), forming a good joint 319310 17 200812080. Here, as can be seen from Fig. 2, in a plan view perpendicular to the plane of the semiconductor substrate, the emitter region 3A and the p-type base region 2a are both formed and completely contained in a P-type base region 2A is formed as a diffusion layer having a shallower depth than the P-type base region 2A, and is necessarily a p-type base except for a surface bonded to the trench 9 and the emitter electrode 丨丨a In the same manner, the P-type base region 2A is formed by diffusing the impurity surface at a high concentration, that is, by bonding the low-resistance contact west with the emitter electrode UA (that is, forming a low-resistance property). In the p-type base region 2A, the outer peripheral edge portion 22 is opposed to the gate electrode 7A via the gate insulating film 6A. The P-type electrode is opposed to the gate electrode 7A. The outer peripheral edge portion 22 of the base region 2A is a channel forming region, in the pair When the threshold electrode 7a is applied with a voltage equal to or higher than a threshold voltage, a reversal layer is formed in a region bonded to the gate insulating film 6A (the channel gate electrode 7A and the emitter electrode 11A are borrowed). The second embodiment is electrically insulated by an interlayer insulating film 1 〇A composed of pSG (scaled silicate glass), BPSG (doped silicate glass), or a nitride film. In the insulated gate type bipolar transistor, the case where the trench 9 and the ?-type base region Μ are formed in a strip shape or a strip shape when viewed from the upper side of the +conductor substrate will be described. However, the trench Up type II The shape of the pole region 2A in a plan view is not limited to the strip shape ', and may be formed, for example, in an island shape, a lattice shape, a mesh shape, or the like. ' 319310 18 .200812080 As described above, 'this day's H sv > x In the month of the second embodiment, the sinusoidal gate-type bipolar transistor of the trench gate structure of the second embodiment can also be applied. [Illustration of the drawings] The brother 1 is the invention of the present invention. A conceptual diagram of the cross-sectional structure of an insulated gate-type transistor in the form of a pattern. A conceptual diagram of the cross-sectional structure of an insulated closed-pole transistor in the form of a pattern. The brother 3 is a well-known example of the structure of the 剖面77 j,,,,,,,,,,,,,,,,,,, Fig. 4 is a conceptual diagram of other conventional examples. [Main component symbol description] IN type base region 3, 3A emitter region 5 Collector region 7, 7A Gate electrode 9 Ditch II 11A Emitter electrode 21, 21A Opening portion 100 Schottky barrier electrode 2, 2A P-type base region 4 Buffer region 6, 6A Gate insulating film 8 Collector electrode 10, 10A interlayer insulating film! 3 Trench U , 22A outer peripheral part 319310 19