200810024 r^juuui 20883twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體材料層的製造方法，且特 別是有關於一種奈米結晶矽點層的製造方法。 【先前技術】 &利用半導體技術所衍生出來的各式記憶體元件 ，如動 悲隨機存取記憶體（DRAM)、靜態隨機存取記憶體 iSRAM)、非揮發性記憶體（Non-Volatile Memory， NVRAM—)等，在目前的半導體產業中佔了舉足輕重的地 ^ 日益成熟的技術’這些記憶體也被廣泛地應用於 缺的重要電子產品。面已成為生活中不可或 =於半導體世代的不斷打微縮，這 成的功率消耗、碑能pi〆、存取記憶體的漏電流所造 k (FLASHmem〇ry)中讀/ :此，開發新的記憶體元件，其具有高;;=二 14、項/寫速度快及不限讀/寫 ^^山度非揮發 消耗、與現有的CMOS製程相料優點知作電璧、低功率 目前所開發的新的記憶體元件巾， 件備受矚目。奈米點非料性記 何餚存中心。因此，即使在穿隨==作為獨立的電 况下，奈米點非揮發性記憶體仍可^ ^電路徑的情 寺良好的電荷保存 成奈米結晶點。另一種奈 灶曰U )沈積氧化秒，以覆蓋結晶㈣，以使BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor material layer, and more particularly to a method of fabricating a nanocrystalline germanium layer. [Prior Art] & Various memory components derived from semiconductor technology, such as dynamic random access memory (DRAM), static random access memory (iSRAM), non-volatile memory (Non-Volatile Memory) , NVRAM-), etc., occupying a pivotal position in the current semiconductor industry ^ increasingly mature technology 'The memory is also widely used in the lack of important electronic products. Face has become inevitable in life = constant shrinkage in the semiconductor generation, this power consumption, monument can be pi〆, access memory leakage caused by k (FLASHmem〇ry) read /: This, development new Memory component, which has a high;; = two 14, the item / write speed is fast and not limited to read / write ^ ^ mountain non-volatile consumption, and the advantages of the existing CMOS process materials known as electricity, low power current A new memory component towel developed by the company has attracted attention. The nano point is not recorded. Therefore, even in the case of wearing == as an independent power, the nano-point non-volatile memory can still be stored as a nano-crystallization point. Another type of Na(R) U) deposits oxidation seconds to cover the crystal (IV) so that
200810024 .......2〇S83twf.d〇c/e 能力。當尺寸縮小後，奈乎彡士曰 性，將電荷儲存在奈米=心，憶體仍然具有良好特 電荷的效果。現今如# ^麵’崎揮記憶體儲存 屬奈米點之研究1可;;=；：點、錯奈米結晶點以及金 妙儲存電荷層。 錢存電荷層絲代傳統的氮化 習知的-種矽奈米結晶 入的方式將雜入於氧化石夕層之;的=方巧子植 曰 <甲再進订尚溫回火，以 料式會破壞氧切的結構，造成結晶 石夕點之間絕緣的問題。第二種方法中，以高溫氧化法 的乳化魏難完全覆紐㈣點，因此 的 絕緣效果同樣不佳，嚴重影響元件的可靠度/^之門的 【發明内容】 、本發明的目的就是在提供一種奈米結晶點層的製作 方法，其結晶矽點之間的絕緣效果佳，應用於 良好的可靠度。 ^ ^ 本發明提出一種奈米結晶矽點層的製造方法，此方法 是在基底上形成一矽層，此矽層為一個混合結構包括一個 部份結晶矽區域與一個部分非晶矽區域。然後，進行氧化 製程，以使全部的非晶矽區域以及結晶矽區域的表面氧化 成氧化石夕’以形成一含奈米結晶矽點的氧化矽層。 5 20883twf.doc/e 200810024 依照本發明實施例所$，上述在基底上形成石夕層 法包括化學氣相沈積製程。 曰 依照本發明實施例所述，上述化學氣相沈積製程的溫 度為攝氏540度至560度，壓力為〇5托，反應的氣體^ 100sccm-280sccm 的石夕烧。 # 依照本發明實施例所述，上述在進行化學氣相沈 程製程之後，進行氧化製程之前，更包括—回火製程，^ 使些結晶矽區域成長。 < 依照本發明實施例所述，上述回火製程的溫度為 500-600 度。 依照本發明實施例所述，上述回火製程所通入的氣體 包括氮氣。 依照本發明實施例所述，上述回火製程的時 時至5小時。 # 依照本發明實施例所述，上述氧化製 =:，高濃度氣態臭氧或是濃度大於 悲六、氧做為氧化劑。 庆㈣#施順述’上驗態的臭氧的溫度為攝 氏至⑽度；氣態的臭氧的溫度為攝氏5GG至600度。 =本^實施例所述，上述在形射層 在基底上形成一第一介電層。 層上形成一第二介電 更勺mr月實施例所述，上述在進行氧化製程之後， 巴括在含示米結晶砍點的氧化秒 層0 6 200810024 -------20883twf.doc/e 依照本發明實施例所述，上述奈米結晶石夕點層為— 揮發性記憶元件之電荷儲存層。 θ .、非 由於奈米結晶矽點表面上的氧化矽，是由原來的择曰 矽區域表面氧化而成，因此，氧化矽與奈米結晶矽點=曰曰 的覆蓋性良好。此外，奈米結晶矽點並不是經過離子植$ 方式形成，而是以沈積方式形成，因此，奈米結晶矽點 間的氧化矽不會遭受破壞，故，奈米結晶矽點之 ^ 效果非常好。 』]、、、巴、、彖 “為讓本發明之上述和其他目的、特徵和優點能更明 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細二 明如下。 u / 口 【實施方式】 圖1Α至1C繪示本發明實補之—種含有奈米結晶石夕 點層之製造方法的流程剖面圖。請參照圖1Α，在一 電層102的基底1〇〇上形成一石夕層刚，此石夕層^包^ -部分結晶梦區域1〇4與一部分非晶秒區域1〇6。砍層⑽ 的沈f方法包括化學氣相沈積製程。在-實施例中，石夕層 1〇8疋以化子氣相沈積製程形成，其製程溫度為攝氏㈣ 度至56〇度，壓力為〇.5托，反應的氣體為職__2術_ 的石夕烧。在進行化學氣相沈積縣之後，可以先進行一回 日日石夕區域1()4成長。回火製程所通入的氣 體2 3鼠軋體如氮氣；回火的溫度為攝氏500-600度； 回火製程的時間為3小時至5小時。 請參照圖IB，i隹;^ xu ^ . ^ ,, a ^ 進仃一虱化製程，藉由非晶矽氧化速 率快而結㈣統速率慢的特性，使全部的非晶石夕區域 7 200810024 x^^v/v/vi 20883twf.doc/e 106氧化成氧化矽i〇6a ;並且使結晶矽區域1〇4的表面氧 化成氧化矽104a ;而未被氧化的結晶矽區域1〇4形成奈米 結晶矽點l〇4b，以完成奈米結晶矽點層1〇8a的製作。^ 化製程可以採用高濃度的氣態的臭氧(濃度範圍 =〇%)或是液態的臭氧(濃度大於17mg/L)做為氧化劑。液 態的臭氧的溫㈣攝氏5G至8G度；氣態的臭氧的溫/ 攝氏500至600度 又為 睛芩照圖1A，在一實施例中，實際在應用 =二 108=在形成上_應之前可以在t 之後，|^:=層1G2’並且在形成奈米結晶雜層108a 後更匕括在奈米結晶矽點層10如覆 110，以構成一谁晶έ士娃智，1¾層 之材質ΓΛ" 如圖1c所示。介電層搬 楊疋喊’形成的方法例如是熱氧化法，厚产 例如疋40埃至50埃。介⑽ 子又 之材質相同或不相冋θ 刊貝層102 化與例如是氧切，形成的方法例如是 化予乳相沈積法，厚度例如是40埃至50埃。 荷儲做為轉發性記K牛之電 應用於SONOS元件二’、：2 ’上述气米結晶矽點層可以 物層，做為控制閘3〇6 ^取代傳統氧化物/氮化物/氧化 由於太来社曰^基底300之間的電荷儲存層304。 石夕點之間的覆蓋而成’因此’氧化賴奈米結晶 離子植入方式來成又 此外，奈米結晶矽點並不是經過 晶矽點之‘氧化矽沈積方式形成，因此’奈米結 不㈢梃叉破壞，故，奈米結晶矽點之 8 200810024 r^uuoi 20883twf.doc/e 非常好，應用於非揮發性記憶元件時’具有 …雖然本發明已以較佳實施例揭露如上，然其並非用以 本發明，任何熟習此技藝者，在不脫離本發明之精神 二靶圍内，當可作些許之更動與潤飾，因此本發明之保譁 幸:圍當視後附之申請專利範圍所界定者為準。 又 【圖式簡單說明】200810024 .......2〇S83twf.d〇c/e Ability. When the size is reduced, it is a gentleman's sex, and the charge is stored in the nano=heart, and the memory still has a good special charge effect. Nowadays, as a #^面's swaying memory storage, it is a study of nano-points;; =;: point, stupid crystallization point, and gold storage charge layer. The deposit of the charge layer is the traditional nitriding of the traditional nitriding - the way of crystallization of the glutinous rice will be mixed into the oxidized stone layer; the = 巧巧子曰 曰 甲 进 进 进 尚 尚 尚 尚 尚 尚The formula will destroy the structure of the oxygen cut, causing the problem of insulation between the crystallized stone points. In the second method, the emulsification of the high-temperature oxidation method is completely difficult to cover the new (four) points, so the insulation effect is also poor, and the reliability of the component is seriously affected. [Invention content], the object of the present invention is The invention provides a method for preparing a nano crystal point layer, which has good insulation effect between crystal defects and is applied to good reliability. The present invention proposes a method for fabricating a nanocrystalline germanium layer by forming a layer of germanium on a substrate, the layer being a mixed structure comprising a partially crystalline germanium region and a partially amorphous germanium region. Then, an oxidation process is performed to oxidize all of the amorphous germanium regions and the surface of the crystalline germanium regions to oxidized oxides to form a hafnium oxide layer containing nanocrystalline crystal defects. 5 20883 twf.doc/e 200810024 In accordance with an embodiment of the present invention, the above-described method of forming a layer on a substrate includes a chemical vapor deposition process.依照 According to an embodiment of the invention, the temperature of the chemical vapor deposition process is 540 to 560 degrees Celsius, the pressure is 〇5 Torr, and the reaction gas is 100 sccm-280 sccm. According to the embodiment of the present invention, after performing the chemical vapor deposition process, before the oxidation process, the tempering process is further included, and the crystallization regions are grown. < In accordance with an embodiment of the present invention, the temperature of the tempering process is 500-600 degrees. According to an embodiment of the invention, the gas introduced by the tempering process includes nitrogen. According to an embodiment of the invention, the tempering process is for a period of up to 5 hours. # According to the embodiment of the present invention, the above oxidation system =:, high concentration of gaseous ozone or concentration is greater than sorrow, oxygen as an oxidant. Qing (4) #施顺述' The temperature of the ozone in the upper test state is Celsius to (10) degrees; the temperature of the gaseous ozone is 5GG to 600 degrees Celsius. In the embodiment, the first dielectric layer is formed on the substrate in the forming layer. Forming a second dielectric and a spoonful of mr month on the layer, after the oxidation process is performed, the oxidized second layer including the crystallization point of the rice is etched. 0 6 200810024 -------20883 twf.doc /e According to an embodiment of the invention, the nanocrystalline stone layer is a charge storage layer of a volatile memory element. θ., 非 由于 由于 由于 由于 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈 奈In addition, the nanocrystalline crystallization point is not formed by the ion implantation method, but is formed by deposition. Therefore, the yttrium oxide between the nanocrystal crystallization points is not damaged, so the effect of the nano crystallization 矽 point is very it is good. The above and other objects, features, and advantages of the present invention will become more apparent and understood. u / PORT [Embodiment] Figs. 1A to 1C are cross-sectional views showing a method of manufacturing a nanocrystalline crystal layer of the present invention. Referring to Fig. 1, a substrate 1 of an electric layer 102 A stone layer is formed on the raft, and the stone layer is covered with a part of the crystal dream area 1〇4 and a part of the amorphous second area 1〇6. The method of the layered layer (10) includes a chemical vapor deposition process. In the example, the 夕 层 layer is formed by a chemical vapor deposition process, and the process temperature is from Celsius (four) degrees to 56 〇 degrees, the pressure is 〇. 5 Torr, and the reaction gas is shi _ _ _ After the chemical vapor deposition county, you can first carry out the growth of the day and night stone area 1 () 4. The gas introduced into the tempering process is a nitrogen-rolled body such as nitrogen; the temperature of the tempering is 500 ° C. -600 degrees; tempering process time is 3 hours to 5 hours. Please refer to Figure IB, i隹;^ xu ^ . ^ ,, a ^ The process is characterized in that the oxidation rate of the amorphous bismuth is fast and the rate of the junction (four) is slow, so that all of the amorphous ceramsite region 7 200810024 x^^v/v/vi 20883 twf.doc/e 106 is oxidized to cerium oxide 〇i〇6a. And oxidizing the surface of the crystalline germanium region 1〇4 to cerium oxide 104a; and the unoxidized crystalline germanium region 1〇4 forms a nanocrystalline crystalline germanium point l〇4b to complete the nanocrystalline crystalline germanium layer 1〇8a Production process can use high concentration of gaseous ozone (concentration range = 〇%) or liquid ozone (concentration greater than 17mg / L) as oxidant. Liquid ozone temperature (four) Celsius 5G to 8G degrees; gaseous The temperature of ozone / 500 to 600 degrees Celsius is again in view of Figure 1A. In an embodiment, the actual application = two 108 = before formation _ should be after t, |^: = layer 1G2' and After forming the nanocrystalline layer 108a, it is further included in the nanocrystalline layer 10, such as the covering 110, to form a crystal έ 娃 娃 13, 13⁄4 layer material ΓΛ " as shown in Figure 1c. Dielectric layer moving Yang The method of screaming 'formation is, for example, thermal oxidation, and the yield is, for example, 40 Å to 50 angstroms. The material of (10) is the same or not θ The shell layer 102 is formed, for example, by oxygen cutting, and is formed by, for example, a milk phase deposition method having a thickness of, for example, 40 angstroms to 50 angstroms. The charge reservoir is used as a forwarding property for the application of the power of the K cattle to the SONOS component 2', 2 'The above-mentioned gas-crystal crystallization point layer can be a layer of material, as a control gate 3〇6 ^ replaces the traditional oxide/nitride/oxidation due to the charge storage layer 304 between the Tailai community and the substrate 300. The coverage between the 'and therefore' oxidized Reiner crystal ion implantation method is furthermore, the nanocrystalline crystallization point is not formed by the yttrium oxide deposition method of the crystal enthalpy point, so the 'nano junction is not (three) frog Destruction, therefore, the nanocrystal crystallization point 8 200810024 r^uuoi 20883twf.doc / e very good, when applied to non-volatile memory elements 'has... although the invention has been disclosed in the preferred embodiment above, but it is not used In the present invention, any skilled person skilled in the art can make some modifications and retouchings without departing from the spirit of the present invention. Therefore, the present invention is protected by the scope of the patent application. Subject to it. Also [Simple diagram description]
制^至lc繪示本發明實施例之—種含有奈米結晶句 點層之製造方法的流程剖面圖。 日日少 圖2本叙明之含有奈米結 r〇s元件之氡化物，物層二;構二 【主要元件符號說明】 100、300 :基底 102、11〇 :介電層 104 :結晶石夕區域 l〇4a、l〇6a :氧化石夕 104b ··奈米結晶石夕點 106 ·非晶妙區域 108 :矽層 .l〇8a:奈米結晶矽點層 120 :堆疊結構 302 : SONOS 元件 3〇4 :電荷儲存層 306 :控制閘 9The method of the present invention is a cross-sectional view showing a method of manufacturing a nanocrystal layer layer according to an embodiment of the present invention. Figure 2 shows the telluride containing the nano-junction r〇s element, the second layer; the second structure [the main component symbol description] 100, 300: substrate 102, 11 〇: dielectric layer 104: crystalline stone eve Region l〇4a, l〇6a: oxidized stone eve 104b · nanocrystal crystallization point 106 · amorphous region 108: 矽 layer. l 〇 8a: nano crystallization 矽 point layer 120: stacked structure 302: SONOS element 3〇4: charge storage layer 306: control gate 9