TW200809628A - Power aware dynamic scheduling in multiprocessor system employing voltage islands - Google Patents

Abstract

Minimizing the overall power conservation in a symmetric multiprocessor system disposed in a system-on-chip (SoC) depends on using voltage islands operated at different voltages such that similar circuits will perform at significantly different levels because of the voltage differences. Otherwise identical processor cores of a symmetric multiprocessor system are placed in various ones of the voltage islands such that they consume differing operating powers because of the voltage differences. The slack-time experienced by each of a variety of tasks during execution by the processor cores is calculated and tabulated. Thereafter, each task is scheduled for a particular processor core according to its performance level as determined by its operating voltage, and depending on the corresponding slack-time calculation for the task. Such scheduling will minimize power consumption by selecting a minimum power processor core, and still allow for complete execution in the time available.

Description

200809628 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a symmetric multiprocessor system constructed by means of a voltage island' and more specifically to the performance and estimation of an execution state by means of measurement A method and circuit that adapts to changing application workloads to save system-on-a-chip (SoC) power consumption. [Prior Art]

Symmetric Multiprocessing (SMP) connects the same processor to a single shared primary memory. Most common multiprocessor systems today use a first-read architecture. Can be assigned to - task-to-processor execution, because the data of the task is in shared memory. The HSMp operating system can move tasks between processors to efficiently balance the implementation of the workload. The eve of the individual processing $ may be urgently needed data 'this is because the memory is usually much slower than accessing each processor of the memory. SMP has many applications in the scientific, industrial, and commercial fields of soft-threaded customization (4) in multi-thread processing. However, paper processing benefits, computer games and most other consumer products are not written in a way that can be profitable from SMP. Programs executed on the SMp system can perform better even when the basin has been written for a single-processing H system. ..., hardware interrupts usually suspend program execution, while in a read system, the core is the parent to hand out the 箸 赫 赫 涵 / interrupt to θ generation to execute - idle processor scatter operating system (os) Support, such as the software compiler and the number of sub-processes (four) and (four) external processors are set to double the length of the increase. 115716.doc 200809628 When dealing with a lot of work in an SMP environment, it can lead to a loss of hardware efficiency. Software programs have been developed to schedule work in a variety of ways to optimize processor utilization. When the right is clocked at a higher rate, a given processor can generally improve its efficiency. The most accurate timing rate is defined by semiconductor technology and operating voltage. For a given operating voltage and semiconductor technology, there will be a maximum clock rate. If the operating voltage is increased, the clock can be scaled up to increase efficiency within practical limits. However, power consumption will increase as the square of the voltage increases. This results in increased performance at the expense of a greatly increased power consumption. The prior art has used dynamic voltage scheduling based on the task execution state of offline computing. Preferably, an energy measurement and estimation unit is used to analyze the execution status during the execution period. In this way, the system can automatically adapt to the application of the application only. The static mapping of these tasks to a single I processor is also undesirable. Estimated execution based on a set of symmetric multiprocessors • Time to dynamically schedule tasks to these symmetric multiprocessors. Advanced technology also handles scheduling tasks to a processor that supports different voltages, thereby maintaining power consumption as a function of cost. However, such processing does not use DVS on a transaction basis. Such conventional devices are classified by the deadline. The task is placed in the reserved list of target processing elements Μ #With the highest and lowest voltage levels supported by the target processing element, the slack time of the task = two. Calculate the task between the highest and lowest voltages. Find out the voltage level at which the task can meet the deadline for the target processing component. The DVS is then used to change its voltage level and schedule the task onto it. Those in need are systems in which different cores of one SoC have different power supply voltages. The voltage island optimizes the core level power of the SoC design by using a single supply voltage for each core. Therefore, in an SoC with the same core and voltage island, all tasks can be kept on a list. Analyze its performance requirements for each task. Subsequently, a particular processor whose power supply voltage is sufficient to ensure the performance requirements of the task is selected to perform the task. Second, the task is analyzed again and the same task can be mapped to a different processor with different supply voltages that guarantee its performance requirements. SUMMARY OF THE INVENTION Briefly, a symmetric multiprocessor system with voltage islands includes dynamic scheduling of application tasks on available processors. The voltage island enables each processor to be supplied with a different independent operating voltage and a corresponding maximum clock frequency. The difference between the available and actual processor task execution times can be estimated to estimate the relaxation time of the recurrence of the ten tasks. The processing power of each processor is cataloged according to the specific operating voltage and frequency. - The dynamic scheduler selects the appropriate processor and voltage island settings based on the apparent processor. This will result in the best power consumption. The present month t U provides an SoC implementation of a symmetric multiprocessor system that will conserve power. Another advantage of this month is to provide a symmetric multiprocessor system that uses voltage islands to avoid the immediate overhead associated with power control. 115716.doc 200809628 Still another advantage of the present invention is that the basis is - (iv) time Calculate the write schedule: the s〇c implementation of the symmetric multiprocessor system. Under the specific conditions of the invention, the details of the invention will be clarified. Gossip, ', and mouth are to understand the above and further goals, features and advantages of this & [Embodiment] One embodiment of a symmetric multiprocessor system of back and 曰本毛明, and

This article: Refers to the general reference number (10). The symmetrical multiprocessor system 100 includes a plurality of voltage islands m 04 placed in a common semiconductor wafer 106. The voltage islands provide three different operating voltages: hi, mid, and 1 电压. A plurality of identical processor cores are respectively disposed in the voltage islands 1〇2_1〇4. 108 11 〇, but these different operating voltages result in processor cores 1 〇 8 having relatively high performance (hi-MIPS), processor cores 1 〇 9 with moderate performance (nnd-MIPS), and processor cores 11 〇 relative Low performance (i〇_Mips). All two processor cores 108-110 have access to a shared memory 112, respectively. Since all three processor cores 108·110 operate at different voltage levels, their respective power consumptions are also different. Power consumption will increase as the square of the voltage increases. For example, ^ = ^. Thus, increased performance is achieved, for example, in processor core 108 at the expense of greatly increased power consumption κ. In modern portable battery-operated devices, all waste of power consumption must be strictly eliminated. An operating system (〇S) 14 provides a selection of specific software tasks 116-120 to be executed by different cores of processor cores 108-110. A relaxation time meter 115716.doc 200809628 The calculator m is connected to compare the time it takes for an assigned task U6_120 to execute on a corresponding processor core 108-11. A processing capability and task loading table 124 is constructed based on the data obtained by the slack time calculator 122. It catalogs the processing power of each of the processor cores 108-110. Enter a measure of the processing load applied to the previously executed task. During the operation, the performance required for a "task" can be tabulated in the form of a million instructions per second (]^11>8) in Table 124. For example, the tentative evidence can be gathered to show "task_d&quot A medium MIPS performance is required. The second chart can be indexed to show that "CPU-2" will be used for the appropriate selection of scheduling tasks _d. A message is sent from the form 124 to the scheduler 126 to be dispatched to the processor core 109 when the ss 114 wants to perform the task -d 119. After the task is executed, the slack time calculator 122 can again verify that the system is a good choice. By avoiding the higher power consumption processor core 108, power is saved by using an alternative processor core with lower power. Different supply voltages are provided for different processor cores of the SoC. The voltage island is optimized by providing a single fixed supply voltage for the mother-processor core to achieve the s〇c design. Has a voltage island and the same processor core. The SoC Valley allows all tasks to be maintained in a single list that can be applied to all of them. Prior art devices prepare separate task lists for each processor core. Each task is evaluated according to its performance requirements. Depending on the ground, the tasks are matched to a specific processor that is capable of re-analysing the task and dynamically revising the task itself when the task itself is completed within the allocated time frame because its power supply is high enough. The ground will be 115716.doc -10- 200809628 eight schedules, " the most appropriate processor core. Dynamic scheduling is implemented in this way. DVS technology has the potential to be too expensive to use on a task-by-task basis. The symmetrical multiprocessor system 100 instead selects a processor core whose power supply voltage can produce the necessary performance level within the time window. The slack time calculator and processing power and task loading table 124 provides effects and estimates to capture the execution time of the task in an application software. Effective energy measurements can be accumulated based on tracking or self-execution time and the deadlines for each task. The average/intermediate value of the relaxation time is calculated, and a plurality of relaxation time values within a certain time window are used to characterize each gas and relaxation time of each task. Thereafter, the characterization information is used to predict a future execution and the relaxation time of the task, thereby dynamically scheduling the task to the appropriate processor. The task has been rescheduled on a different processor core, the relaxation time calculator The processing capabilities and task loading tables further provide measurement information reset for such tasks. 2 depicts an embodiment of a symmetric multiprocessor system of the present invention that allows each voltage island to be adjusted by means of DVS and is referred to herein by the general reference numeral 200. The symmetric multiprocessor system 2 includes a plurality of voltage islands 2〇2_204 disposed in a common semiconductor wafer 206. These provide independent and controllable dynamic electrical compression (DVS) for each voltage island. Dynamic voltage scaling (DVS) has become a common way to adjust the operating voltage and clock to balance the performance of a circuit with its accompanying power consumption. Voltage islands have been used in conventional designs to allow multiple portions of a wafer to undergo independent DVS control. However, after DVS has changed to a new value, the settling time can be 115716.doc •11- 200809628 up to 200 home seconds. Therefore, the best case is that the DVS setting should not be changed very frequently, or not changed at all after initialization.

A plurality of processor cores 208-210 each have access to a shared memory 212. The parent-processor cores are each placed in one of the voltage island counterparts such that changes in the DVS will proportionally affect the performance and power consumption of each processor core. An operating system (〇8) 214 provides a selection of specific software tasks 216_22 to be executed by different cores of the processor cores 208-210. A relaxation time calculator 222 is coupled to compare the time taken by the assigned tasks 216-220 to execute on a corresponding processor core 2〇8_21〇 with a particular set value. A processing capability and task loading table 224 is constructed based on the information obtained by the relaxation time calculator 222. It catalogs the processing power of each of the processor cores 208-210 with a multi-Dvs setting. Input – A measure of the processing load imposed on a previously performed task. The OS 214 controls a scheduler 226. The scheduler looks for one of the items in the processing capability and task loading table 224 for each new task to be scheduled. If the task has been previously characterized, scheduler 226 sends the task to an appropriate, available processor core 2〇8_21(). A DVS control is issued for the corresponding voltage island - a value that will minimize power consumption and is still fully executed at the available time. A dynamic schedule assigns application tasks to processors on a symmetric multiprocessor system that can be isolated by a voltage island. Different independent (four) frequencies are provided for each of the processors. The relaxation time is measured by the time difference between the final period of the task and the actual execution time. Place the 115716.doc -12- 200809628 ^ time in the -Application Tasks chart. The measurement will track the future of the mission. Statically maintaining the processing schedules of the various processors is primarily based on the loose time of the tasks ‘, , 〜* & select the appropriate processor to produce the optimal power consumption.

The processing capability table indicates the performance of the MIPS bit provided by each processor. MIPS, which is supplied by each step and at 1 棱, depends on the processing of the processing; the drum frequency is operated. This can be estimated by looking at the voltage source of the processor. The table is statically configured with the desired performance. It can also account for the average relaxation time of each task by making several observations that are being made. The dynamic scheduler uses static estimates and analysis results ((4) cents (10) also maps tasks to available processors. Its self-efficient energy measurement and estimation unit obtains the loose information of the money application task. Considering mapping to the first task on the first processor, if the first task on the first processor measures the time to deviate from the average loose time, the first task can be dynamically scheduled. On the second processor with the I requirement. The mapping of tasks to other processors is based on a processing capability table lookup. The embodiment of the present invention is such that the task assignment to an available processor assumes that the processor is symmetric but uses different supply voltages that enable the processor to provide different throughputs. The task schedule is based on the task's I. Using power islands and dynamically scheduling these tasks based on their estimated performance requirements or slack cycles can provide significant power savings. While the specific embodiments of the invention have been illustrated and described herein, the embodiments are not intended to limit the invention. Various modifications and variations will be apparent to those skilled in the art, and the invention is intended to be limited only by the scope of the scope of the patent application of the Japanese Patent Application No. H5716.doc 13-200809628. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a "single implementation, two-force I block diagram" of a symmetric multiprocessor system embodiment of the present invention, wherein the symmetric multi-processing system uses a fixed voltage island to provide power to the processor core. Choose; and

Each Figure 2 is a functional block diagram of another SoC embodiment of the symmetry ❹ processor system embodiment of the present invention, wherein the symmetrical multiprocessor system provides DVS control for the voltage islands.

[Major component symbol description] 100 Symmetric multiprocessor system 102 Voltage island 103 Voltage island 104 Voltage island 106 Semiconductor wafer 108 Processor core 109 Processor core 110 Processor core 112 Shared memory 114 Operating system (OS) 116 Software task 117 Software Tasks 118 Software Tasks 119 Software Tasks 120 Software Tasks 115716.doc -14- 200809628 122 Relaxation Time Calculator 124 Processing Capabilities and Task Load Table 126 Scheduler 200 202 203 204 206 208 209 210 212 214 216 217 218 219 220 222 224 226

Symmetric multiprocessor system voltage island voltage island voltage island semiconductor chip processor core processor core processor core shared memory operating system (OS) software task software task software task software task software task relaxation time calculator processing capability and task Into the table scheduler 115716.doc -15-

Claims (1)

200809628 X. Patent Application Scope: A multiprocessor system comprising: a plurality of voltage islands disposed in a total of μ cattle conductor wafers and providing different independent operating voltages in each voltage island · a plurality of processor cores, Having access to the shared memory, and each of them is placed in a corresponding one of the voltage islands such that the current operating voltage difference proportionally affects the performance and consumption of each processor core; a loose time calculator that is connected to compare the time taken by the __ assigned task to execute on a corresponding processor core; - processing capability and task loading table for use by the time calculator The acquired data is constructed to catalog the processing capabilities of each of the processor cores, and the associated metrics of the processing loads imposed by the tasks performed prior to the execution; and the drainer , which is connected to check the _project in the process, force and task manned form under a schedule, and if the task has been previously confined, scheduling it to one will minimize power consumption And still allows the processor core to be fully executed within this available time. 2. A system as claimed, further comprising: an operating system (OS) that provides a selection of a particular software task to be executed by a different one of the processor cores and is coupled to the scheduler to allow Schedule tasks to the selected processor core. 3. The system of claim 1, wherein: the relaxation time calculator and the processing capability and the task loading form provide the effect 115716.doc 200809628 Energy measurement and estimation to capture the execution time of the task in the application software. For example, in the system of claim 3, where the relaxation time calculator and the processing capability and the task loading form provide an effect-energy measurement, the equivalent energy measurement or the tracking time or the execution time of each task and The deadlines are cumulative, and wherein the average/intermediate values of the relaxation time are calculated, and a plurality of relaxation times in a time window are used to characterize each relaxation time of each task, and The characterized information is then used to predict the future execution and slack time of the task, thereby dynamically scheduling the tasks to the appropriate processors. 5. The system of claim 4, wherein: the relaxation time calculator and processing capability and task loading form provide the measurement information for the task when a task is rescheduled to a different processor core reset. 6. A symmetric multiprocessor system, comprising: a plurality of voltage islands disposed in a common semiconductor wafer and providing independent and controllable dynamic voltage scaling (Dvs) for each voltage island; a plurality of processors a core having access to a shared memory and respectively disposed in a respective one of the voltage islands such that the change in the Dvs proportionally affects the performance and power consumption of each processor core. An system (OS) that provides for selection of specific software tasks to be performed by different cores of the processor cores; a relaxation time calculator coupled to compare an assigned task to a particular DVS setting for a corresponding processing The time spent on the execution of the core is 115716.doc 200809628; - processing capability and task loading table, which is used to construct according to the data obtained by the relaxation time FaUt#l1, read with various DVS settings and by the first The relevant amount of processing load imposed by the task of the task 胄(7)4, etc., of each processing capability of the processor core, cataloging; and the squirrel, the connection Up to the 〇s, the 〇s detect the next scheduled _ continuation task in the processing capability and one of the tasks loading table, and if the task has been previously characterized, the task is scheduled to - The processor core and the DVS of its voltage island are set to values that will minimize power consumption and still allow full execution within the available time. 7. A method of total power savings in a multi-processor system disposed in a system on a wafer (s〇c), comprising: operating a plurality of voltage islands placed in a s〇c at different voltages, Having similar circuits operate at significantly different levels due to such voltage differences; • The same processor core of a multi-processor system is placed in a different one of the plurality of voltage islands to cause it to operate due to its operating voltage difference Compensating for different operating powers; calculating the slack time experienced by each of the plurality of tasks performed by the processor cores and tabulating them; and ^, M determining the performance level of the task's operating voltage And depending on the 'correspondence (four) time calculation of the task, each task is scheduled to two specific processor cores, wherein the schedule causes the power consumption to be minimized and still allows full execution in an available time. 115716.doc