CN105930289A - Multi-core processor system, allocation program, control program, allocation method, and control method - Google Patents
Multi-core processor system, allocation program, control program, allocation method, and control method Download PDFInfo
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- CN105930289A CN105930289A CN201610236777.7A CN201610236777A CN105930289A CN 105930289 A CN105930289 A CN 105930289A CN 201610236777 A CN201610236777 A CN 201610236777A CN 105930289 A CN105930289 A CN 105930289A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5033—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering data affinity
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Abstract
A CPU#0 detects an allocation instruction of a process 1. The CPU#0 obtains residual time, wherein the residual time is time obtained by subtracting time (Dt of a handle) from a generation moment of an event of the handle B, which is allocated to a CPU#1 and that is interrupted, to an execution deadline of the handle B by processing time of a handle A (i.e. CP of the handle B). The CPU#0 determines whether the obtained residual time is over processing time (CP of a process 1) of processing which is defined as interrupt disability of the process 1. That is, when the process 1 is allocated to the CPU#1, even if the event of the handle B is generated during execution of the process 1, whether the Dt of the handle B can be complied with is determined. If the event of the handle B is generated during execution of the process 1, it is determined that the Dt of the handle B can be complied with. Therefore, the CPU#0 allocates the process 1 to the CPU#1.
Description
The application be national applications number be 201080068231.6, enter the National Phase in China date be
On January 24th, 2013, invention entitled " multi-core processor system, distribution program, control journey
Sequence, distribution method and control method " the divisional application of application for a patent for invention.
Technical field
The present invention relates to the polycaryon processor system that course allocation or driver distribution are controlled
System, distribution program and distribution method.And, the present invention relates to the clock supplied to processor
The frequency multi-core processor system, control program and the control method that are controlled.
Background technology
Pass through for the interrupt signal from equipment in computer systems conventionally, there is known a kind of,
Make the process being carrying out by CPU (Central Processing Unit) keep out of the way, carry out for
The interrupt processing of interrupt signal, is carried out at high speed the technology of the process corresponding with equipment.Will be with equipment
Corresponding process is referred to as device driver, as the action of device driver, exists: with 1
One action type driver that secondary interrupt signal finishes and when producing 1 interrupt signal with necessarily
Time intervals etc. continuously generate the continuous action type driver of interrupt signal.
The driver of one action type, for the register set operation of equipment, is altered to software friendly
The interface of (software friendly).The driver of one action type is for example adapted for keyboard and drives
Dynamic program, mouse driver etc..The driver of continuous action type is by for utilizing FIFO
The shortage of the buffer that (First In, First Out) is managed and the interruption of buffer full state
Signal carries out DMA (Direct Memory Access) and sets, and carries out data transmission.Continuously
The driver of action type is for example adapted for display driver, camera driver etc..
In the driver of continuous action type, according to the mark of the object data transmitted as data
Standard, the situation that there is time deadline date (deadline time) is more.Such as, display
Driver has in the case of display updates with 60 [Hz], as time deadline date about
This standard of data is transmitted within 0.017 [second].
If as a example by camera driver, then camera apparatus is installed in end as input unit
End, is stored in row buffering by a line a line from the input data of camera apparatus while shooting
Device (line buffer).When line buffer becomes the 1/2 of the capacity of this line buffer, produce
Interrupt processing, the data stored in this line buffer, for image procossing or compression, are used DMA
(Direct Memory Access) transmits to shared memory.
It addition, in single core processor system, it is known to based on multiple processes by a CPU
The process time switches the technology (referring for example to following patent document 1) of the execution of this process.
It addition, in multi-core processor system, the distribution of each driver is determined when this system start
Fixed.The most known have a kind of by using special as driver for a CPU in polycaryon processor
CPU, even if realizing producing interrupt processing also to be able to not make process keep out of the way and the skill that performs
Art is (referring for example to following patent document 2.).
Patent document 1: Japanese Unexamined Patent Publication 2005-285093 publication
Patent document 2: Japanese Unexamined Patent Publication 4-33130 publication
But, sometimes have in process and be defined the process forbidding interrupting.It is defined performing this
Forbid that, in the processing procedure interrupted, even if producing the interrupt processing of driver, this interrupt processing is also
It is not performed immediately.It is as noted previously, as the driver of continuous action type when there is the deadline date
Between, if so to be defined the process time of process forbidding interrupting longer than this time deadline date,
Then there is the problem that the driver of continuous action type can not observe time deadline date.
Such as, camera driver described above is such, if can not observe to shared memory
Time deadline date of function of the data of transmission line buffer, then owing to losing and can not transmit
Data, so causing the shortage of data of the image of shooting so that image thickens.
As it has been described above, in multi-core processor system, by the CPU that configuration driver is special,
Will not overlap with the process forbidding interrupting that is defined of process.But, when in process specific
CPU starts multiple process, and the CPU not utilizing driver special performs any driving
During program, there is the problem that load concentrates merely on the CPU of process specific.
Summary of the invention
In order to eliminate above-mentioned problem of the prior art point, it is an object of the invention to, it is provided that Neng Gouzun
Keep time deadline date of driver and distribute the multinuclear process of process to the CPU having surplus energy
Device system, distribution program and distribution method.
A viewpoint according to the present invention, it is provided that following multi-core processor system, distribution program with
And distribution method, wherein, the distribution instruction to process detects, when detecting above-mentioned process
During distribution instruction, obtaining residual time, this residual time is to core arbitrary polycaryon processor
The heart distribution interrupt processing recall the time to the Deadline of above-mentioned interrupt processing in the moment
In deducted time processing the time of above-mentioned interrupt processing, and judge that the residual time that obtains is whether
For above-mentioned process be defined forbid interrupt process the process time more than, be judged as above-mentioned
When residual time is the process time being defined the process forbidding interruption of above-mentioned process more than, to
Above-mentioned any core distributes above-mentioned process.
Other viewpoints according to the present invention, it is provided that following multi-core processor system, distribution program with
And distribution method, wherein, by the time that performs of object interrupt processing and in polycaryon processor
The arbitrarily execution time of the interrupt processing being assigned of core distribution is added, and comes based on addition results
Judge above-mentioned any core whether can observe from above-mentioned object interrupt processing recall execution
Time limit and from the above-mentioned interrupt processing being assigned recall Deadline, be judged as
Can observe from above-mentioned object interrupt processing recall Deadline and distribute from above-mentioned
During the Deadline that the interrupt processing finished rises when recalling, distribute in above-mentioned object to above-mentioned any core
Disconnected process.
Other viewpoints according to the present invention, it is provided that following multi-core processor system, control program with
And control method, wherein, to any core distributed in polycaryon processor be assigned enter
The end of journey detects, at the end of detecting the above-mentioned process being assigned, it may be judged whether
Do not distribute any process to above-mentioned any core, be judged as not to the distribution of above-mentioned any core
During any process, obtaining residual time, this residual time is from distribute above-mentioned any core
Disconnected recalling in the time to the Deadline of above-mentioned interrupt processing in the moment of process has deducted
Time after the process time stating interrupt processing, according to the residual time obtained by above-mentioned acquisition unit
With the ratio processing the time of above-mentioned interrupt processing, determine the clock to the supply of above-mentioned any core
Frequency, and determination result is given to the supply source of above-mentioned clock.
According to this multi-core processor system, distribution program and distribution method, play and process can be divided
Dispensing can observe this effect of CPU of time deadline date of driver.It addition, according to
This multi-core processor system, distribution program and distribution method, recall multiple driving journey even if playing
Sequence, it is also possible in accordance with this effect of time deadline date of each driver.It addition, it is many according to basis
Core processor system, control program and control method, play and can observe each driver
Rear deadline time and this effect of low consumption electric power can be realized.
Accompanying drawing explanation
Fig. 1 is the explanatory diagram of the example representing the present invention.
Fig. 2 is the explanatory diagram of another example representing the present invention.
Fig. 3 is the explanatory diagram of the example representing ESL model.
Fig. 4 is the block diagram of the hardware representing the Design assistant device involved by embodiment 1.
Fig. 5 is the explanatory diagram representing ESL simulation example.
Fig. 6 is the explanatory diagram of the output example of CP and Dt representing driver.
Fig. 7 is the explanatory diagram of the output example of the CP representing process.
Fig. 8 is the calculating of the CP memory Dt representing the driver carried out by Design assistant device
Process the flow chart of step.
Fig. 9 is the block diagram of the hardware representing multi-core processor system.
Figure 10 is the functional block diagram of the multi-core processor system 900 relevant to when starting.
Figure 11 is the explanatory diagram of the distribution example representing handle (handler).
Figure 12 is that the distribution representing driver when multi-core processor system 900 starts processes step
Rapid flow chart.
Figure 13 is the functional block diagram of the multi-core processor system 900 relevant to when running.
Figure 14 is the explanatory diagram of the calculated example representing App.
Figure 15 is the explanatory diagram of the distribution example representing process A.
Figure 16 is the explanatory diagram of the distribution example representing process B.
Figure 17 is the explanatory diagram of the distribution example representing process C.
Figure 18 is to represent the flow chart that calculating processes step.
Figure 19 is to represent the flow chart that the distribution of main OS processes step example 1.
Figure 20 is that the distribution representing OS911 processes step example 2 flow chart.
Figure 21 is the functional block diagram of the multi-core processor system 900 relevant to clock frequency.
Figure 22 is the flow chart of the control process step of the clock frequency representing OS.
Detailed description of the invention
Below, referring to the drawings to multi-core processor system involved in the present invention, distribution program and
The preferred embodiment of distribution method is described in detail.
Fig. 1 is the explanatory diagram of the example representing the present invention.First, CPU#0 detection procedure
The distribution instruction of 1.Then, CPU#0 obtains residual time, and this residual time is from as right
The generation moment of the event of the handle A of the interrupt processing of CPU#0 distribution is to the execution phase of handle A
The time (Dt of handle A) only that is limited to eliminates the handle A processing the time as handle A
CP after time.
Then, whether the residual time acquired by CPU#0 judgement is that being defined of process 1 is forbidden
More than the process time (CP of process 1) of the process interrupted.That is, this is in CPU#0
In the case of being assigned with process 1, even if producing the event of handle A in the execution of process 1, also
Judge whether to observe the Dt of handle A.
As it is shown in figure 1, in the case of CPU#0 is assigned with process 1, if in process 1
Be defined the event producing handle A in the execution of the process forbidding interruption, then it is determined that can not
Enough observe the situation of the Dt of handle A.Therefore, CPU#0 does not distributes process 1 to CPU#0.
Fig. 2 is the explanatory diagram of another example representing the present invention.First, CPU#0 detect into
The distribution instruction of journey 1.Then, CPU#0 obtains residual time, and this residual time is from conduct
To CPU#1 distribution interrupt processing handle B event produce moment holding to handle B
The departure date be limited to the time (Dt of handle B) only eliminate as handle B process the time sentence
Time after the CP of handle B.
Then, whether the residual time acquired by CPU#0 judgement is that being defined of process 1 is forbidden
More than the process time (CP of process 1) of the process interrupted.That is, this is in process 1 and is divided
In the case of dispensing CPU#1, even if producing the event of handle B in the execution of process 1, also
Judge whether to observe the Dt of handle B.
If as in figure 2 it is shown, produce the event of handle B in the execution of process 1, being then judged as energy
Enough observe the Dt of handle B.Therefore, CPU#0 distributes process 1 to CPU#1.
First, in embodiment 1, each driver is performed the calculating of time and each driving journey
The deadline date of sequence illustrates.During the starting of then, 2 pairs of polycaryon processors in embodiments,
The distribution of interrupt handling routine and the distribution of process illustrate.
(embodiment 1)
In embodiment 1, use ESL (Electronic System Level) model to each driving
The calculating performing the time of program illustrates.Herein, ESL model refers to by according to hardware device
Behavior (action: behavior) based on describe, by skill simulated for hardware environment
Art.Such as, in the ESL model of CPU, it is not the mechanism by instructing the electric circuit sent
Former state is simulated, but shows with distribution order and its time needed.
It addition, be not the most to utilize circuit mechanism strictly to calculate number in the ESL model of bus
According to the delay propagated, but according to visiting demand, the potentially multiple mode in design is multiplied, by action and
Concept of time is simulated as behavior (action).
In the past, simulation referred to according to circuit design letters such as RTL (Register Transfer Level)
Breath, the situation that actual installation semiconductor ground is not simulated, it is used by realizing and physical device
The action of equivalent is verified.
But, in order to the Detailed simulation of implementing circuit grade is the most time-consuming (generally, for reality
The speed of border equipment is the process time of the one of tens million of～several hundred million points), reality is difficult to make should
While running by program, the movement that system is overall is resolved.On the other hand, at ESL mould
In type, owing to resolving processing the concept with the time as action, so being to be made without
The simulation of circuit just can evaluate the environment processing the time substantially.
(ESL model)
Fig. 3 is the explanatory diagram of the example representing ESL model.ESL model 300 has to be commented
The peripheral circuit model 301 of valency object, peripheral circuit model 302, interrupt control unit model 303
And CPU model 304.
The peripheral circuit model 301 of evaluation object e.g. camera apparatus model or dynamic image are again
Generating apparatus model.If the peripheral circuit model 301 of evaluation object is camera apparatus model, then comment
Valency object driver is camera driver.It addition, peripheral circuit model 301 and periphery electricity
As long as the model that road model 302 accesses to shared memory model 305.
Herein, by increasing the number of bus buffer (bus buffer), make for CPU
The load of model 304 increases.Such as, the degree of depth of bus buffer is 2 to be to represent at bus model
In the case of the bit width of 306 is 128 bits, the hardware beyond CPU model 304 (is evaluated
The peripheral circuit model 301 of object and peripheral circuit model 302) occupy the bus model of 16 bits
306.The degree of depth of buffer be 16 expressions be 128 bits at the bit width of bus model 306
In the case of, (the peripheral circuit model 301 of evaluation object is with outer for the hardware beyond CPU model 304
Enclose circuit model 302) occupy the bus model 306 of 128 bits.
(hardware of Design assistant device)
Fig. 4 is the block diagram of the hardware representing the Design assistant device involved by embodiment 1.At figure
In 4, Design assistant device has CPU (Central Processing Unit) 401, ROM (Read
Only Memory: read-only storage) 402, RAM (Random Access Memory:
Random access memory) 403, disk driver 404, disk 405, optical disk drive 406,
CD 407, display 408, I/F (Interface) 409, keyboard 410, mouse 411,
Scanner 412 and printer 413.And, each portion is connected respectively by bus 400.
Herein, CPU401 administers the overall control of distributor.ROM402 storage has guiding journey
The programs such as sequence.RAM403 is used as the working region of CPU401.Disk driver
404, according to the control of CPU401, control the read/write of the data for disk 405.Disk 405
The data that storage is write by the control of disk driver 404.
Optical disk drive 406, according to the control of CPU401, controls the data for CD 407
Read/write.The data that CD 407 stores the control by optical disk drive 406 and writes,
Or make computer read the data of storage in CD 407.
With cursor, icon or tool box as representative, display 408 show document, image and
The data such as function information.This display 408 such as can use CRT, TFT LCD,
Plasma display etc..
I/F409 by communication line and LAN (Local Area Network: LAN),
The networks 414 such as WAN (Wide Area Network: wide area network), internet connect, and warp
It is connected with other device by this network 414.And, I/F409 administers network 414 with internal
Interface, control the input and output of data from external device (ED).I/F409 such as can use
Modem, lan adapter etc..
Keyboard 410 possesses the key for inputting word, numeral, various instructions etc., carries out data
Input.Alternatively, it is also possible to be the board-like tablet of touch surface, numerical key etc..Mouse 411 is carried out
Light target moves, scope selects or the movement of window, the change etc. of size.As long as possess
With the equipment as the function as pointing device, it is also possible to be tracking ball, control stick etc..
Scanner 412 reads image optically, is taken into view data in distributor.This
Outward, scanner 412 can be made to possess OCR (Optical Character Reader) function.
It addition, printer 413 print image data, document data.Printer 413 such as can use
Laser printer, ink-jet printer.
First, the calculating to the Dt of each object driver illustrates.CPU401 presses each
Object driver obtains the operating frequency of object peripheral circuit, and CPU401 is by 1/ operating frequency
Result of calculation as the deadline date.Such as, the movement standards of display is 60 [Hz], at sound
It is 44.1 [kHz] that the action of reason uses.
The Dt=1/60=16.6 [ms] of display driver
The Dt=1/44.1=22 [μ s] of audio driver
Then, the CP of each object driver is illustrated.
Fig. 5 is the explanatory diagram representing ESL simulation example.CPU401 uses ESL simulator at ESL
Distribute on the CPU model 304 of model 300 and perform evaluation object driver.Bus is delayed
The degree of depth rushing device is that execution time when 2 is as theory execution value.By the reason of display driver
Opinion execution value is set to 10.0 [ms], and the theoretical execution value of audio driver is set as 10.0 [μ s].
In curve map 500, perform result and illustrate performance ratio and the audio frequency of display driver
The performance ratio of driver.The transverse axis of curve map 500 is the degree of depth of bus buffer, curve map 500
The longitudinal axis be performance ratio.Performance than be using the degree of depth of bus buffer be performance when 2 as 1 time
Perform the time ratio.
Specifically, such as CPU401 detects the minimum property of each driver according to curve map 500
Can compare.Herein, for display driver and audio driver, all at bus buffer
The degree of depth be 0.98 this lowest performance ratio when being 16.That is, distinguish for performance maximum degradation 2 [%].
Herein, the deterioration rate of display driver and audio driver is 102 [%].And, as
Following formula calculates the virtual value (CP) of ESL like that.
CP=theory execution is worth × deterioration rate [%]
Therefore, the CP of display driver is the result 10.2 [ms] of 10.0 [ms] × 102 [%].
The CP of audio driver is the result 10.2 [μ s] of 10.0 [μ s] × 102 [%].Thus,
The CPU performing driver can obtain the CPU with other, other hardware to shared storage
The execution time of the driver when access of device there occurs competition.Therefore, in embodiment 2,
The distribution of the distribution of process, driver can be determined based on performance execution time time low.
It addition, CPU401 is for being defined the process forbidding interrupting, calculate the quilt in this process
The execution time (CP) of the process interrupted is forbidden in definition.Specifically, such as CPU401 is to ESL
CPU model 304 in model 300 distributes this process, by using ESL simulator to perform
ESL simulates, and calculates this execution time (CP).
CPU401 exports CP and Dt of each driver, the CP of process.As output form,
The display of the most oriented display 408, to the printout of printer 413 and utilize I/F409
To the transmission of external device (ED).Alternatively, it is also possible to be stored in RAM403, disk 405 and CD
The storage region of 407 grades.
Fig. 6 is the explanatory diagram of the output example of CP and Dt representing driver.At table 600
In, keep Dt and CP by each each Interrupt driver program.Table 600 has driver name project
601, Dt project 602 and CP project 603.Driver name project 601 keeps driving
The identification information of dynamic program, holding Dt, holding in CP project 603 in Dt project 602
CP.Such as, when the identification information in driver name project 601 is video driver,
The value of Dt project 602 is 16.6 [ms], the value of CP project 603 is 10.2 [ms].Wherein, sentence
Handle 1～handle 5 are used for the explanation of the distribution of driver.
Fig. 7 is the explanatory diagram of the output example of the CP representing process.Table 700 is determined by each
Justice forbids that the process interrupted keeps the execution time being defined the process forbidding interruption of this process.Table
700 have process name project 701 and CP project 702.Process name project 701 keeps process
Identification information, CP project 702 keeps be defined the execution time of process forbidding interrupting.
(calculating of CP and Dt of driver processes step)
Fig. 8 is that the calculating of CP and Dt representing the driver carried out by Design assistant device processes
The flow chart of step.First, Design assistant device obtains ESL model (step S801), judges
Whether there is unselected driver (step S802).Then, it is judged as at Design assistant device
When there is no a unselected driver (step S802: "Yes"), from unselected driver
Select a driver (step S803).
Design assistant device obtains the movement standards (step S804) of object driver, makes Dt=1
/ movement standards (step S805).Dt (the step of Design assistant device object output driver
S806), use ESL simulator is to the CPU model supply object driver of ESL model
Perform ESL simulation (step S807).Then, whether Design assistant device judges ESL simulation
Terminate (step S808).
Design assistant device be judged as ESL simulation be not over time (step S808: "No"),
Return to step S808.On the other hand, it is judged as that ESL simulation terminates at Design assistant device
Time (step S808: "Yes"), detect deterioration rate (step S809) according to analog result.
Then, Design assistant device obtains the theoretical execution value (step S810) of object driver,
Calculate CP=theory execution and be worth × deterioration rate (step S811).Such as, designer can be with base
Number of steps etc. in object program calculates the theoretical execution value of object driver.It addition, meter
The theoretical execution value of the object driver calculated is stored in the storage dress that CPU401 is able to access that
Put.Then, the CP (step S812) of Design assistant device object output driver, return
To step S802.In step S802, when Design assistant device is judged as not having unselected driving
During dynamic program (step S802: "No"), terminate a series of process.
(embodiment 2)
Then, in embodiment 2, the distribution of driver and the distribution of application program are carried out
Explanation.Herein, in multi-core processor system, polycaryon processor refers to be equipped with multiple core
Processor.As long as being equipped with multiple core, it can be the single treatment being equipped with multiple core
Device, it is also possible to be the processor processor group arranged side by side of single core.Wherein, this embodiment party
In formula, in order to make explanation simplify, carry out as a example by single-core processor processor group side by side
Explanation.
(hardware of multi-core processor system)
Fig. 9 is the block diagram of the hardware representing multi-core processor system.In multi-core processor system 900
There is peripheral circuit 901, peripheral circuit 902, interrupt control unit 903, CPU#0, CPU#
1, memory 905 and clock supply circuit 906 are shared.Each portion is connected by bus 904.
CPU#0 and CPU#1 is respectively provided with core, register and cache memory.
CPU#0 performs the OS911 as main OS, the entirety of management multi-core processor system 900
Control.Which CPU OS911 controls the course allocation by creating distribution instruction to, and has
The distribution program having the switching to the process in CPU#0 to be controlled supplies to CPU#0 with decision
The control program of the frequency of the clock given.Further, OS911 has at multi-core processor system 900
The distribution program of the distribution of driver is determined during starting.
CPU#1 performs as from the OS912 of OS.OS912 has distributing to CPU#1
The distribution program that is controlled of the switching of process and determine the frequency of clock to CPU#1 supply
The control program of rate.
Clock supply circuit 906 is to each CPU, peripheral circuit 901, peripheral circuit 902, interruption
Controller 903 and shared memory 905 are supplied respectively to clock.And, in embodiment 2,
Clock supply circuit 906 such as has CPU by each of each portion and can set and supply to this each portion
The register of the clock frequency given.Clock supply circuit 906 is based on the value next life set in register
Become clock, supply clock to each portion.
Peripheral circuit 901 and peripheral circuit 902 e.g. camera apparatus, audio frequency apparatus, keyboard
Deng.
If interrupt control unit 903 receives from peripheral circuit 901, the interruption of peripheral circuit 902
Signal, then make each CPU recall the interrupt handling routine corresponding with this interrupt signal based on interrupt table.
Sharing memory 905 is the memory that CPU#0 and CPU#1 shares.Share memory
905 such as have ROM (Read Only Memory), RAM (Random Access
And flash rom etc. Memory).Share memory 905 such as store have management of process table 922,
The programs such as the bootstrap of OS911 Yu OS912, above-mentioned table 600 and above-mentioned table 700, driving
Program 921 groups and not shown interrupt table.
Such as, ROM or flash rom store this program, driver group etc., RAM conduct
The working region of CPU#0 and CPU#1 is used.By storage in shared memory 905
OS911 and OS912 is loaded in each CPU, makes each CPU perform the most decoded process.
Driver group 921 has the driver corresponding with each peripheral circuit.Each OS selects from driving
The driver that dynamic program group 921 recalls.
Management of process table 922 e.g. represents each process is assigned to which CPU, allocated
Whether CPU is carrying out the information of this process.Each CPU reads management of process table 922, in advance
Store it in the cache memory of each CPU.If OS911 by course allocation to CPU#
Any one CPU in 0 and CPU#1, then register this process to management of process table 922 and divided
Which CPU of dispensing.It addition, each OS is at the end of the execution to the process that this OS distributes, will
Description about this process eliminates from this management of process table 922.
Then, in embodiment 2, the distribution to driver illustrates.At embodiment
In 2, it is driven the distribution of program when multi-core processor system 900 starts.It addition, not
It is confined to this, it is also possible to after the OS of polycaryon processor updates, determine the distribution of driver, also
Can determine when downloading any driver.
(functional block diagram of the multi-core processor system 900 relevant to when starting)
Figure 10 is the functional block diagram of the multi-core processor system 900 relevant to when starting.At multinuclear
Reason device system 900 has adder 1001, determines portion 1002, judging part 1003 and distribution
Portion 1004.Adder 1001～dispenser 1004 have OS911, CPU#0 from shared storage
After device 905 loads OS911, in this OS911, perform the process of the most decoded (coding).
Adder 1001 is by the time that performs of object interrupt processing and to appointing in polycaryon processor
The execution time of the interrupt processing being assigned of meaning CPU distribution is added.
Judging part 1003 addition results based on adder 1001, it is judged that whether arbitrary CPU
The Deadline started when above-mentioned object interrupt processing recalls can be observed and from being assigned
The Deadline started when recalling of interrupt processing.
Utilize judging part 1003 be judged as can observe from object interrupt processing when recalling from the beginning of
Deadline and when the Deadline started when recalling of the interrupt processing being assigned,
Dispenser 1004 distributes above-mentioned object interrupt processing to arbitrary CPU.
It addition, determine that portion 1002 recalls the moment to Deadline from object interrupt processing
The interrupt processing being assigned of time and each interrupt processing being assigned recall the moment
In the time of Deadline, determine the shortest time.Embodiment 2 will be referred to as the shortest time
The shortest Dt.
Judging part 1003 judges by determining that whether shortest time that portion 1002 determines is in adder
Below the addition results of 1001.
When utilizing judging part 1003 to be judged as that the shortest time is below addition results, dispenser 1004
To arbitrary CPU distribution object interrupt processing.
In view of above step, accompanying drawing is used to be described in detail.
Figure 11 is the explanatory diagram of the distribution example representing handle.Handle 3 and handle 4 are assigned to CPU
#0, handle 1 and handle 2 are assigned to CPU#1.If each handle is allocated, then OS911
By retrieving the CP of just allocated all handles from table 600, obtain these all handles
CP.Then, OS911 calculates the aggregate value of CP by the CP obtained is carried out add operation.
The aggregate value of the CP in CPU#0 is 15 [ms], and the aggregate value of the CP in CPU#1 is
21[ms]。
First, OS911 selects unappropriated handle 5 from multiple handles.Herein, multiple handles
It it is the continuous action type driver determining CP and Dt.Then, OS911 is from shared storage
Device 905 obtains handle 5.Then, by OS911 retrieve from table 600 handle 5 CP and
The Dt of handle 5, obtains the CP and the Dt of handle 5 of handle 5.
The aggregate value of CP and the CP of handle 5 are carried out add operation by each CPU by OS911.
The addition results of CPU#0 is 20 [ms], and the addition results of CPU#1 is 26 [ms].Then,
OS911 determines the CPU of below the Dt that addition results is handle 5.Herein, CPU#0 is by really
Fixed.Then, OS911 distributes handle 5 to the CPU#0 determined.
(distribution of driver processes step)
Figure 12 is that the distribution representing driver when multi-core processor system 900 starts processes step
Rapid flow chart.In the above example, detect simultaneously all CPU CP aggregate value and
The shortest Dt, but in this flow chart, start to detect in order the aggregate value of CPU from CPU#0
The shortest Dt, and judge whether to distribute to CPU.
First, OS911 starts system start, driver distribution process (step S1201).So
After, OS911 makes k=0 (step S1202), it is judged that (step that whether all drivers distribute is terminated
Rapid S1203).When OS911 is judged as unallocated all drivers (step S1203: "No"),
Select a driver as object driver (step from unappropriated driver
S1204)。
Then, the OS911 CP of driver and object driver to distributing to CPU#k
CP carry out the add operation aggregate value of CP (calculate) (step S1205).OS911 is from dividing
The Dt of the driver of dispensing CPU#k and the Dt of object driver determines the shortest Dt (step
Rapid S1206).Then, OS911 judges whether the aggregate value≤the shortest Dt (step S1207) of CP.
OS911 be judged as be not the aggregate value≤the shortest Dt of CP time (step S1207: "No"),
Make k=k+1 (step S1208), make k≤all CPU numbers (step S1209).?
OS911 is judged as, during k≤all CPU numbers (step S1209: "Yes"), returning to step
S1205.On the other hand, OS911 be judged as be not k≤all CPU numbers time (step
S1209: "No"), output error (Error) (step S1210), terminates a series of process.
When OS911 is judged as the aggregate value≤the shortest Dt of CP (step S1207: "Yes"), to
CPU#k distribution object driver (step S1211).It addition, when distribution, by this object
Which CPU driver is assigned to stores in interrupt table.Then, the OS912 of CPU#k
Start object driver (step S1212).
It addition, when OS911 is judged as being assigned all drivers (step S1203:
"Yes"), ends with system starts (step S1213), and terminates a series of process.
Even if it addition, to the designer of multi-core processor system 900 when design by all driving journeys
Sequence distributes to polycaryon processor, and all drivers also are able to work and confirm.Thus, design
Person is able to verify that and does not the most produce the weak point in design in multi-core processor system 900.
Then, the distribution of process when running multi-core processor system 900 illustrates.
(functional block diagram of the multi-core processor system 900 relevant to when running)
Figure 13 is the functional block diagram of the multi-core processor system 900 relevant to when running.At multinuclear
Reason device system 900 has test section 1301, obtaining section 1302, judging part 1303 and dispenser
1304.Test section 1301～dispenser 1304 have OS911, CPU#0 from shared memory
905 load OS911, and perform the most decoded process in this OS911.
The distribution instruction of test section 1301 detection procedure.
If utilizing test section 1301 to detect the distribution instruction of process, then obtaining section 1302 obtains residual
The remaining time, this residual time is the interrupt processing that any CPU from polycaryon processor is allocated
Recall the process time deducting interrupt processing in moment to the time of the Deadline of interrupt processing
After time.Herein, the time to the Deadline of interrupt processing in the moment is recalled from interrupt processing
For Dt.Residual time is set as App.
Judging part 1303 judges whether the residual time obtained by obtaining section 1302 is being determined of process
Justice forbids the process time of the process of interruption more than.
What utilizing judging part 1303 to be judged as, residual time was process is defined the place forbidding interrupting
Time more than the process time of reason, dispenser 1304 distributes process to this any CPU.
In view of above step, accompanying drawing is used to illustrate.
Figure 14 is the explanatory diagram of the calculated example representing App.In fig. 14, video driver quilt
Distributing to CPU#0, audio driver is assigned to CPU#1.First, if driver
Distribution process terminate, the most each OS obtains allocated all drivings by retrieval table 600
The CP of program and the Dt of this driver.
Then, each OS calculates the aggregate value of CP.In fig. 14, due to each OS the most only
An allocated driver, so the aggregate value of the CP in OS911 is 10.2 [ms], OS912
In the aggregate value of CP be 10.2 [μ s].Then, each OS is from allocated driver
Dt retrieves the shortest Dt, the shortest Dt.The shortest Dt in OS911 is 16.6 [ms], OS912
In the shortest Dt be 22 [μ s].
Then, each OS deducts the aggregate value of CP from the shortest Dt.Subtraction in OS911 is tied
Fruit is set as App (0), and the subtraction result in OS912 is set as App (1).OS912
The aggregate value of App (1) and CP is set up and associatedly notifies to the OS911 as main OS.
It addition, the aggregate value of each OS output CP and App.As output form, such as, can store
To sharing memory 905.
Figure 15 is the explanatory diagram of the distribution example representing process A.If OS911 detects process A
Distribution instruction, then OS911 is by from the CP of table 700 retrieval process A, obtaining process A
CP.OS911 determines the CPU of the App of more than the CP of process A.CPU#0 is by really herein
Fixed.Then, OS911 distributes process A to the CPU#0 determined.
Figure 16 is the explanatory diagram of the distribution example representing process B.Then, if OS911 detect into
The distribution instruction of journey B, then OS911 is by from the CP of table 700 retrieval process B, obtain into
The CP of journey B.OS911 determines the CPU of the App of more than the CP of process B.CPU herein
#0 and CPU#1 is determined.Then, OS911 distributes process B to the CPU#1 determined.
Figure 17 is the explanatory diagram of the distribution example representing process C.Then, if OS911 detect into
The distribution instruction of journey C, then OS911 is by from the CP of table 700 retrieval process C, obtain into
The CP of journey C.OS911 determines the CPU of the App of more than the CP of process C.CPU herein
#0 is determined.Then, OS911 distributes process C to the CPU#0 determined.
(calculating of multi-core processor system 900 processes step and distribution processes step)
Figure 18 is to represent the flow chart that calculating processes step.Each OS performs the calculating of App and processes,
This illustrates as a example by sentencing OS912.First, whether OS912 judges the distribution of driver
Terminate (step S1801).(step at the end of OS912 is judged as the distribution not of driver
Rapid S1801: "No"), return to step S1801.Then, it is judged as driving journey at OS912
At the end of the distribution of sequence (step S1801: "Yes"), obtain allocated all driving journeys
CP and Dt (step S1802) of sequence.
Then, the aggregate value (step of the CP of all drivers that OS912 calculating is allocated
S1803), from the Dt of allocated driver, the shortest Dt (step S1804) is detected.
OS912 calculates the aggregate value (step S1805) of the shortest Dt-CP of App=, leads to main OS
Know the aggregate value (step S1806) of App Yu CP.
Figure 19 is to represent the flow chart that the distribution of main OS processes step example 1.First, as master
The OS911 of OS judges whether distribution instruction (step S1901) of the process that receives.At OS911
It is judged as, during the distribution instruction of the process that is not received by (step S1901: "No"), returning to step
Rapid S1901.On the other hand, (the step when OS911 is judged as the distribution instruction of the process that receives
S1901: "Yes"), obtain the CP (step S1902) of the process receiving distribution instruction.
Then, OS911 makes i=0 (step S1903), it may be judged whether there is CPU#i (step
S1904).When OS911 is judged as existing CPU#i (step S1904: "Yes"), calculate
Go out the CP (step S1905) acquired by the App-of SUB=CPU#i, then judge whether
SUB >=0 (step S1906).
When OS911 is judged as SUB >=0 (step S1906: "Yes"), CPU#i is true
It is set to the CPU (step S1907) that can distribute, SUB is set up associatedly defeated to CPU#i
Go out (step S1908), make i=i+1 (step S1909).On the other hand, judge at OS911
During for not being SUB >=0 (step S1906: "No"), move to step S1909.
It addition, when OS911 is judged as not existing CPU#i (step S1904: "No"),
Judge whether the CPU determined has multiple (step S1910).It is judged as determining at OS911
CPU when having multiple (step S1910: "Yes"), from the CPU determined, determine SUB
Maximum CPU (step S1911), to CPU distribution process (step S1912) determined,
And return to step S1901.
When OS911 is judged as that the CPU determined is not multiple (step S1910: "No"),
To CPU distribution process (step S1913) determined, then return to step S1901.
Figure 20 is to represent the flow chart that the distribution of OS911 processes step example 2.First, OS911
Judge whether distribution instruction (step S2001) of the process that has been received by.It is judged as not at OS911
When receiving the distribution instruction of process (step S2001: "No"), return to step S2001.Separately
On the one hand, when OS911 is judged as the distribution instruction of the process that receives (step S2001: "Yes"),
Obtain the CP (step S2002) of the process receiving distribution instruction.
Then, OS911 makes i=0 (step S2003), it may be judged whether there is CPU#i (step
S2004).When OS911 is judged as existing CPU#i (step S2004: "Yes"), it is judged that
The whether CP (step S2005) of the App of CPU#i >=acquired.It is judged as at OS911
During the CP of the App of CPU#i >=acquired (step S2005: "Yes"), divide to CPU#i
Join process (step S2006), then return to step S2001.
OS911 be judged as be not the CP of the App >=acquired of CPU#i time (step
S2005: "No"), make i=i+1 (step S2007), and return to step S2004.It addition,
When in step S2004, OS911 is judged as not existing CPU#i (step S2004: "No"),
Output error (step S2008), and return to step S2001.
Then, enter by the example that the clock frequency supplied to the CPU of unassigned process reduces
Row explanation.
(functional block diagram of the multi-core processor system 900 relevant to clock frequency)
Figure 21 is the functional block diagram of the multi-core processor system 900 relevant to clock frequency.Multinuclear
Each OS of processor system 900 has test section, judging part, obtaining section, determination section and sets
Determine portion.OS911 has test section 2101, judging part 2102, obtaining section 2103, determination section 2104
And configuration part 2105, OS912 have test section 2111, judging part 2112, obtaining section 2113,
Determination section 2114 and configuration part 2115.Each CPU loads respective from shared memory 905
OS, performs the most decoded process in this OS.
Test section 2101 and test section 2111 are same treatment, it is judged that portion 2102 and judging part
2112 is same treatment.Further, obtaining section 2103 and obtaining section 2113 are same treatment, determine
Portion 2104 and determination section 2114 are same treatment, and configuration part 2105 is identical with configuration part 2115
Process.Herein, illustrate as a example by test section 2101～configuration part 2105.
Test section 2101 detects being assigned that any CPU in polycaryon processor distributes
The end of process.Herein, any CPU is set as CPU#0.
At the end of the process utilizing test section 2101 to detect to be assigned, it is judged that portion 2102
Judge whether not distribute any process to arbitrary CPU.
When not distributing any process to CPU#0 utilizing judging part 2102 to be judged as, obtaining section
2103 obtain residual times, and this residual time is from the tune of interrupt processing to CPU#0 distribution
Go out the process deducting above-mentioned interrupt processing in the time to the Deadline of interrupt processing in the moment
Time after time.Herein, residual time is App.
Determination section 2104 is according to the residual time obtained by obtaining section 2103 and interrupt processing
The ratio of reason time, determines the clock frequency to CPU#0 supply.
Configuration part 2105 is to the determination result in the supply source supply constraints portion 2104 of clock.Herein,
Clock supply source is clock supply circuit 906.Therefore, the most such as by CPU#0, clock is supplied
To register corresponding with the clock frequency supplied to this CPU#0 in the register in circuit 906
Set determination result.
It addition, test section 2101 detects the distribution to CPU#0 of the unappropriated process.
If utilize test section 2101 detect above-mentioned unappropriated process to the distribution of CPU#0,
Then configuration part 2105 will be supplied to the supply source of above-mentioned clock by the frequency of the specification of CPU#0
Give.
Such as, the App of CPU#0 is set as 6.4 [ms], the aggregate value of CP is set as
10.2[ms].Now, relative to 10.2 [ms], owing to being the remaining of CPU#0 before 6.4 [ms]
Power, it is possible to it is 0 that clock is reduced to surplus energy.Herein, by with the specification of CPU#0
The clock frequency set supplied to this CPU#0 be CMAX.In the case of Gai, it is possible to will be to
The clock frequency of CPU#0 supply is reduced to C.
C=CMAX { aggregate value of 1-App/CP }
Herein, CMAX is 100MHz,
C=100 { 1-6.4/10.2}=37.25 [MHz].
Herein, in shared memory 905, maintain the CMAX of each CPU.Use stream
Detailed process is illustrated by journey figure.
(control of clock frequency processes step)
Figure 22 is to represent the flow chart that the control to clock frequency of OS processes step.By respectively
OS performs control and processes, and illustrates here as a example by OS911.First, OS911 judgement is
The execution of the no distribution detecting process or process terminates (step S2201).Judge at OS911
For do not detect the distribution one-level process of process execution at the end of (step S2201: "No"),
Return to step S2201.
Then, (step S2201: process when OS911 is judged as the distribution detecting process
Distribution), obtain by the clock frequency (CMAX) (step S2202) of specification.About
The distribution of process, it is possible to detected with reference to management of process table 922 by OS911.
Then, OS911 gives CMAX (step S2203) to clock supply circuit 906,
And return to step S2201.To clock supply circuit 906 give CMAX refer to to time
The register that the clock frequency of the CPU#0 supply in clock supply circuit 906 is corresponding sets
CMAX。
On the other hand, (step at the end of the execution of the process that detects it is judged as at OS911
The execution of S2201: process terminates), it may be judged whether there is allocated process (step S2204).
OS911 can detect the end of process by referring to management of process table 922.
When OS911 is judged as there is allocated process (step S2204: "Yes"), return
Return to step S2201.(the step when OS911 is judged as there is not allocated process
S2204: "No"), obtain by the clock frequency (CMAX) (step S2205) of specification.
Then, OS911 calculates C=CMAX × (aggregate value of 1-App/CP) (step
Rapid S2206), give C (step S2207) to clock supply circuit 906.To clock supply electricity
Road 906 gives the time clock frequency that C refers to give with the CPU#0 in clock supply circuit 906
Register corresponding to rate is set as C.
As described above, according to multi-core processor system, distribution program and distribution method,
Process is assigned to arbitrary core, by judging the interrupt processing being assigned to this any core
Whether can observe the Deadline from the recalling of this interrupt processing, decide whether to arbitrarily
Core distribute this process.Thus, even if distribution is defined the process forbidding interrupting, it is also possible to abide by
Keep the Deadline from the recalling of interrupt processing.I.e., it is possible to not in order to driver is special
Guarantee CPU.
Described above, according to multi-core processor system, distribution program and distribution method,
By the execution time of object interrupt processing with to one or more interrupt processings that any core is distributed
The execution time is added.Then, by based on add operation result, it is judged that this object interrupt processing with
And 1 or multiple interrupt processing whether can observe the Deadline from respective recalling, energy
Enough judge whether to this arbitrary core distribution object interrupt processing.Thus, even if recall many simultaneously
Individual interrupt processing, it is also possible to observe the Deadline from the recalling of each interrupt processing.
It addition, from moment to time of Deadline that recalls of this object interrupt processing and each
The above-mentioned interrupt processing being assigned of the interrupt processing being assigned recall the moment to the execution phase
It is limited in the time only, determines the shortest time.Then, it is judged that whether this shortest time determined
Below addition results.Thereby, it is possible to judge this object interrupt processing and the interruption being assigned
Process and whether can observe the Deadline from respective recalling.Therefore, it can make at judgement
Reason high speed, it is possible to carry out the distribution of interrupt processing at high speed.
Described above, according to multi-core processor system, control program and control method,
If detecting, the execution of the process being assigned distributed any CPU terminates, then be judged as
Any process is not distributed to this any CPU.Without allocated any process, then based on
From to the Deadline the recalling of interrupt processing of this any CPU distribution, determine to
The clock frequency of this any CPU supply.Thereby, it is possible to observe the deadline date of each driver
Time, realize low power consumption simultaneously.
If it addition, detect the distribution to this any CPU of the unappropriated process, then will be to this
The clock frequency that meaning CPU gives returns to the frequency determined by specification.Thereby, it is possible to observe each
Time deadline date of driver.
Symbol description: 900... multi-core processor system；1001... adder；1002... determine portion；
1003,1303,2102,2112... judging part；1004,1304... dispenser；1301、2101、
2111... test section；1302,2103,2113... obtaining section；2104,2114... determination section；2105、
2115... configuration part.
Claims (2)
1. a multi-core processor system, has:
Multiple cores, perform allocated interrupt processing；And
Storage part, stores process temporal information and the Deadline information of each interrupt processing,
1st core of the plurality of core is in the case of detecting the 1st interrupt processing, based on depositing
The described process temporal information being stored in described storage part calculates each distribution to the plurality of core
Interrupt processing and the total of described 1st interrupt processing process the time, and according to based on storage
The Deadline of described 1st interrupt processing of described Deadline information and institute in described storage part
State total and process the time by described 1st interrupt processing distribution to holding in described Deadline
Any one in the plurality of core of row.
2. a control method for multi-core processor system,
Described multi-core processor system has:
Multiple cores, perform allocated interrupt processing；And
Storage part, stores process temporal information and the Deadline information of each interrupt processing,
1st core of the plurality of core performs to process as follows:
In the case of detecting the 1st interrupt processing, based on the described place being stored in described storage part
Reason temporal information calculates in the interrupt processing and the described 1st of each distribution of the plurality of core
The disconnected total processed processes the time,
At described 1st interruption based on the described Deadline information being stored in described storage part
The Deadline of reason and described total process the time by described 1st interrupt processing distribution to can be
Any one in the plurality of core performed in described Deadline.
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