TW200807356A - Control module and data driver - Google Patents

Abstract

A control module including a first sampling unit, a second sampling unit, a first latch unit, a first inverter, a second inverter, a capacitor and a buffer. The first sampling unit samples a data signal to generate a first sampling signal. The first latch unit latches the first sampling signal to generate a first latch signal. The second sampling unit samples the first latch signal to generate a second sampling signal. The first and second inverters and the capacitor latch the second sampling signal and transform the level of the second sampling signal. The buffer is coupled to the first and second inverters for generating a second latch signal and amplifies the second latch signal.

Description

200807356 . IX. INSTRUCTIONS: 1. Technical Field 1. The present invention relates to a sampling and challenge control module, and more particularly to a sampling and latching control module having a level shift function. group. [Prior Art] Fig. 1 is a schematic diagram of the connection of a conventional sampling/latch and level converter. As shown, the sample/interrogation lock 12 has sample/latch units 122,124. The sample/latch unit 122 samples the data signal DATA and locks the sampled signal. The sample/latch unit 124 receives the latched signal from the sample/latch unit 122 and samples and latches the signal. Finally, the sample/latch unit 124 outputs the latched signals to the level shifters 14 and 16. Since the operating voltages of the sampling/latch units 122, 124 are VDD and VSS, the level of the output signal of the sampling/latch unit 124 is at VDD and VSS. However, the level of the output signal of the sampling/latch unit 124 can be adjusted to VDD2 and VSS2 by the level shifters 14 and 16. First, the level shifter 14 first adjusts the level of the output signal of the sample/latch unit 124 from VDD to VDD2. At this time, the level of the output signal of the level shifter 144 is VDD2 and VSS. The level shifter 16 then adjusts the level VSS of the output signal of the level shifter 144 to VSS2. At this time, the level of the output signal OUT of the level shifter 16 is 0773-A32083TWF; P2006013:joamie 5 200807356 is VDD2 and VSS2. As can be seen from the above, in order to adjust the level of the round-trip dream of the sampling/latch unit U4, the level signals of the sampling/latch unit 124 are subjected to level conversion by the level shifters 14 and 16. However, it causes an increase in component cost and a reduction in usable space. SUMMARY OF THE INVENTION The present invention provides a control module including a first and second sampling unit, a first latch unit, first and second inverters, a capacitor unit, and a buffer. The first sampling unit samples a data signal to generate a first sampling signal. The first latch unit latches the first sampling signal to generate a first latch signal. The first latch signal has a first and a second level. The first sampling unit samples the first latch signal to generate a second sample signal. The input of the first inverter receives the second sampled signal. The input of the second inverter is coupled to the output of the first inverter. The capacitor unit is coupled between the input end of the first inverter and the output end of the second inverter. The first and second inverters and the capacitor unit are used to latch and convert the level of the second sampled signal. The buffer is coupled to the first and second inverters for generating a second challenge signal and amplifying the second latch signal. The present invention further provides a data driver including a shift register, a control board group, a digital class comparison, and an analog buffer. The shift register generates a pulse signal based on the clock signal. The control module samples and latches the data signal based on the pulse signal and converts the level of the latched data signal to generate a digital signal. The digital type comparator is used to convert the digital signal outputted by the 0773-A32083TWF; P2006013:jo; 6 200807356 control module into an analog signal. An analog buffer is used to amplify the analog signal. The control module includes first and second sampling units, a first latch unit, first and second inverters, a capacitor unit, and a buffer. The first sampling unit samples a data signal to generate a first sampling signal. The first latch unit latches the first sampling signal to generate a first latch signal. The second sampling unit samples the first latch signal to generate a second sample signal. The input of the first inverter receives the second sampled signal. The input of the second inverter is coupled to the output of the first inverter. The capacitor unit is positioned between the input of the first inverter and the output of the second inverter. The first and second inverters and the capacitor unit are used to latch and convert the level of the second sampled signal. The buffer is coupled to the first and second inverters for generating a second latch signal and amplifying the second latch signal as a digital signal input to the digital analog converter. The above and other objects, features and advantages of the present invention will become more <RTIgt; A schematic diagram of the contents of the liquid crystal display of the present invention. As shown, the liquid crystal display 20 includes a scan driver 22, a data driver 24, and a display array 26. The scan driver 22 supplies a scan signal to the gate electrodes G1 to Gn. The data driver 24 supplies a data signal to the source electrodes S1 to Sm. The display array 26 has a plurality of arrays arranged in an array manner. 0773-A32083TWF; P2006013: joamie 7 200807356 = early 7L 262' per-display unit minus-gate and poles are used to receive corresponding scan signals and data signals. The original 244, Π: move 22 includes a 'shift register 242, a control module digital cheque comparator 246, and an analog buffer. When a certain pole receives the sweep signal, the shift register 242 sends the pulse signals SPi to SPn to the control module 244 according to the clock CLK. The control group Π 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据 据/Latch unit (not shown), in the most, level-level sample/question lock unit, not only the sampling and latching action of the upper-stage sampling/latch-single 7G output signal, but also the leveling Conversion 'Therefore, the control module 244 has the functions of sampling, asking for lock and conversion. The digital analog converter 246 receives and converts the digital apostrophe of the control module 244 by φ into an analog signal. The analog buffer 248 amplifies the analog signal and outputs it to the corresponding source electrode such that the display array 26 presents the image. Figure 3 shows a possible example of one of the control modules of the present invention. The control module 244 of the present invention has a multi-stage sampling/latch unit, and the sampling/flash lock unit of the last stage has a level conversion function, so that it is not necessary to additionally set the level converter. The present invention does not limit the number of stages of the sampling/latch unit, and for convenience of explanation, the figure 3 shows only the two-stage sampling/flash lock unit. As shown, the control 0773-A32083TWF; P2006013: joanne 8 200807356 module 244 includes the sampling network lock unit 32 and the inverter 351 in the core shut-off unit 34 to operate, in sampling / and has a capacitor unit 354 Therefore, the sampling brain and not only have the function of sampling and latching, but also have the level shifting 34. The butterfly lock unit 32 includes the sampling unit 322 ^^[ 3 2 4 . Sampling unit 3 22 according to the sample material = lock early

Sampling action to generate sampling money~. In the case of the A-like signal (10), the pulse letter 322 shown in Fig. 2 is the transistor τρ, and its gate receives the sampling signal (4): the vertical DATA ? SS1 〇 (10) ^ 0324 asks to lock the sampling unit to turn off The signal ssl' is sampled to generate a question lock signal Su. In this embodiment, the Xiang unit cookware sH^331~333. The input of the inverter 331 receives the sample U ssl , and its output terminal is connected to the input terminal of the inverter 332. The inverter looks like the output terminal of the inverter, 331 is used to flash the sampling signal SS1. The reverse phase benefit 333 is connected to the inverter, such as the output terminal, and the latch signal SL1 取样 the sample/flash lock unit 34 includes a sampling unit 342 and a question lock unit 344. The sampling unit 342 acts on the (10) signal & amp to generate a sampling signal Ss2 based on the sampling signal (10). In the present embodiment, the sampling unit 342 is a transistor TP2, the gate of which receives the sampling signal (4), the source of which receives the flash lock signal SL1, and which has a pulsed sampling signal ^. The flash lock unit 344 flashes the sampling unit such as the sampled signal Ss2' that is rotated to generate the flash lock signal sL2. In the present embodiment, the flash lock unit 0773-A32083TWF; P2006013: joanne 9 200807356 344 has inverters 351 to 353 and a capacitor unit 354. The input terminal of the inverter 351 receives the sampling signal SS2, and the output end thereof is coupled to the input terminal of the inverter 352. The capacitor unit 354 is coupled between the input of the inverter 351 and the output of the inverter 352. Inverters 351 and 352 and capacitor thick 354 are used to latch the sampling signal Ss2 and to convert the sampling signal sS2i to VDD2 and VSS2. The inverter 353 serves as a buffer having an amplification function coupled to the output of the inverter 351 for generating and amplifying the latch signal SL2 to the digital analog converter 246. As shown, the operation level of the inverter 33U32 of the sample/interlock unit 32 is VDD and VSS, so the level of the latch signal SL1 is also VDD and VSS. However, the inverters 351 to 353 of the sampling/flash lock unit 34 are inserted at VDD2 and VSS2, so that the level of the latch signal sL2 can be adjusted to VDD2 and VSS2. The level VDD2 is greater than the level VDD, and the level VSS2 is less than VSS. Figure 4a is a possible embodiment of one of inverters 331 and 332. As shown in the figure, the inverter 331 includes transistors 411 and 412. The transistor 411 is of the P-type, and its gate receives the sampling signal core 1, and its source receives the level of ¥00. The transistor 412 is of the N-type, the gate of which is coupled to the gate of the transistor 411, the source of which receives the level VSS, and the drain of which is coupled to the drain of the transistor 411. Inverter 332 includes transistors 413 and 414. The transistor 413 is p-type, its gate is coupled to the drain of the transistor 412, and its source receives the level VDD. The transistor 414 is of a berm type, the gate of which is coupled to the drain of the transistor 412, the source of which receives the level Vss, and the drain of which is coupled to the drain of the transistor 413 0 0773-A32083TWF; P2〇〇6〇i3: j 10 200807356 Figure 4b shows inverters 351, 352 and possible embodiments of capacitance. As shown, one of the inverters 351 is 422. What is the transistor 421? Type, its closed-pole transistor 421 and source receive level VDD2. The transistor 42 has a signal Ssz, the gate of the transistor 421, and its source 1 gate is switched to the drain of the transistor 42! The VSS2' is infinitely lightly connected. The inverter 352 includes a transistor type, and its gate is coupled to the transistor 44. Transistor 423 gp VDD2. The drain of the transistor 424 · , has its source receiving the level, its source receiving level vss: &gt; ', the gate is lightly connected to the transistor 422; and the pole. The 电容 capacitor unit 344 of the 耦 耦 电 电 电 电 344 344 344 344 344 344 344 344 344 344 344 344 344 344 425 425 425 425 425 425 425 425 425 425 425 The transistor 425 is coupled to the gate of the transistor 422.曰~ 424 汲 , , , , , , , , , , 其 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 424 w - and VSS2 ' and the level of the capacitor single is adjusted to the two-stage conversion of the latch signal converter generated by VDD2 &amp; 34, without the need to additionally use the two levels to add space. The present invention may be substantially reduced in size, and the present invention is not limited to the general knowledge without departing from the spirit and scope of the present invention. Retouching, therefore, the protection of the present invention, when it can be made a little more change and the class of consumption is attached to the patent application model 0773-A32083TWF; P2006013: joanne 200807356 as defined. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing the connection of a conventional sampling/latch and level converter. Fig. 2 is a view showing the contents of a liquid crystal display to which the present invention is applied. Figure 3 shows a possible example of one of the control modules of the present invention. • Figure 4a is a possible embodiment of one of inverters 331 and 332. Figure 4b is a possible embodiment of inverters 351, 352 and capacitor unit 354. [Main component symbol description] 12: Sampling/interrogation lock; 14, 16: Level shifter; 122, 124, 32, 34: Sampling/latch unit;

20 · LCD display, 24 · poor driving drive Christine, 262: display unit; 244: control module; 248: analog buffer; 324, 344: latch unit; 22: scan driver; 26: display array; 242: shift register; 246: digital comparator 322, 342: sampling unit; TP1, TP2, 411~414, 421~425: transistor; 331~333, 351~353: inverter; 354 : Capacitor unit. 0773-A32083TWF;P2006013:joamie . 12

Claims (1)

200807356 X. Patent application scope: 1. A control module comprising: a first sampling unit, sampling a data signal to generate a first sampling signal; a first sensing unit, latching the first sampling Signaling to generate a first latch signal, the first latch signal is at a first and second level; and a second sampling unit sampling the first latch signal to generate a a second sampling signal having a first input terminal and a first output terminal, the first input terminal receiving the second sampling signal; a second inverter having a second input terminal; a second output terminal coupled to the first output terminal; a capacitor unit coupled between the first input terminal and the second output terminal, the first and second inverters The capacitor unit is configured to latch and convert the second sampling signal; and 10 a buffer coupled to the first and second inverters to generate a second latch signal and amplify the second latch Lock signal, the level of the second latch signal is a third The fourth level, the third level greater than the first level, the fourth level is less than the second level. 2. The control module of claim 1, wherein the first and second sampling units are P-type transistors. 3. The control module of claim 1, wherein the first inverter comprises: 0773-A32083TWF; P2006013: joanne 13 200807356 a first p-type transistor, the gate receiving the second a sampling signal, the source receiving the third level; and a first N-type transistor having a gate coupled to the gate of the first P-type transistor and the capacitor early 'the source receiving the fourth The level is 'not coupled to the drain of the first P-type transistor. 4. The control module of claim 3, wherein the second inverter comprises: a second P-type transistor, the gate of which is coupled to the drain of the first N-type transistor, The source receives the third level, and the drain is coupled to the capacitor unit; and a second N-type transistor, the gate of which is coupled to the drain of the first N-type transistor, and the source receives the first The four terminals are quasi-polarized and coupled to the drain of the second P-type transistor. 5. The control module of claim 4, wherein the first latch unit comprises: a third inverter having a third input and a third output, the third input Receiving the first sampling signal; a fourth inverter having a fourth input end and a fourth output end, the fourth input end is coupled to the third output end, and the fourth output end is coupled to the third output end The third and fourth inverters are configured to latch the first sampling signal, and a fifth inverter is coupled between the third output terminal and the second sampling unit to generate the The first latch signal is to the first sampling unit. 6. The control module of claim 5, wherein the 0773-A32083TWF; P2006013: joanne 14 200807356 • the third inverter comprises: a third p-type transistor, the gate receiving the first a sampling signal, the source receiving the first level; and a third N-type transistor having a gate coupled to the gate of the first P-type transistor, the source receiving the second level, The drain is coupled to the drain of the third P-type transistor. 7. The control module of claim 6, wherein the fourth inverter comprises: a fourth P-type transistor, the body of which is coupled to the third N-type transistor a drain, the source receiving the first level; and a fourth N-type transistor having a gate coupled to the drain of the third N-type transistor, the source receiving the second level, and wherein the source receives the second level The pole is coupled to the drain of the fourth P-type transistor. 8. A data driver, comprising: a shift register, generating a pulse signal according to a clock signal; I a control module comprising a first sampling unit, sampling a data signal according to the pulse signal to generate a first sampling signal; a first latching unit latching the first sampling signal to generate a first latching signal, wherein the first latching signal is at a first and second level a second sampling unit sampling the first latch signal to generate a second sampling signal; a first inverter having a first input and a first output 0773-A32083TWF; P2006013: joaime 15 200807356 The first input end receives the second sampling signal; a second inverter has a second input terminal and a second output terminal, the second input end is coupled to the first output end; Between the first input terminal and the second output terminal, the first and second inverters and the capacitor unit are configured to latch and convert the second sampling signal; and a buffer, coupled Connect the first and second inversion The second latch signal is at a third and fourth level, the third level is greater than the first level, and the fourth level is smaller than the second latch level. The second level, the buffer and amplifying the second latch signal to generate a digital signal. A digital analog comparator for converting the digital signal into an analog signal; and an analog buffer for amplifying the analog signal. 9. The data driver of claim 8, wherein the first sampling unit is a P-type transistor, the gate receives the pulse signal, the source receives the data signal, and the drain receives the signal. First sampling signal. 10. The data driver of claim 8, wherein the second sampling unit is a P-type transistor. 11. The data driver of claim 8, wherein the first inverter comprises: a first P-type transistor, the gate receiving the second sampling signal, and the source receiving the first a third level; and 0773-A32083TWF; P2006013: joanne 16 200807356 a first N-type transistor having a gate coupled to the gate of the first P-type transistor and the capacitor unit, the source receiving the fourth bit Precisely, it is not coupled to the drain of the first P-type transistor. 12. The data driver of claim 11, wherein the second inverter comprises: a second P-type transistor, the gate of which is coupled to the drain of the first N-type transistor, The source receives the third level, and the drain is coupled to the capacitor unit; and a second N-type transistor, the gate of which is coupled to the drain of the first N-type transistor, and the source thereof receives the fourth The gate is coupled to the drain of the second P-type transistor. 13. The data driver of claim 12, wherein the first latch unit comprises: a third inverter having a third input and a third output, the third input receiving The fourth sampling signal has a fourth input end and a fourth output end, the fourth input end is coupled to the third output end, and the fourth output end is coupled to the third output end The third and fourth inverters are used to latch the first sampling signal; and a fifth inverter is coupled between the third output terminal and the second sampling unit to generate and output The first latch signal is to the first sampling port - a single port. 14. The data driver of claim 13, wherein the third inverter comprises: 0773-A32083TWF; P2006013: joanne 17 200807356 a third p-type transistor, the gate receiving the first sampling a signal, the source receiving the first level; and a third N-type transistor having a gate coupled to the gate of the first P-type transistor, the source receiving the second level, and the drain The drain of the third P-type transistor is coupled. 15. The data driver of claim 14, wherein the fourth inverter comprises: a fourth P-type transistor, the gate of which is coupled to the drain of the third N-type transistor, The source receives the first level; and a fourth N-type transistor having a gate coupled to the drain of the third N-type transistor, a source receiving the second level, and a drain coupled to the source The > and the pole of the fourth P-type transistor. 0773-A32083TWF;P2006013:joanne 18