200806096丨岭 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種電路板及其品質的管理方法，且 特別是有關於一種具有辨識圖樣的電路板及其品質的管理 方法。 【先前技術】 在科技持續進步的現代生活中，3C電子產品充滿人們 ^生活中。這些電子產品隨著時代潮流不停的改進，並朝 者n短'小的趨勢演變。當人們對電子產品的需求 曰漸增加時’電子產品週邊的諸多構件也跟著大量生產， 其中電路板(Circuit board)便是不可或缺的構件之一。 般而言’f知技術是在—面積較大的基板上，視產 品设計的需求來進彳了相龍的線路層的製程，以形 具有線路層的平板(panel)。其中平祐μ查丨 “ 小的條板㈣），且每崎塊較 完成後續製程後，接著對平板進行切割， 案匕線路 在現今的電路板生產過程當中， 分的可觀。以台灣生產手機電路板的的產量十 下’習知技術通常會對這些用以生產手2大的生產量 是條板進行檢測，以確定生產_ =板的平板或 良率是否符合標準。 一卞板及疋條板之製程的 6 200806096崎 理方法，來作為 分析的依據，並 藉此建立電子化 因此，如何建立一套電路板的品 生產過程中品質管理、進度掌控口、^ 有效掌握f顿生產雜的 ^ f料庫’是目前業界所亟欲達成 【發明内容】 ^ 以有效地掌控電路 本电明之目的是提供一種電路板 板的生產進度。 本&明之另-目的是提供—種電路板品質的管理方 避免在電路㈣加工過財繼續對有瑕_部分進 括一2上其他目的’本發明提出-種電路板，包 :板至夕―線路圖案以及相對應的-辨識圖案，上 述之線路圖案以及辨額案皆位於基板上，其中辨識圖幸 用以代表線路圖案形成後製程的檢驗結果。 —在本發明之一實施例中，上述之辨識圖案選自於文 字、數字、符號及其組合所構成的族群其中之一。 在本發明之一實施例中，上述之基板具有一第一切割 區域，且線路圖案與辨識圖案皆位於第一切割區域内。 在本發明之一實施例中，上述之電路板更包括一第一 切副線。這些切割線位於基板上，並且沿著第一切割區的 輪廓排列。 在本發明之一實施例中，上述之第一切割區域内具有 夕個弟—切割區域，且辨識圖案位於第二切割區域外。 在本發明之一實施例中，上述之第二切割區域的排列 200806096 .doc/g 方式為陣列排列。 f本發明之—實關中，上述之電路板更包括多條第 二切割線，上述之第二切割線位於基板上，且沿著第二切 割區域的輪廓排列。 在本叙明之一貫施例中，上述之辨識圖案的材 在本發明之一實施例中，上述之辨識圖案是適於受一 辨識系統辨識的圖樣。 本發明提出一種電路板品質的管理方法，首先提供一 電路板，電路板包括—絲、—線路圖案以及—辨識圖宰， 其中線路圖案與辨識圖案位於該基板上。接著對線路圖荦 驗步驟，以得到一檢驗結果。之後將檢驗結果儲 存；一貝料儲存單元。爾後再辨識上述之辨識圖案，並且 依據辨硪結果自資料儲存單元讀取檢驗結果。 明之—實施例中，上述之檢驗步驟為自動化光 子欢’、（utomatic Optical Inspection，A0I)步驟。 之線具有辨識圖案，並且此辨識圖樣代表對應 制r中檢驗結果，因此本發明可以在電路板的後續 错由辨識此辨識圖案來隨時獲得線路圖案的檢驗結 疋i本發明可以掌控電路板生產流程的進度與品質。 易惜為：本之上述和其他目的、特徵和優點能更明顯 J如^文特舉較佳實施例，並配合所附圖式，作詳細說 200806096^ 【實施方式】 圖1為本發明一實施例之電路板結構剖面圖。請參照 圖1 ’本貫施例之電路板10包括一基板1〇〇、一線路圖案 ll〇a以及一辨識圖案11〇b。線路圖案n〇a以及辨識圖案 110b白位於基板；1〇〇上，且辨識圖案用以代表線^ 圖案UOa形成後製程的檢驗結果。值得注意的是，在本， 施例中辨識圖案！ 10b是選自文字、數字、符號及其組合ς 構成的族群其中之一，並且辨識圖案11%適於受一辨 統的辨識。 卵μ 以下將對電路板10的製作方法進行詳細地描述。圖 LA至圖2B為本實施例之電路板之製造方法的流程示意 1 回10。’首先提供—基板1 °。。之後將—導電層 二上。導電層iig的材質例如是銅，而 ==方法例如是直接將銅箱(c»oil)貼 =基板⑽上、經由紐法將-銅_成於基板100上 2是其它種細在基板1GGJ1形成 = 置於導一 的方=疋貼附乾膜（dry film)光阻、塗佈光阻或是其他 械#目案化光阻層120a以及 :其中第一圖案化光阻層：二=: ，欲形成之線路層的 應於後__权賴崎的雜== 200806096^ 施例可以經由將_雷射光照射於 射於光阻層12。的部 t 光照 -圖案化光阻層12 中,先罩具有對應於第 接々/么 乂及弟一圖案化光阻層120b的F1 樣。之後，對光阻層12 勺圖 圖案化光阻層120a以月^ =、、員〜衣私’以形成第一 此外以及一弟二圖案化光阻層120b。 曝光外，、衰例除了可以經由光罩對光阻層120進行 * k σ以經由雷射光束對光阻層120進彳fβ 以相較於光罩而古，太…進仃曝先。是 為精細且較為複由雷射光束來形成較 案化光阻層^ 圖案化光阻層⑽以及第二圖 射先ft ΪΪ的微影製程’亦可以同時採用光罩以及雷 以及第二圖案化光阻層！薦开其成*圖=光阻層1施 以形成第-圖案化光阻芦12 貝=可以經由光罩 曰並且經由雷射#蚩爽带成 圖木=精細且較為複雜的第二_化光阻層隱。/ 声施t/itm進⑽刻’並且將第一圖案化光阻 ^w案化光阻層⑽剝除，以形成如圖 :不的電路板1〇。更詳細地說，本實施例是以第一圖案 、二曰1施以及一第二圖案化光阻層12此為罩幕，對 2 g 110進订|虫刻’以形成一線路圖案n〇a以及一辨識 ，木腾。之後將第1案化光阻層驗以及一第二圖 案化光阻層·剝除以形成線路板10。此外，本實施例 更可以將一知罩層（未緣示)配置於線路圖案11 〇a以及辨識 圖案11Gb上’其中焊罩層暴露出辨識圖案丨⑽以及線路 10 200806096— 圖案ll〇a的部分區域。 另外，本實施例之第一圖案化光阻層12如以及一第 二圖案化光阻層邊除了可以經由微影製程的方式而被 f成於導電層11G上之外，還可以經由喷墨的方式形成於 V電層110上。請參照圖3，其為本實施例之另一種形成 第二，案化光阻層120a與第二圖案化光阻層12〇b的方法 的示W圖首先提供一基板100。之後將一導電層11〇配 置於^板100上。然後以喷印(ink-jet printing)的方式，直 ⑩接將第一圖案化光阻層12〇a與第二圖案化光阻層12〇b形 成於導電層110上。更詳細地說，本實施例是經由一喷墨 ，200將光阻材料210形成於導電層11〇上，以直接形成 第一圖案化光阻層12〇a與第二圖案化光阻層12〇b。 當然，本實施例中更可以經由前述的微影製程，先在 導電層no上形成第一圖案化光阻層12〇a。之後再經由喷 墨頭200,將第二圖案化光阻層12%形成於導電層上。 -圖4A至圖4B為圖1之電路板的另一製造方法的流程 • 示意圖。請參照圖4A，首先提供一基板100。之後將一導 毛層110配置於基板100上。之後，經由前述的微影製程， 在導電層110上形成第一圖案化光阻層施'然後，以第 一圖案化光阻層120a為罩幕，對導電層11〇進行蝕刻，以 12〇a|)J^〇 明茶考圖4B，接著經由噴墨頭2〇〇將塗料21〇喷印於基板 則上，以形成圖1所示的電路板1G，其中辨識圖案聰 是由塗料220所形成。值得注意的是，上述的塗料210是 200806096.〇〇/§ 基板1〇0的顏色有明顯差異之材料，1中- 製程上4:=:=::，方法在 並且可視㈣需加二= 圖案的材質包括銅或塗料等 卜辨識 設計的不同而加以改變。辨_材料’亦可隨製程[Technical Field] The present invention relates to a circuit board and a quality management method thereof, and more particularly to a management method for a circuit board having an identification pattern and its quality. [Prior Art] In the modern life of continuous technological advancement, 3C electronic products are filled with people's lives. These electronic products have been constantly improving with the trend of the times, and have evolved toward a short 'small trend. When people's demand for electronic products is gradually increasing, many components around the electronic products are also being mass-produced, and the circuit board is one of the indispensable components. Generally speaking, the technology is on the substrate with a large area, and the process of the circuit layer of the phase is carried out according to the design requirements of the product, so as to form a panel having a circuit layer. Among them, Pingyou μ 丨 小 “small slats (4)), and after each subsequent block of the subsequent process, the slab is cut, and the case line is in the production process of today's circuit board, which is quite impressive. The production of the board is ten times. [The conventional technology usually tests the production of these two large production lots to determine whether the production plate or the yield of the board meets the standard. The method of stripping the process of 2008 20089696 is to be used as the basis for analysis, and to establish electronicization. Therefore, how to establish a set of circuit board production quality management, progress control, ^ effective mastery of production The ^f library' is currently the industry's desire to achieve [invention content] ^ to effectively control the circuit of this electric purpose is to provide a circuit board production progress. This & Ming is another - the purpose is to provide a kind of circuit board The management of the quality avoids the processing in the circuit (4). The continuation of the 瑕 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The identification pattern, the above-mentioned circuit pattern and the identification case are all located on the substrate, wherein the identification map is used to represent the inspection result of the post-pattern forming process. - In an embodiment of the invention, the identification pattern is selected from the In one embodiment of the present invention, the substrate has a first cutting area, and the line pattern and the identification pattern are both located in the first cutting area. In an embodiment of the invention, the circuit board further includes a first nip line. The dicing lines are located on the substrate and are arranged along the contour of the first cutting area. In an embodiment of the invention, the above In the first cutting area, there is a mating-cutting area, and the identification pattern is located outside the second cutting area. In an embodiment of the invention, the arrangement of the second cutting area is 200806096 .doc/g. In the present invention, the circuit board further includes a plurality of second cutting lines, and the second cutting line is located on the substrate and along the second cutting area. In the consistent embodiment of the present invention, in the embodiment of the present invention, the identification pattern is a pattern suitable for recognition by an identification system. The present invention provides a circuit board. The quality management method firstly provides a circuit board including a wire, a line pattern, and an identification pattern, wherein the line pattern and the identification pattern are located on the substrate. Then the line drawing step is performed to obtain a test result. After that, the test result is stored; a bunker storage unit is then identified by the above identification pattern, and the test result is read from the data storage unit according to the identification result. In the embodiment, the above test step is automated photonics (utomatic Optical Inspection, A0I) step. The line has an identification pattern, and the identification pattern represents the inspection result in the corresponding system r, so the present invention can obtain the line pattern inspection at any time by identifying the identification pattern in the subsequent error of the circuit board. Conclusion i This invention can control the progress and quality of the board production process. It is to be understood that the above and other objects, features and advantages of the present invention will be more apparent. The preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. A cross-sectional view of a circuit board structure of an embodiment. Referring to FIG. 1, the circuit board 10 of the present embodiment includes a substrate 1A, a line pattern 11a, and an identification pattern 11b. The line pattern n〇a and the identification pattern 110b are white on the substrate; 1 ,, and the identification pattern is used to represent the inspection result of the post-process of the line pattern UOa. It is worth noting that in this example, the pattern is recognized! 10b is one of a group selected from the group consisting of a character, a number, a symbol, and a combination thereof, and the identification pattern 11% is adapted to be recognized by a recognition. Egg μ The method of manufacturing the circuit board 10 will be described in detail below. FIG. LA to FIG. 2B are flowcharts 1 to 10 of the method for manufacturing the circuit board of the embodiment. 'First provided - substrate 1 °. . After that - the conductive layer is on the second. The material of the conductive layer iig is, for example, copper, and the == method is, for example, directly attaching a copper box (c»oil) to the substrate (10), forming a copper-based layer on the substrate 100 via a New method, and the other is fine on the substrate 1GGJ1. Formation = Placed on the lead = 疋 attached dry film photoresist, coated photoresist or other mechanical #mesh photoresist layer 120a and: wherein the first patterned photoresist layer: two = : The line layer to be formed should be after the __ right Laiqi's miscellaneous == 200806096^ The embodiment can be irradiated onto the photoresist layer 12 by irradiating _ laser light. In the portion t-illumination-patterned photoresist layer 12, the first mask has an F1 pattern corresponding to the first and second patterned photoresist layers 120b. Thereafter, the photoresist layer 120 is patterned on the photoresist layer 12 to form a first and a second patterned photoresist layer 120b. In addition to the exposure, the fading can be performed by performing a *k σ on the photoresist layer 120 via the reticle to introduce 彳fβ into the photoresist layer 120 via the laser beam to be compared with the reticle. It is a fine and relatively complex laser light beam to form a patterned photoresist layer (the patterned photoresist layer (10) and the second image of the first ft ΪΪ lithography process can also use the reticle and the lightning and the second pattern Photo resist layer! Recommended to open * map = photoresist layer 1 applied to form the first - patterned photoresist Reed 12 shell = can be through the mask 曰 and via the laser #蚩爽带成图木 = fine and more complex second _ The photoresist layer is hidden. / Sound t/itm into (10) engraved and stripped the first patterned photoresist photoresist layer (10) to form a circuit board as shown in FIG. In more detail, in this embodiment, the first pattern, the second pattern, and the second patterned photoresist layer 12 are used as a mask, and the 2 g 110 is ordered to be inscribed to form a line pattern. a and a recognition, Mu Teng. Thereafter, the first patterned photoresist layer and a second patterned photoresist layer are stripped to form the wiring board 10. In addition, in this embodiment, a mask layer (not shown) can be disposed on the line pattern 11 〇a and the identification pattern 11Gb, wherein the solder mask layer exposes the identification pattern 10 (10) and the line 10 200806096 - the pattern 〇 〇 a partial area. In addition, the first patterned photoresist layer 12 and the second patterned photoresist layer of the embodiment may be formed on the conductive layer 11G by means of a lithography process, and may also be inkjet. The manner is formed on the V electrical layer 110. Referring to FIG. 3, another embodiment of the method for forming the second, patterned photoresist layer 120a and the second patterned photoresist layer 12B is first provided with a substrate 100. A conductive layer 11 is then placed on the board 100. Then, the first patterned photoresist layer 12A and the second patterned photoresist layer 12A are formed on the conductive layer 110 by ink-jet printing. In more detail, in this embodiment, the photoresist material 210 is formed on the conductive layer 11 via an inkjet, 200 to directly form the first patterned photoresist layer 12a and the second patterned photoresist layer 12. 〇b. Of course, in the embodiment, the first patterned photoresist layer 12〇a may be formed on the conductive layer no via the aforementioned lithography process. Thereafter, a second patterned photoresist layer 12% is formed on the conductive layer via the ink jet head 200. - Figure 4A to Figure 4B are flow diagrams of another method of manufacturing the circuit board of Figure 1. Referring to FIG. 4A, a substrate 100 is first provided. Then, a hair guiding layer 110 is disposed on the substrate 100. Thereafter, a first patterned photoresist layer is formed on the conductive layer 110 via the lithography process described above, and then the conductive layer 11 is etched with the first patterned photoresist layer 120a as a mask. a|) J^〇明茶考图4B, and then the coating material 21〇 is printed on the substrate via the inkjet head 2〇〇 to form the circuit board 1G shown in Fig. 1, wherein the identification pattern is made of the paint 220 Formed. It is worth noting that the above coating 210 is 200806096. 〇〇 / § The material of the substrate 1 〇 0 has a significant difference in the color, 1 - process on the 4: =: =::, the method is in and visible (four) need to add two = The material of the pattern is changed by the difference in design of copper or paint. Identify _materials can also follow the process
夫上為太本5明另—實施例之電路板結構的剖面圖。請 =圖5，本貫施例之電路板結構3〇包 =案·、一辨識圖案320、多個第一崎 342 °其中線路圖案31G、辨識圖案 320、弟-切麟332以及第二切割、線如皆位於基板· 上，且賴圖案320用以代表線路圖案31〇的檢驗結果。 —與所述實施解_是’本實關之電路板結構具有 了第:切割區域330’其中線路圖案31〇、辨識圖案32〇 以及第二切割線342皆位於第一切割區域33〇内，而第一 切割線332，則是沿著第一切割區域33〇的輪廓排列。 此外，第一切割區域33G内具有多個第二切割區域 340，上述之辨識圖案320位於第一切割區域.％〇内，但位 於第二切割區域340之外。第二切割線342，則沿著第二 切割區域340的輪廓排列。 由上述可知，若沿第一切割線332進行切割，便可將 第一切割區域330自基板300上分離。在本實施例中，電 路板具有一個第一切割區域330，而在其他實施例中，第 12 200806096J〇c/g 一切剔區域330的數量則可視設計所需加以調整。 明、續參照圖5 ’在本實施例中，第二切割區域340 的排列方式為陣列排列（area array)，然而在其他實施例 中，亦可以為其他排列方式，例如是任意排列或交叉排列。 此外若〜第一切割線342進行切割，則可以不包括辨識 圖案320而將第二切割區域mo自第一切割區域中分 _以進行後續製程。在其他實施例中，第二切割區域340 的數量亦可以視設計所需而調整。 馨 f述實施例不_是，在本實施例之電路板結構 中，第一切割區域330内具有多個線路圖案310，辨識圖 案320亦可代表整個第一切割區域330之檢驗結果。換句 話說一個辨識圖案320並非僅能代表一個線路圖案31〇， 亦可視電路板與檢驗倾的設計，調整賴®案320所代 表的線路圖案31〇的範圍。 圖6為本發明一實施例之電路板品質的管理方法示意 圖。請參照圖6，以電路板10為例，首先將一電路板1〇 φ 置於一辨識系統410内，其中電路板10包括一基板10〇、 一線路圖案110a以及一辨識圖案11〇b。在本實施例中， 辨識系統410為一自動光學檢測系統，其中此自動光學檢 測系統包括一影像擷取裝置例如是電荷耦合元件(charge Coupled Devices ’ CCD)，用以擷取電路板1〇上線路圖案 110a與辨識圖案li〇b的影像。 ” 請繼續參照圖6,接著辨識系統410對電路板1〇進行 一檢驗步驟，以得到一檢驗結果。值得注意的是，此檢驗 13 'loc/g 200806096^ 二。驟可以是對線路圖案ma進行檢驗，或 木UOa後之製程進行檢驗。之後將所得于驗^敦路圖 於一資料儲存單元420中。在本實施例中， Γ存^伽也可以是光碟或是記憶體等資2存^ 综上所述，本發明之電路板 件’且各辨識圖案可代表對應之的： ==:=案，讀取資料儲存單 度2、ί=ΓΓ果’藉此追縱、管理電路板的進 度/、口口貝，亚由此建立Ε化的電子資 适 由辨二產過程中，可隨時'經 ㈣Q累，5貝取對應之電路板上線路圖案之檢驗 中，八二可以在電路板的後續製程或是下游廠商的製程 =辨出平板或是條板的哪個部分具有瑕疲，進而可避 的節1瑕_部分進行加工’有助於時間成本與製造成本 此外d為本發明之辨識圖案可對應於各線路圖 圖:對應於數個線路圖案’可視設計所需而調整，且辨識 方法可為喷印法或f射曝光法’亦可視製程所 =選擇應用’所以本發明之辨識圖案在製程上具有彈性 的空間，適於應躲不同的電路板製程中。 14 200806096d〇c/g 雖然本發明已以較佳實施例揭露如上，妙 限定本發明，任何熟習此技藝者，在不 ^教非用以 和範圍内，當可作些許之更動與潤飾，因=明之精神 範圍當視後附之申請專利範圍所界定者為準。x明之保護 【圖式簡單說明】 圖1為本發明一實施例之電路板結構剖面圖。 圖2A至圖2B為本實施例之電路板之製造方法的流程 示意圖。 圖3為本實施例之另一種形成第一圖案化光阻層與第 一圖案化光阻層的方法的示意圖。 圖4A至圖4B為圖1之電路板的另一製造方法的流程 示意圖。 圖5為本發明另一實施例之電路板結構的剖面圖。 圖6為本發明一實施例之電路板品質的管理方法示意 圖。 【主要元件符號說明】 100、300 :基板 110 :導電層 110a、310 ··線路圖案 110b、320 :辨識圖案 120a :第一圖案化光阻層 120b :第二圖案化光阻層 200 :喷墨頭 210 :塗料 15 200806096i〇〇/g 330 :第一切割區域 332 :第一切割線 340 ··第二切割區域 342 ··第二切割線 410 :辨識系統 420 :資料儲存單元The above is a cross-sectional view of the circuit board structure of the embodiment. Please refer to FIG. 5, the circuit board structure of the present embodiment 3 package = case, an identification pattern 320, a plurality of first 342 °, wherein the line pattern 31G, the identification pattern 320, the brother-cutting 332 and the second cutting The lines are all located on the substrate, and the dashed pattern 320 is used to represent the inspection result of the line pattern 31〇. - with the implementation solution _ is 'the actual circuit board structure has a: cutting area 330' wherein the line pattern 31 〇, the identification pattern 32 〇 and the second cutting line 342 are located in the first cutting area 33 ,, The first cutting line 332 is arranged along the contour of the first cutting area 33〇. Further, the first cutting area 33G has a plurality of second cutting areas 340, and the above-mentioned identification pattern 320 is located in the first cutting area .%, but outside the second cutting area 340. The second cutting line 342 is then aligned along the contour of the second cutting area 340. As can be seen from the above, the first cutting region 330 can be separated from the substrate 300 by cutting along the first cutting line 332. In this embodiment, the circuit board has a first cutting area 330, and in other embodiments, the number of all the tick areas 330 of the 12 200806096J〇c/g can be adjusted as desired by the design. Referring to FIG. 5 'in this embodiment, the second cutting area 340 is arranged in an array, but in other embodiments, other arrangements may be used, such as arbitrarily arranged or cross-arranged. . In addition, if the first cutting line 342 is cut, the second cutting area mo may be divided from the first cutting area without the identification pattern 320 for subsequent processing. In other embodiments, the number of second cutting regions 340 can also be adjusted as desired by the design. In the circuit board structure of the present embodiment, the first cutting area 330 has a plurality of line patterns 310, and the identification pattern 320 can also represent the inspection result of the entire first cutting area 330. In other words, an identification pattern 320 does not only represent a line pattern 31〇, but also a circuit board and inspection tilt design, and adjusts the range of the line pattern 31〇 represented by the Lai® 320. Fig. 6 is a schematic view showing a method of managing the quality of a circuit board according to an embodiment of the present invention. Referring to FIG. 6, taking the circuit board 10 as an example, a circuit board 1 〇 φ is first placed in an identification system 410. The circuit board 10 includes a substrate 10A, a line pattern 110a, and an identification pattern 11b. In the present embodiment, the identification system 410 is an automatic optical detection system, wherein the automatic optical detection system includes an image capturing device such as a charge coupled device (CCD) for capturing the circuit board 1 The line pattern 110a and the image of the recognition pattern li〇b. Please continue to refer to FIG. 6, and then the identification system 410 performs a verification step on the circuit board 1 to obtain a test result. It is worth noting that the test 13 'loc/g 200806096^ 2 may be the line pattern ma After the inspection, or the process after the wood UOa is carried out, the inspection is carried out in a data storage unit 420. In this embodiment, the storage can also be a CD or a memory. In summary, the circuit board of the present invention' and each identification pattern can represent a corresponding one: ==:= case, reading data storage unitiness 2, ί=ΓΓ果' thereby tracking, managing circuit The progress of the board /, the mouth of the shell, the sub-establishment of the e-sufficiency of the electronic resources by the identification of the second production process, can be at any time (four) Q tired, 5 shells corresponding to the circuit board on the circuit board inspection, 82 can be Subsequent process of the board or the process of the downstream manufacturer = Identify which part of the plate or strip is exhausted, and then avoid the section 1瑕_ part of the processing 'helps time cost and manufacturing cost The identification pattern of the invention can correspond to each line map: Adjusted for several line patterns 'visual design, and the identification method can be spray printing or f-exposure method' can also be used to select the application. Therefore, the identification pattern of the invention has a flexible space in the process. The present invention has been disclosed in the preferred embodiments as described above, and the present invention is not limited to the scope and scope of the present invention. When a few changes and refinements are made, the scope of the spirit of the invention is defined by the scope of the patent application. The protection of the invention is as follows: Figure 1 is a schematic diagram of a circuit board structure according to an embodiment of the invention. 2A to 2B are schematic flowcharts of a method for manufacturing a circuit board of the embodiment. FIG. 3 is a schematic diagram of another method for forming a first patterned photoresist layer and a first patterned photoresist layer according to the embodiment. 4A to 4B are schematic flow charts showing another manufacturing method of the circuit board of Fig. 1. Fig. 5 is a cross-sectional view showing the structure of a circuit board according to another embodiment of the present invention. Fig. 6 is a circuit board quality according to an embodiment of the present invention. of Schematic diagram of the method. [Main component symbol description] 100, 300: substrate 110: conductive layer 110a, 310 · line pattern 110b, 320: identification pattern 120a: first patterned photoresist layer 120b: second patterned photoresist layer 200: inkjet head 210: paint 15 200806096i〇〇/g 330: first cutting area 332: first cutting line 340 · second cutting area 342 · second cutting line 410: identification system 420: data storage unit