TW200805679A - Memory devices - Google Patents

Abstract

Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, -Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).

Description

200805679 P940260 19580twf.doc/e IX. INSTRUCTIONS: This application is related to the application of US Patent No. 940222 (11/425482), which is filed concurrently and at the same time, and whose name is "Methods and Structures for Expanding a". Memory, Operation Window and Reducing a Second Bit Effect", created by Wu Zhaoyi, is owned by the applicant of this application. This application is related to the application of the US Patent No. 940,233 (11/425,523), which is hereby incorporated by reference in its entirety in

Window’’, created by Wu Zhaoyi, is owned by the applicant of this application. This application is related to the application of U.S. Patent No. 940,259 (11/425,541), which is filed concurrently and at the same time, the name of the invention is: Ding, p Dielectric Structures in Memory Devices and Methods for

Expanding a Second Bit Operation Window,,, was created by Wu Zhaoyi and owned by the applicant of this application. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to electrically programmable and erasable memory, and more particularly to the use of memory for operation in the operation of a single memory cell. The method and components of the second bit effect. [Prior Art]: Electro-programmable and erasable volatile memory-based technology based on charge storage structures known as electrically erasable programmable read-only memory (eepr〇m) and flash memory A variety of modern applications. The flash memory is designed to have a memory cell array that can be independently programmed and read, 19580 TW/doc/200805679. A sense amplifier (SenseampHfier) in the flash memory can be used to determine the value (one or more) of the data stored in the non-volatile memory. In a typical sensing scheme, the current sense amplifier compares the current flowing through the positively sensed memory cell with the reference current. Many memory cell structures are used in EEPROM and flash memory. As the size of the integrated circuit is reduced, due to the scalability and simplicity of the manufacturing process, the memory cell structure based on the charge trapping dielectric layer is being more concerned. The memory cell structure based on the charge trapping dielectric layer contains industrial names such as Nitride Read-Only Memory, semiconductor-oxide-nitride-oxide-semiconductor (s〇N〇s), and A structure known as a patterned electronic memory (pHINES) by injecting a nitride through a thermoelectric hole. These memory cell structures store data by trapping charges in a charge trapped dielectric layer (e.g., tantalum nitride). When trapped in a negative charge, the threshold voltage of the memory cell increases. By removing the negative from the charge trapping layer, the threshold voltage of the memory cell is reduced. "When I use a nitride-only read-memory device, the bottom oxide =, point, and loss are relatively thick (for example, nano' and usually about 5 to 9 nm). Instead of straight: tunneling, Can be used, between the belts ^ hole injection ((4) Qing) to erase the memory cells. However, _, = V cooked to damage the oxide, resulting in high threshold voltage memory cells in the low-voltage I hope that the charge gain in the cell will be remembered. In addition, it is difficult to erase the accumulated and accumulated, the stylized and the second, the incoming junction will gradually increase. This charge accumulation is due to the band, the same, the = work When erasing 6 200805679 F^40Z6U 195S0twidoc/e The injection points are not related to each other and after the erasing pulse. - In addition, in the nitride reading only, _々: Butterfly ^ and Xinsheng Beikou has U version of Shaanxi During the erasing period of the flash memory component: the erasing speed of each memory cell differs due to process variations (for example, channel length variations). This erases the read to the original, the previous, Vf, ,, and eliminates The difference in twist results in the erased state of the AVt knife cloth. Among them, some memory cells become difficult to erase - some memory cells are = Wipe this. After this, after several passes and wipe _ ring, the eye is repeatedly Vt margin off, and the view _ poor durability.

It will become more serious when the scale is reduced proportionally. Conventional floating closed-loop components store a single-element charge in a conductive floating gate. A nitride read-only memory cell has emerged in which each-nitride-read memory cell provides a two-bit flash memory cell that stores charge in an oxygen-nitride/oxide/germanium dielectric. In the vapor-only read memory memory typical structure towel, the nitride element is positioned at the top of the oxide layer and the bottom oxide layer. The electric radiation of the 0Ν0 dielectric wipe with the nitride layer is trapped on the left side of the nitrided cell (i.e., the left bit) or the right side, the right bit). ^ The bit is applied, affecting the right bit, or vice versa, this is known as the second bit = effect. The second bit effect affects the operation of nitride-reading memory cells. A commonly used technique for memory-like memory in a stylized nitride-reading memory array is the hot electron injection method. A common technique used to erase memory cells during the erase operation is called band-to-guide band wear and thermoelectric hole entry. The inherent problem of the second valued effect affects the operational margin. The second bit effect is caused by the interaction of the left bit in the memory cell of the nitride read-only memory with the TO of the right 7 200805679 P940260 19580twf.doc/e. It is desirable to have a memory operation margin to significantly reduce the second bit effect. [Inventive content], "How to increase the memory operation margin in a plurality of records, do, +, 夕如^曰 ° 〖 〖 版 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆 忆Dust + Vg will memory the memory of the cell to get the charge into the disciplinary, negative voltage level. Increase the coffee operation margin 2; kg = charge into memory erased below the initial threshold voltage: : Voltage level is achieved. The charge is trapped in the body of the body = ^ square ί or erased as the servant of the first ship boundary light (four) f pressure value of the two *^, ^«, aurn.onmode) (TOMf^-- The undivided method can be performed before the facetization step (ie, pre-stylized wipe or after the stylization step (ie, post-programmatic erase operation).], operation = two embodiments of the invention are illustrated The secrets of the exemplary erasing room include (4) the injection operation and the _- conduction belt to positively erase the knowledge. In the first embodiment, the hole is injected into the Μ: pressure The hole tunneling of the row is used to erase the charge and get into the memory. In the case of If:, the hole is injected to remove the charge trapped memory by the hole in the negative voltage. In the third embodiment中, 8 200805679 P940260 39580twf.doc/e The hot-hole operation between the band and the conduction band ^ The charge is trapped in the memory and is erased into memory. A program suitable for operations involving the integration of electronic (coffee) reading. Chemical Technology Initial 4 =: 适 秘 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ As in the read 〇s memory element, the charge trapping layer is in the dielectric layer disposed above the charge trapping layer in the p&I s J. The 矽 layer is formed above the charge trapping layer on the day and night. The addition of an + oxide structure enables easy implantation of a hole from a polycrystalline in-layer. The second aspect of the present invention describes a metal nitride-oxide- =======(_s_s(6) structure Memory element ^ reduces the effect of a sputum while increasing the memory Operating margin. In the case where the gate bias voltage Vg is applied, in the source region and the non-polar region 3, iHMNC) s. the memory includes a charge trap on the channel, where 电荷' where the charge trapping structure is included in the dielectric The memory element above the layer is implemented on a metal_oxide-nitride-oxidation=+conductor' insulator including a charge trapping structure having an oxide-nitride stack. MONOS.) In memory, the suitable material for dreams consists of shame stone eve (sounding can be: Shi Xi 〇 life, ρη,, / one person 7th day 甩 甩 牙 抹 或 or can bring _ The combination of the thermoelectric holes in the conduction band and the wiper channel thermal electron technology is applied. Wood 9 200805679 F940260 19580twf.doc/e In a third aspect of the invention, a memory element of a metal-nitride-oxide-nitride-oxide-semiconductor (MN0N0S) structure is described, which uses an on-mode method The operating margin is increased while reducing the second bit effect. The MNONOS memory structure includes a top oxide structure having a tantalum nitride layer on the dielectric layer. Alternatively, the memory element is implemented in a metal-oxide-nitride-oxide-nitride_oxide__semiconductor having a top oxide structure of an oxide-nitride-oxide stack (m〇n〇n 〇s) in the structure. The memory element having the top oxide structure can also be implemented on the thin film transistor (TFT) structure by fabricating the memory element on the polysilicon substrate instead of the clothing; The components of the component are & MNQNQS TFT recording structure and mqn〇n〇s TFT memory structure. The hole tunneling wire or the bandable tape can be applied in combination with channel thermal electronics. The turn-on mode operation can utilize both high-voltage memory operation and low-voltage memory operation. In the low-voltage memory, the erase operation can be performed by adding or applying voltage. In the fourth aspect of the present invention, a charge-trapping body of a metal-oxide-nitriding emulsion-magnification-semiconductor (M〇N〇NS) structure is described. The older margin money II = $iil°MQNC) NS memory structure consists of a bottom oxide structure with a layer of nitrogen. Alternatively, the memory is in the bottom oxide shell with an oxide/nitride-oxide stack = in the MOMCWOS structure. It is also possible to make a memory element on a thin film transistor (TFT) structure by making a memory element on a substrate instead of a shredded wire, and having a bottom oxide system. Therefore, other implementations of the body element include M-ca NS TFT memory and = graph S = memory structure. In a further embodiment, the electrical inclusion includes a charge on the stone substrate, a m(10)) structure, or a dielectric on the polycrystalline substrate. Material (M(HK)NQSTFT structure> The erase hole erase operation between the hole penetration guide can be performed with the channel 哉 optional = about plus or minus the voltage to implement the memory for the charge trapping memory The method of increasing the 钿 钿 亚 亚 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小 减小It can be more clearly as follows. The cattle are well-connected, and in conjunction with the drawings, a detailed description of the [embodiment], i to Figure 34' provides a structural example and method for the present invention. Restricted to the implementation of mosquitoes:: and = can be expressed using other features, components, methods. Inflammation. Similar elements in various embodiments - generally similar reference structure view 'Please refer to Figure U' A simplified structural diagram of s, ', orbital charge trapped in memory cell 100. The trap 200805679 P940260 19580twf.d〇c/e=hex=1〇〇 has a p-type substrate with n+ doped regions 112 and 114, and the dielectric structure 12〇 (bottom oxide) covers the p-type substrate (10), 12( Γ,: the structure 130 (for example, a tantalum nitride layer) covers the bottom dielectric structure, the Thunder v ^ type polycrystalline layer, just covering the charge trapping structure 13 〇. Applying the gate 152 ^ Γ Γ to the Ρ type (4) The layer is paired, and the substrate voltage Vsub is mixed to the P-type substrate 110. The immersion voltaic Vd 156 is applied to the n+ doping "good, and the source voltage Vs 158 is applied to the n+ tweeting region ι ΐ 2. The MN 〇s structure in which the charge is trapped in the memory cell 100 is the other one that can implement the charge trapping structure in the case where the real oxidation _11=1== has a _ partial oxide, and the bismuth bismuth two = two:: Combination, '1 compound-oxide_0' stacking a wide variety of materials to implement P-type polycrystalline stone = 40 曰 或 or metal Figure 1B illustrates the charge into the memory cell 100 through the right bit 162 ^ = two U I, to programmatic hot electrons are applied to the right bit 162_Γ, °; ^ Μ 16 () indicates the channel sub-edge. Apply 8: volt gate voltage ^ ' Ρ = 电 in the memory. The pass of the right bit in the middle of the switch is switched between the drain and the source region 112. The input of the memory in the memory 100 is a staggered implementation of the charge trap. Figure 1C is a diagram illustrating the stylization of charge maps through the 203805679 P940260 19580 twf.doc/e left 兀 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The second position, such as the pressure vg 150, Shi Zhi 〇 you know the addition of 8 volt gate electric: Λ: special finite voltage Vd 156, apply 5 volts two M Vs 158 'and apply (four) special basal plane v 2 source The pole rf (four) causes the charge to fall into the left bit of the memory cell = the application of the dice ^: is the positive threshold voltage + Vt. , ^- This hot injection ==:= into the hole in the channel area of the memory cell 1 〇 °, ^ (four), Ϊ map. The term "hole injection, also known as: two-input erase is usually not a conventional eraser 2: mouth force 乂 ==== =, used in memory cells as used herein, stylization involves reduction The critical voltage of the memory cell. == : ============================================================================================= The voltage product and the apparent top dielectric f comprise 4 (four) Miuu's with a thickness of about 5 to 10 nm or other similar 13 200805679 P940260 19580twf.doc/e dielectric constant materials including, for example, A12〇3. Representative bottom dielectrics include thick oxygen and oxygen oxynitride, or other _"electrically representative charge trapping structures containing a thickness of about 3 to 9 showing the unresolved fossils, including, for example, A1203, Hf02, Ce02 Other similar high dielectric constant materials 2 and II of the metal oxides thereof are discontinuous collections of agglomerated or granular charge trapping materials, or continuous layers as shown in the middle. The electric turnover structure m has a charge that is trapped, for example, by an electron. Green, please refer to FIG. 2, which illustrates the first embodiment of the erasing method. The wiping method applies a positive gate voltage by using a closed gate voltage from the 〇N〇s memory 2〇〇. The memory hole of the memory is erased as a negative threshold voltage. The memory layer 2 includes a charge trapping structure 212 of the dielectric layer 210, and a second dielectric layer 214-type polysilicon layer 22 covering the charge trapping junction 212 in the second dielectric layer. 14 on. The high bias applied to the gate terminals results in band distortion such that the second dielectric layer 214 may be thinner in certain regions to allow the holes to penetrate the second dielectric ^=4. When a high bias is applied to the gate terminal in the n-type polysilicon layer 22A, the gate terminal (indicated by arrows 240a, 240b) passes through the second dielectric layer 214 and injects the hole into the charge trapping structure 212. . The second dielectric 214 can be selected to be thin enough to tunnel through the second dielectric layer 214. A gate voltage Vg 23 施加 of a positive voltage of 16 volts is applied, a 4-inch drain voltage column 234 is applied, a volt-volt source voltage Vs 236 is applied, and a volt-volts substrate voltage Vsub 232 is applied. The combination of these applied voltages is led to = hole tunneling erase of the SONOS memory 200 to become a negative threshold 14 200805679

Py4U260 〗 〖9580twf.doc / e 伹兀 电 屡 -Vt ' thereby increase the § memory memory margin and reduce the structure of the second embodiment of the erase method is not illustrated in Figure 3, The erase method causes the memory cell to become a negative threshold voltage by applying a negative gate voltage from the substrate of the SONOS memory cell 300 to the SONOS memory cell. The SONOS memory cell 300 includes a charge trapping structure 312 covering the first dielectric layer 310, and a dielectric layer 3141 type polysilicon layer 32 covering the charge trapping structure 312 on the second dielectric layer 314. The high negative bias applied to the substrate 302 results in a band-stable change from 31 可能 in some regions that may be thin to allow the hole to penetrate the first dielectric layer 3iM to apply a high negative offset _ 30 from the substrate 3 〇2 (by arrow 3, ♦ n through ί a dielectric layer 310 and to the charge trapping structure 312 pair = dielectric layer 31G can be selected to be sufficiently thin, so that my brother, the electric layer 310 performs the hole penetration Extreme Vg 330, the application of the twist causes the memory of the S0N0S to be electrically ===; the boundary voltage, thereby increasing the memory gymnastics; Fig., ====!; _ the structure of the embodiment of the thermal conduction between the conduction bands Put the second two, explain the SONOS memory cell _ : 贝 ^ 电屋. Figure 4A

The erasing operation of S_S memory cell _ = is illustrated, and Figure 4B uses energy band-axis_electric_ to ^200805679 P940260 I958〇twf.doc/e 极极电Vd 434 and applies G volt source hole toward The charge traps the right _ 436 of the structure 41〇 so that when the power is erased from the left position it, the opposite state is opposite to the 3 4& =: When erasing the left bit, the Shi-Volt source is indicated by the second element. In the right position and applied. Volts = L = 8 volts _ ~ 30 or, in the first, second and third embodiments, the memory erase is below the initial critical power two' instead of being erased to the negative critical Vt. Although the above-mentioned borax; Lai is also in the present invention, it is expected that the charge of the 包含 丨 包含 包含 contains the SONOS type or TFT-SONOS memory.

As shown in FIG. 5, it is a flow chart of the process 5GQ in the first embodiment of the first embodiment, which is transmitted through the use of channel thermal electron technology. Dereliction of duty 1 cell 300. At step 520, the S〇N〇S memory cell is erased = ^ threshold voltage by applying a positive gate voltage from the gate terminal. The S〇NOS memory cell 300 is erased to a negative threshold voltage to restore the memory margin and reduce the second bit effect. Alternatively, the S0N0S memory cell is erased by applying a positive closed-pole voltage ' from the terminal: a voltage level lower than the initial threshold voltage. ..., and in FIG. 6, the flow is illustrated in the second embodiment of the second embodiment of the method for erasing the negative gate voltage by using the channel thermal electron technology. s〇N〇s memory cell 300. At step 620, the SONOS memory cell 300 is erased to a negative threshold voltage by applying a negative gate voltage that causes the hole to be erased from the substrate. Erasing the SONOS memory cell 300 to a negative threshold voltage increases the memory operation margin while reducing the second bit effect. Alternatively, § MSC 300 is erased to a voltage level lower than the initial threshold voltage by applying a negative gate voltage from the substrate of SONOS § MSC 300.

Figure 7 is a flow diagram illustrating a flow 700 in a third embodiment of an erase method that is performed by a thermal hole erase between an energy band and a conduction band. At step 71, the S〇N()s memory cell 3(8) is fibrillated using channel thermal electrons. At + 720, the memory cell 300 is erased to a negative threshold voltage by using a thermal hole erase between the band and the conduction band. The erase operation of dividing the s〇N〇s memory cell into a negative threshold voltage increases the A memory miscellaneous margin and reduces the second bit effect. Alternatively, the SONOS memory 16 is erased to a voltage lower than the initial threshold voltage by using the thermal hole erasing between the band and the conduction band. FIG. 8A is a stylized diagram of the left bit in the 匪0S structure. Figure 8B is a corresponding diagram illustrating the second bit effect (in this example, the operation margin of a single § recall cell two-bit representing the right-valued element. The second bit? should occur using a single-memory cell two-bit The operation of the operation (ie, the left bit and the : bit) is trapped in the memory. When one of the two bits is programmed; the bit is even if one bit is being programmed, the other The voltage and voltage may also increase. The stylization of the left bit is illustrated in Figure 8A, which is in the left bit 812. Although only the left bit 812 is programmed by the program, the left bit 812 is also programmed to cause the threshold voltage of the right bit 814 to increase, as depicted in Figure 8B. Curve 820 illustrates that as the left bit is programmed, the threshold voltage of the right bit 814 rises. This phenomenon is called the second bit effect. An ideal curve without a second bit effect will stylize the left bit of the green bit to cause the threshold voltage of the left bit to increase, but will not affect the threshold voltage of the right:, so that the threshold voltage of the right bit will保持 兀 兀 图 图 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 ' ' ' ' ' ' ' ' ' ' In Fig. 9B, the symbol % offset is used to indicate the bit margin (4) right bit_boundary voltage %(1). One: the difference between the offsets of the boundary voltage Vt(1) is 9: the two edges, the threshold voltage of the left bit has been The offset is about 3.5 volts and the right: = the threshold voltage has been shifted by _ U volts. The margin of the bit is calculated as the offset of Vt(1) and the second bit of the case is calculated as follows: the difference between 3.5 wins and U moves, and FIGS. 10A and 10B are diagrams showing the right-handed & The chart of the second bit margin of the cell is represented by the symbol (4) in the tender, and the position in the figure _ is in the figure as shown in the figure, and the == in the left bit. Example (4) The two-bit margin is calculated as the difference between vt and the shift, which is calculated as follows: , partial bias and vt (0 is offset as shown in Figure 9A is about Avot = 4.5 volts. The erase is a negative threshold voltage; the ^ bit is compared with the violation between Figure 10A, and the erase is negative 200805679 F940260 19580twf.doc/e =:: The second bit margin of the axial erase operation is significant The second bit margin is greater than the erase operation of the eraser and force volts. ^ In the present invention, the second view's figure u is used to describe the implementation in the memory of the memory (11). The sound of the first embodiment = !^S01 includes the oxide ί V 0 2 / insulation (4) on the dream substrate iiig. In the structure (10), without applying the idle bias g, the month, overnight 1130 is formed between the n+ source region 1132 and the n+ drain region (1) 4. The n+ source region (10), the channel 113〇, and the polar region 1134 are on the emulsion layer 1120. The channel 113〇 is deposited as a single oxide on the oxide layer. The day 1100 can be implemented with wormite or polycrystalline stone. The example of a suitable thickness U190 of the channel is in the range of about 5 〇〇A to about 〇A. 1150 is on the oxide layer 114, which is also referred to as a nitride-oxide (NO) stack. The polysilicon gate 116 is on the charge trapping layer. Some suitable materials for the application of the polysilicon gate 116〇 include η. Type polycrystalline germanium, p-type polycrystalline germanium or metal gate. In the absence of the top oxide on the charge trapping layer 1150, the erase operation toe using the tunneling injection is more than enough to make the hole move more The spar is idle and enters the charge trapping layer 115Q. The gate bias 1170 is connected to the polysilicon gate 1160, the source dust 1172 is connected to the n+ source region 1132, and the pole voltage U74 is connected to the n+ drain region 1134. And the substrate voltage 1176 is connected to the germanium substrate 1110. FIG. 12 is a schematic diagram illustrating a first embodiment implemented in the MONOS-SOI memory 1200. The MONOS-SOI memory includes an oxide layer 122 on the germanium substrate 1210. To act as an insulating material. In the s〇i structure, 19 200805679 P940260 19580twf.doc/e In the case where the gate bias voltage Vg is not applied, the channel 1230 is formed between the n+ source region 1232 and the n+ drain region 1234. n+ source region 1232, channel 1230 and n+; 1234 is on oxide layer 122. Channel 1230 is deposited as a single crystal on oxide layer 1220. Channel 123 can be applied by epitaxial or polycrystalline germanium. An example of a suitable thickness of channel 1230 is 129 Å at about 500 Å. Within a range of about 1 A. The charge trapping layer 125 is on the bottom oxide layer 1240 and the top oxide layer 126 is on the charge trapping layer 125'. This is also referred to as an oxide-nitride-oxide stack. . The polysilicon gate Η% is on the top oxide layer 126G. Some of the reclining materials used to implement the polycrystalline stone gate 127 包含 include n-type multi (four), P-type polycrystalline or metal gates. In one embodiment, the top oxide layer 126 is selected to be sufficiently thin to be implanted through the via tunnel, and the hole can move through the polycrystalline montage and top oxide layer 1260 to the charge trapping layer 125. . The idle pole bias 1280 is connected to the polycrystalline gate 127 〇, the source voltage 1282 is connected to the stalk source region 1232, the drain voltage 1284 is connected to the n+ immersion region 1234, and the bottom voltage 1286 is connected to the 矽 substrate 121 〇 . Soil, Figure 13A to Figure l3C illustrate the memory in the _〇8_8〇1 memory or MONOS-SOI memory! A block diagram of the first embodiment of the wiping operation in which the hole tunneling is performed in 200. In Fig. 13A, on the right bit of the channel hot electron Z MN 〇 S memory _, as the arrow ΐ 3 〇 ^ is moved to the right, and the electronic coffee is placed on the right side of the charge trap layer ^. Applying a voltage of 10 volts Vg, applying volts

Vsub ' applies a zero volt source voltage VS, and applies 5 volts, and engages ^

Vd. Let the source voltage Vs 117? #, the 〆 〆 · · 义 ” 卫 卫 I I 172 172 172 172 172 172 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 The electrons are guided on the left bit, as shown by the arrow in Fig. 13B, and the electrons 1340 are injected into the charge trapping layer 1150, the second and the fifth, and the 5 volt source voltage Vs, and the voltage is applied. During the period 'as shown in Fig. 13C, apply +16 volts of positive power H to your second Vg 117G, apply G volt base voltage Vsub 1176, 1] 74. The pole voltage Vs 1172, and apply 0 volts without the poles repeatedly Vd show :=wearing with the erase operation causes the hole (10) such as the arrow I% to penetrate the polycrystalline slab gate _ and enter the charge trapping layer 115〇. 囝4A to Fig. 14D illustrates the etch through the mn〇S-SOI The second embodiment of the dividing operation is performed in 1100 or MONOS-SOI memory 1; the heat is in the right bit of the memory cell, and the base voltage is one == drain voltage Vd. The source voltage vs n is made. [The voltage offset in vcnm is reversed. On the element, as shown by the arrow 丨, move to the left - sub: = and apply a voltage of 0 volts to the drain. In Figure 4C, S, Figure _ Chinese households still use the two upper sum (10) on the left bit, apply _ base cake Vsub ^ = gate f electric cover 屡 VS Π 72, and apply 5 volts 汲 电 屡 V V V = = = U / 4. Right 彳立上21 200805679 P940260 19580twf.doc/e The band-to-conductor hot hole erasing causes the hole l45 移动 to move from the n+ drain region 1134 into the channel 1130, through the oxide layer 114 〇 and enter the charge trapping layer 1150, as indicated by arrow 1460. Apply 〇 volt volts negative; voltage gate voltage Vg 1 Π 0, apply 5 volts substrate voltage Vsub 1176, ^ · · 〇 volt source voltage Vs 1172 And applying a 0 volt bungee voltage Vd 1174. The hot hole erase between the band-bands on the left bit causes the hole Μ% to move from the n+ source region 1132 into the channel 1130, through the oxide layer The charge trapping layer 1150 is shown as arrow 148. Figure 15A is a diagram showing the stylized structure of the left bit in the MNOS-SOI memory 11〇〇 or M〇N〇SS〇I: 忆, 1200, (d) ΐ5β is a corresponding graph illustrating the operational margin of a single memory cell octet of the second bit effect (referring to the right bit in this example). The two-bit effect occurs in a memory cell that uses two bit operations (ie, left and right bits). When stylizing one of the two bits, even if only one bit is stylized The threshold voltage of another bit may also increase. The stylization of the left bit 说明 is illustrated in Figure 15A, indicating that the charge 151 is on the left bit 1512. Although only the left bit 1512 is stylized, the stylization of the left bit 1512 also causes the threshold voltage of the right cell fl4 to increase, as depicted in Figure 15B. The curve 1520 ^ " 儿明卩 returns to the left bit 1512 is stylized, the threshold voltage of the right bit 1514 increases. This phenomenon is called the second bit effect. The rational J curve without the second bit effect will reflect that the continuous stylization of the left bit will cause the critical voltage of the left bit to increase, but will not affect the threshold voltage of the right bit, thus the threshold voltage of the right bit. Keep it substantially constant. The second embodiment of the present electric power diagram illustrates a first embodiment of a shell oxide having a multilayer dielectric structure implemented in the MNONOS memory 1600, which includes an on-mode operation 22 200805679 P940260 19580 twf.doc/e. The MNONOS memory 1600 is fabricated on a p-type germanium substrate 1610. A drain n+ doping region 1620 and a source n+ doping region 1622 are formed on the upper right side and the upper left side of the p-type broken substrate 1610. A bottom dielectric structure 1630 (e.g., oxide) covers the p-type germanium substrate 161, and a charge trapping layer 1640 including a tantalum nitride layer covers the bottom dielectric structure 163.

The top dielectric structure 1650 covers the charge trapping layer 1640. The view m structure 1650 has a plurality of layers including a tantalum nitride layer 1654' covering the oxide layer 1652. This is also referred to as an N-0 stack. A p-type polysilicon layer 166 〇 covers the top dielectric structure 1650. Other suitable materials may be implemented in place of the p-type polysilicon layer 166, such as an n-type polysilicon or a metal gate. A gate voltage Vg 167G is applied to the p-type polysilicon layer 166, and a bottom voltage Vsub 1672 is applied to the p_ substrate 161Q. A drain voltage 1674 is applied to the gateless n+ doped region 162, and a source voltage % 1676 is applied to the source n+ doped region 1622. Figure Π illustrates the top oxide ^ __ with a multi-layer stack structure implemented in Remembrance 17QG in an on mode operation. M〇N()N()s memory 17(8) is fabricated on p-type Shi Ximei ί on the substrate instead of the f gauge. The immersed n+ doped region 172 soil 0 (four) 1722 is formed in the (iv) dream base mG right dielectric structure 1730 (eg 'oxide') covering the substrate 1710, and the bismuth telluride layer 174 〇 covers the bottom layer 丄 丄 « « « « And mouth structure 1730. Top Dielectric Structure Recipe II Cut 1740. The top dielectric structure mG has a plurality of layers, and the oxide layer 1750 covers the nitrided cucurbit 1754 覆盖 overlying oxide layer 1752, which is a stacking of the first layer 1752. P-type polycrystalline litho layer 23 200805679 P940260 19580twf.doc/e 1760 covers the top dielectric structure 175〇. Other suitable materials may be implemented in place of the p-type polysilicon layer 1760, such as an n-type polysilicon or a metal gate. A gate voltage Vg 177 施加 is applied to the p-type polysilicon layer 1760, and a substrate voltage of 1772 Vsub is applied to the p-type polysilicon substrate 1710. The gate 11+ doping region 1720 is finely added; and the terminal voltage yd 1774 is applied, and a source voltage Vs 1776 is applied to the source n+ doping region 1722. 18A through 18C are block diagrams illustrating a first method for increasing a second bit margin in a top multilayer dielectric structure used in an on-type operation, which is applicable to MN〇N〇s Both the first and second embodiments of the modality and the MONOOS memory 17〇〇. Figure 18A is a block diagram showing the programming of the MNONOS $ memory 1600 through the channel hot electrons placed by the right sister element. Directional arrow 181 indicates that the applied hot electrons are applied to the right bit, such as by the electrons in the charge trapping layer 164(). An 8 volt gate electric voltaic Vg 167 施加 was applied, a $ volt applied volts applied to the volts volt source voltage VS 1676, and 0 m VSUb 1672 was applied. The combination of the four (4) pressure causes the right bit in the OSsfe face to become a positive threshold voltage + vt. FIG. 18B is a diagram illustrating that the hot electrons of the ONOS memory are touched by the left bit element to privately apply the channel hot electrons to the left position. Please refer to the emperor; mm recognition-, Ge from the book The electrons 1840 in layer 1640 are not painted. The volts of the volts of the second poles of the volts Vd: 1674, the application of 5 volts such as two coffee, plus 〇 〇 〇 volts base voltage Vsub 16 ^ H = Vs 1676 ' and Shi Zhi coffee N0S memory 16 左 left ^ The electric_combination guides the threshold voltage +Vt. : 〇 位 凡 凡 凡 凡 凡 凡 凡 凡 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 During the erase operation, it is difficult to move the hole charge 1860a through the p-type polycrystalline layer 166 〇, the nitride layer 1654, and the oxide 丨 652 into the charge trapping layer, in the direction indicated by the arrow 185 上. Perform hole punching and erasing on the left bit. Also, by making the hole electric, delete b and move through p-type polycrystalline dream layer lion, nitrogen cut layer 1654 and milk 1 material 1652 and enter the charge trapping layer, and implement electricity c on the right bit. A 16 volt inter-electrode voltage Vg 167 施加 was applied, a =74 ” volt source (4)% 1676 was applied, and t t Μ 1672 was applied. This combination of Weijia leads to penetration == teeth shouting hole charge moving through? The type of polycrystalline pin 166 〇, nitriding eve 1654 and oxide 1652 and into the mine p々 κι hole injection erase. It is said that the & human layer 1640 is electrically connected to the figure to make it suitable for low voltage operation. The picture is layer dielectric; the second is used to increase the top of the first and the first ... L touch and M 〇 N 〇 N 〇 S memory 1700 used in the on mode operation. 19A to 19B are respectively structural diagrams for stylizing the middle, ten, and * 透过 through the MNONOS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . Indicates that the channel will be hot electrons II]

The position 'If the charge is trapped in the layer i6 U 8 volt gate _ Vg _, the application applies 0 胪 胪 此 this A powder and the pole voltage Vd 1674, ~ the original voltage Vsl676, and the application of 0 volt base voltage ν 25 200805679 J 9580twf.doc/e ^ The pressure (4) causes the channel hot electrons in the right bit 70 in the __s memory circle to become a positive critical electromigration + vt. In order to make the MNONOS memory through the left bit position, the electric memory is applied to the left bit element, such as the electrons 1940 in the hard trapped layer. . Apply 8 to the furnace pw Tungsaw voltage then 74 =: = 1 = 'apply 0 volts. She adds > volt source voltage Vs 1676, and applies the stagnation voltage Vsub 1672. This picture deletes the channel hot electrons of the left bit in __ = threshold voltage + Vt. Bao Yiyi Ma Zheng $ 19C is a structural diagram of the hole through the hole tunneling to the _ 〇 memory surface K Ding hole. During the erasing operation, by moving the hole 196 through the P-type polycrystalline layer 1660, nitriding the layer 1654 t, and entering the charge trapping layer 1640, the left bit is implemented. The hole is erased. Applying a hole to the right bit in the direction indicated by the former 1950 by moving the hole charge 19_ through the p-type layer 1660, the nitride layer 1654, and the oxide leg into the charge trapping layer 1640; ==8 volts between the pole voltage Vgl (four), applied. Volt immersed electricity £ Vd 1674, applying volts volts source voltage % 1676, and applying volts of substrate power M Vsub 1672. These applied combinations lead to tunneling to cause the hole charge to move through the p-type polycrystalline layer 166, the layer 1654 and the oxide 1652, and enter the charge trapping layer to perform hole injection erasure. The second method of operation operates at a low voltage by applying a gate bias voltage from +16 to +8 volts and applying _8 volts through the "(iv) substrate 161(). 26 200805679 P940260 19580 twf.doc/e operates at a low voltage. Figure 2A疋Describe the stylized structural diagram of the left bit in Mn〇NOS memory 1600 or mononos jfef 17GG, and Figure 2〇B is the first 兀 effect (in this example, the right bit) (5) Single memory cell A corresponding graph of the operating margin of the two bits. The second bit effect occurs in a memory cell that uses two bits # (ie, 'left and right bits'). When stylized in two bits In one bit, even if only one bit is programmed, the threshold voltage of the other bit may increase. Figure 2A shows the stylization of the left bit, which indicates that the charge 2〇1〇 is in the left bit. 2〇12. Although only the left bit 2012 is stylized, the stylization of the left bit 2〇12 also causes the 63⁄4 boundary voltage of the right bit 2014 to increase, as shown in Figure 2〇b. Curve 2020 It is shown that as the left bit 2〇12 is programmed, the threshold voltage of the right bit 2〇14 increases. This phenomenon is called the second bit effect. An ideal curve with a second bit effect will involve a continuous stylization of the left bit that will cause the threshold voltage of the left bit to increase, but will not affect the threshold voltage of the right bit, so that the threshold voltage of the right bit will remain The MNONOS memory 1600 having a p-type germanium substrate and the MONONOS memory 1700 having a p-disk substrate are intended as an illustration of the on-mode operation of the third aspect of the present invention with reference to FIGS. 16 through 20. Other memory structures, including TFT memory and MONONOS TFT memory, can also be practiced within the spirit of the present invention. In a fourth aspect of the present invention, Figure 21 illustrates the implementation of the use in MONONS memory 2100 in an on mode operation. A first embodiment of a bottom oxide of a multilayer dielectric structure. MONONS memory 21 〇〇 fabrication 27 200805679 P940260 19580twf.doc/e On a P-type germanium substrate 2110, a p-type germanium substrate 2110 has a p-type germanium formed thereon, respectively. The upper right side and the upper left side of the substrate 2110 have a drain n+ doped region 2i2 and a source n+ doped region 2122. The bottom dielectric structure 2130 covers the p-type germanium substrate 2110. The bottom dielectric structure 2130 has a plurality of The oxide layer 2134 includes a hafnium nitride layer 2132, which is also referred to as a 0-N layer. The tantalum nitride layer 214 〇 covers the bottom dielectric structure 2130, and the oxide layer 2150 covers the tantalum nitride layer 214f and the P-type polysilicon The layer 2160 covers the oxide layer 215. Other materials can be implemented instead of the P-type polysilicon layer 2160, such as an n-type polysilicon or a metal gate. A gate voltage Vg217 is applied to the p-type polysilicon layer 2160. And a substrate voltage Vsub 2176 is applied to the P-type germanium substrate 2110. A wave voltage Vd 2m is applied to the drain time doping region 2120, and a source voltage Vs 2174 is applied to the source dummy pad 2122. Referring to Figure 22, a second embodiment of a bottom oxide having a multilayer dielectric structure in the MONONOS memory 2200 for use in an on mode operation is illustrated. The MONONOS memory 2200 is fabricated on a p-type 矽 substrate 2210 having a drain η+ doped region 222 〇 and a source doped region formed on the upper right and upper left sides of the P-type ί ί 2222. The bottom dielectric structure 2230 covers the p-type Shi Ximei 221 〇. The bottom dielectric structure has a plurality of layers including an oxide layer % 236 covering the emulsified layer 2234 and a nitride layer 2234 covering the oxide layer, which is also referred to as a 0-Ν-0 layer. The nitride layer 2240 covers the bottom dielectric structure 223, the material layer 2250 covers the nitrogen-cut layer, and the p-type polycrystalline layer is the back cover oxide layer 2250. Other suitable materials may be employed instead of the p-type polycrystalline layer 2260, such as η-type polycrystalline chopping or metal idler. A gate voltage of 2270 Vg is applied to the p-type polycrystalline stone 28 200805679 P940260 19580twf.doc/e layer 2260; and a substrate voltage of 2276 Vsub is applied to the p-type germanium substrate 221. A gate voltage is applied to the drain n+ doping region 222, a voltage Vd 2272 is applied, and a source voltage v~2274 is applied to the source n+ doping region 2222. In Fig. 23, a third embodiment of a bottom oxide having a multilayer dielectric implemented on a polycrystalline germanium substrate in MONONS TF butyl memory 2300 for use in an on mode operation is illustrated. M〇n〇ns tft 记 体 • 2300 is fabricated on a P-type polycrystalline germanium substrate 2310, and the P-type polycrystalline germanium substrate 2310 has a bungee n+ on the upper side and the upper left side of the p-type home crystal ill base 231〇. Doped region 2320 and source n+ doped region 2322. The bottom dielectric structure 2330 retries the p-type polysilicon substrate 231. The bottom dielectric structure μ兕 has a plurality of layers including an oxide layer 2334 covering the nitride layer 2332, also referred to as a 0-turn layer. The nitride layer 234 〇 covers the bottom dielectric structure 233 〇, the oxygen layer 2350 covers the nitrogen cut layer, and the p-type polycrystalline chop layer 236 covers the 盍 盍 layer 2350. Other suitable materials may be substituted for the p-type polycrystalline layer • 236G and Μ Μ ' for example, type 11 multi-day sun-break or metal gate. A gate voltage of 237 〇 Vg is applied to the p-type polycrystalline layer 2360, and 2376 Vsub is pressed to the p-type polycrystalline base substrate. A drain *voltage Vd 2372 is applied to the drain η+ doping region 232, and 2Ρ4 is applied to the source η+ doping region 2322. Fig. 24 illustrates a bottom oxide (four) having a multilayer dielectric structure implemented on a polycrystalline substrate in an M_NOS system memory 24, used in an on mode operation. MqNq body 2400 is manufactured in? Type 曰 々 々 PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI PI 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Region 242 〇 and source n+ doped region MM. The bottom dielectric, and 2430-pole p-type polycrystalline germanium substrate 241〇. The bottom dielectric structure has a plurality of layers ' including an oxide layer 2436 covering the nitride layer 2434 and a nitrogen oxide layer 2434 covering the oxide layer MM, which is also referred to as a (10) layer. The nitride layer 2440 covers the bottom dielectric structure 243〇, the oxide layer is deposited on the tantalum nitride layer 2440, and the p-type polycrystalline layer leaks over the oxide layer 245 [other suitable materials can replace the p-type polycrystalline dream Layer 246G is implemented, such as a doped polysilicon or a metal gate. An inter-electrode voltage of 2470 Vg was applied to the p-type polycrystalline silicon layer 246, and a substrate voltage of 2476 Vsub was applied to the palladium-type polycrystalline germanium substrate 2410. A drain voltage Μ is applied to the drain η+ doping region 242, and a source voltage vs 2474 is applied to the source n+ doping region 2422. Referring to Figure 25, a first embodiment of a μ (HK) NOS § Remembrance 2500 for use in an on mode operation, each memory cell of the Μ (Ηκ) N〇S memory 2500 is illustrated. A two-dimensional and high dielectric (mgh-k)-material is stacked on a germanium substrate. M (HK) N 〇 s memory 2 5 (10) is fabricated on a p-type germanium substrate 2510 having drain d+ doped regions 2520 formed on the upper right and upper left sides of the p-type germanium substrate 2510, respectively. Source n+ doped region 2522. A bottom dielectric layer 2530 including an oxide layer is on the p-type germanium substrate 2510, and a charge trapping layer 2540 including a tantalum nitride layer is on the bottom dielectric layer 253. The high dielectric material stack layer 255() is disposed over the charge trap layer 2540, and the p-type polysilicon layer 256 is disposed over the high dielectric material stack layer 2550. A gate voltage of 2570 Vg is applied to the p-type polysilicon layer 256 ,, and a substrate voltage is applied to the P-type germanium substrate 251 2008. 200805679 P940260 i958〇twfd〇c/e 汲 A bungee voltage Vd 2572 is applied to the non-polarization replacement region 2520 And to the hetero-n+_ zone, you apply the source power plant to the Vs2r7r. In the case of a wide application, the high dielectric material stacking layer 255G is selected from the right = electricity = i ^ Si02 + 丨μ Or in the M〇s gate and gate dielectrics, the area ^ is not thick enough to prevent over-largeness. In the other example, the 'high dielectric material stack layer 2550 is selected from the 2nd 2nd layer 254G. High dielectric constant dielectric materials. Some examples of suitable dielectric materials 2550 include oxidized A1203 and emulsified to Hf 〇 2. The description of the high dielectric material stack layer also applies to the implementation described in Ref. Figure 26 illustrates a second embodiment of the M (HK) N 〇 s character structure 26 GG used in the on mode operation + the 冋 dielectric material stack layer in the 触 一 (1) 忆 版 260 〇 On the polycrystalline germanium substrate, Μ(Ήκ)=〇S memory 2600 is fabricated on p-type polycrystalline substrate 261, p-type polycrystalline substrate 261 0 has a drain n+ doped region 2620 and a source n+ doped region 2622 formed on the upper right side and the upper left side of the p-type germanium substrate 261A. The bottom dielectric layer 2630 is on the p-type polysilicon substrate 261 and nitrided. The germanium layer 264 is on the bottom dielectric layer 2630. The high dielectric material stack layer 265 is disposed over the nitride layer 2640, and the p-type poly germanium layer 266 is disposed over the high dielectric material stack layer 2650. The polysilicon layer 2660 applies a gate voltage of 2670 Vg and applies a substrate voltage of 2676 Vsub to the p-type polysilicon substrate 261. A gate voltage vd 2672 is applied to the drain n+ doped region 262, and 31 200805679 P940260 19580twf.doc/e A source voltage Vs 2674 is applied to the source n+ dummy pad 2622.

27A through 27C are block diagrams illustrating a first method for increasing a second bit margin of Μ (HK) NOS s memory 2500 or 2600 used in an on mode operation, in which V! (HK) N〇s memory 25〇〇 or 2600 high dielectric material stack layer on the germanium or polycrystalline substrate. Figure 27A疋5 shows the structure of the μffiONOS memory 2500 or 2600 programmed by the channel hot electrons placed by the right bit. The directional arrow 271 指示 indicates that the channel hot electrons are applied to the right bit, as depicted by the electrons 2720 in the charge trapping layer 254. An 8 volt gate voltage Vg 257 施加 was applied, a 5 volt gate voltage Vd 2574 was applied, a volt volt source voltage Vs 2576 was applied, and a 0 volt substrate voltage Vsub 2572 was applied. The combination of these applied voltages causes the channel hot electrons of the right cell in Μ() NOS memory 25〇〇 or 2_ to become a positive threshold voltage +Vt. FIG. 27B is a structural diagram illustrating a channel thermoelectron coming through the left bit cell = Μ (HK) side memory 25 〇〇 or 26 。. Direction The front head 2730 indicates that the channel hot electrons are applied to the left bit, such as the dice 2740, which is trapped in the charge trapping layer 2540 t. An 8 volt gate voltage 2570' was applied to apply the sag residual voltage Vd plus, a $ volt source voltage Vs 2576' was applied and a volt volt base voltage 2572 was applied. The combination of these applied voltages causes the channel hot electrons of the M (HK) memory % (8) or the left 70 in the toilet to become a positive threshold voltage. The picture shows the formation of the M (HK) N0S memory measurement or the toilet erase through the tunnel. During the erase operation, by moving the hole 2760a through the p-type substrate 251() (p-type dream substrate or p-type poly 32 200805679 P940260 19580twf.doc/e wafer substrate), and passing through the bottom dielectric layer 253 〇2540, hole tunneling is performed on the left bit. Also through the p-type substrate 251G (P_ substrate ^ more = substrate), the bottom dielectric layer 253G and into the direction of the human charge P 2 = 2750 in the direction of the hole on the right bit through the erasing ^ 刖^ = Negative voltage 峨Vg 257〇, modulo two, apply volts volts source voltage Vs 2576 voltage V-2572. These applied = base f tunnels cause the hole charge to move through the p-type substrate H through the hole and into the charge TM; the figure 28A to FIG. 28C is used to increase the memory in the mode = ΗΚ) , or 26 baht. The structure of the first scoop method is shown in the structure diagram of the %(Ηκ)-assisted two-layer laminate or polycrystalline=upper-secondary 2600. In the direction arrow 2810: ==1 to the right bit, such as the charge trapping layer 2540 5 volts. Applying a 8 volt closed-pole voltage Vg 2570, applying and expanding two: two ^ 2574 ' applied 0 volt source (four) voltage Vs 2576, ί Ϊ I voltage - 2572. The group channel hot electrons of these applied voltages become positive 4; the body ν Γ or FIG. 28 Β is a block diagram illustrating that the M (MO NOS memory 25 (10) or 2 _ structure diagram is programmed by the channel holding electrons placed by the left bit bit. Direction 33 200805679 P940260 19580twf.doc/e Arrow 283 0 indicates that the channel hot electrons are applied to the left bit, as indicated by the electron 284 in layer 2540. Applying 8 volts to the voltage 曰·: 2, applying 〇 Volt and pole voltage vd, apply 5 volt source with voltage Vs 2576, and apply 0 volt substrate voltage Vsub 2572. This = '· voltage combination results in Μ (HK) NOS memory 2 · or . 2; ^ The channel hot electrons of the left bit of the port become a positive threshold voltage + vt. Fig. 28C is a structural view illustrating the hole injection erasing of the M (HK) N 〇 s memory Φ (8) or 2 cap by tunneling. During the erase operation period, by causing the hole charge 2860a to move through the p-type polysilicon layer 256, the high dielectric material 2550, and into the charge trapping layer 254, the hole penetration is performed on the left bit in the direction of the arrow S285. Tunneling is also removed by moving the hole charge 286〇b through the P-type polysilicon layer 2560. The dielectric material 255 进入 enters the charge trapping layer 2540, and the hole tunneling erase is performed on the right bit. = the gate voltage Vg 2570 of the negative voltage of 8 volts is applied, and 8 volts is applied to the voltage Vd 2574, and 8 volts is applied. The source voltage Vs 2576 and the application of 8 volts of the ruthenium voltage VSUb 2572. The combination of these applied voltages causes the tunneling of the hole to move the charge through the 1) type substrate 251, the bottom dielectric layer 2530 and enter the charge. The layer 2540 is trapped and the hole is implanted and erased.

29A is a block diagram showing the stylization of the left bit in the M(HK)NOS memory 2500 or the m(HK)NOS body 2600, and illustrates the first bit effect (in this example, the right bit) A corresponding graph of the operational margin of a single memory cell. The second bit effect occurs in the memory cell that makes ^ two bit operations (ie, left and right bits). When one of the two bits is privately categorized, even if only one bit is normalized, the g-term voltage of the other bit may increase. The stylization of the left bit is illustrated in Figure 29a, which indicates that the charge 291 is on the left bit 2912. Although only the left bit 2912 is stylized, the stylization of the left bit 2912 also causes the boundary voltage of the right bit 2914 to increase, as depicted in Figure 29B. The curved line 2920 illustrates that as the left bit 2912 is programmed, the critical voltage of the right bit 2914 increases. This phenomenon is called the second bit effect. An ideal curve without a second bit effect would include a continuous stylization of the left bit φ 会 that would cause the threshold voltage of the left bit to increase, but would not affect the threshold voltage of the right bit, so that the threshold voltage of the right bit would Keep it substantially constant. In addition to the erase operations described above with reference to various embodiments, the present invention is also applicable to the pre-programmed erase step as described in the following flow chart. Figure 30 is a flow diagram illustrating a process 3000 for pre-programming erase s〇N〇s type or TFT_s〇N〇s memory. At step 3〇10, using hole tunneling erase from s〇N〇s type or TFT-SONOS memory, applying positive gate voltage +Vg through idle terminal ^ will include two bits per memory cell The pre-programmed erase of the memory structure of the SONOS-type or TFT-SONOS memory is a negative threshold voltage -Vt. At step 3020, the s〇N〇s type, 'or TFT-S〇 NOS memory is programmed by the channel hot electrons of the left and right bits of the charge trap. At step 3030, the s〇N〇s type or TFT-SONOS memory is erased by a hole injection or a band-to-band thermal hole technique. Alternatively, at step 3〇1〇, in this embodiment, a pre-programmed erase is performed using a thermal hole erase between the band-guide tapes without using a tunneling technique. In other embodiments, at step f3〇i, the hole tunneling technique in the pre-programming erase operation erases the s〇N〇s type or 35 200805679 P940260 19580twf.doc/e TFT-SONOS memory into Below the initial threshold voltage % (i) voltage level. 31 is a flow chart illustrating a flow 3100 of pre-programming erase SONOS-type or TFT_s〇N〇s memory. At step 311, the 彳〃s〇n〇s type or the TFT-SQNOS memory/bottom hole _ ^ ^, by applying a negative gate voltage -Vg, will include two bits per memory cell. SONOS type or TFT-S 〇 记忆 记忆 记忆 纽 纽 纽 纽 纽 结构 结构 肺 肺 肺 肺 肺 肺 肺 肺 肺 肺 肺 肺 肺 肺At step 3120, the S0N0S TFT-S0 pin memory is programmed by channel hot electrons to the left and right cells of the memory cell. At step (10), the coffee (10) or TFT-SONOS memory is erased by a hole injection or a hot hole technique between the bands. Alternatively, in step 311, in some embodiments t, a pre-programmed erase is performed using the energy band, the conduction band, the thermal power, and the hole. It implements the money, in the step · at the pre-synthesis of the wipes of the electric hole to wear the lions = 〇 〇 〇 〇 _ _ _ drama · vt (1)

Figure 32 is a flow chart showing the flow 32 (10) of the pre-programmed erase s〇N〇s memory, the S0N0S type or the TFT_S0N0S ^ memory includes a top gate oxide having a multi-layer stack, wherein each memory cell is a memory The cell has two positions.

Type or TFT-S0N0S memory of the closed pole; where = S〇N〇S by applying a positive gate voltage +Vg ^, (4) (four) except ' or TFT-S0N0S: memory structure: ~ m and have a multi-layer stacked S0N0S Type negative threshold voltage -Vt. At step 200805679 P940260 19580twf.doc/e 3220, SONOS-type or TFT-SONOS memory is programmed by channel hot electrons to the left and right bits of the memory cell. At the step, _ is erased by a hole injection technique or a band-to-band thermal hole technique to remove the S0N0S type or TFT-SONOS memory. Alternatively, at step 321A: In some embodiments, the pre-programmed erase is performed using a hole-to-band thermal hole erase instead of a hole tunneling technique. In other embodiments, at step 3210, the hole tunneling technique in the pre-programmed erase erases the s〇n〇s Φ-type or TFT-S0N0S memory to a voltage lower than the initial threshold voltage Vt (〇 In a further embodiment, at step 321A, by applying a negative gate voltage -Vg, a hole tunneling erase is used from the substrate of the SONOS-type or TFT-SONOS memory, and s〇N having a multi-layer stack The 〇s-type or TFT-SONOS memory structure is erased to a negative threshold voltage ^^. Figure 33 is a diagram illustrating the pre-programmed erase s〇NOS type or tft_s〇n〇s

The flow chart of the process 3300, s〇N〇S type or TFT-SONOS, includes a bottom gate oxide having a multi-layer stack, wherein each memory cell has two bits per memory cell yuan. At step 3310, the gate terminal of the SON〇s-type or TFT-SONOS memory is erased using a hole, • The S0N0S type % or TFT_S0N0S memory having a multi-layer stack is applied by applying a positive gate voltage +Vg. The structure is erased to a negative threshold voltage. At step 3320, the channel is transmitted to the left and right cells of the memory cell, and the electronic Z is programmed to the S0N0S type or the 1st 0 memory. At step 3S3, the SONOS type or mONGS memory is accessed by a hole injection technique or a hot hole technique between the band and the conduction band. Or, at the step of deleting: in the "something", use the hot hole between the band and the conduction band without using 200805679 P940260 19580twf.doc/e

♦it 3 2/T, /, pre-programmed erase. In other embodiments, at the ?:, the hole tunneling technique in the stylized erasing erases the SONOS line stomach TFT S(10)OS WE body to an electric reverse level lower than the initial threshold voltage %(1). In the embodiment, at step 3310, the s〇n〇s type or the TFT-SONOS memory structure having the multilayer stack is used by applying the negative gate HVg ' from the s(10) Gs type or the base of the memory. Erased to a negative threshold voltage -^.

Figure 34 疋虎明Preprogramming erase s〇N〇s type or Ding Ding _8〇^〇8

Flow chart of mouth and mouth L3, body level private 3400, sonos type or Ding FT-SONOS

The memory includes a high dielectric material in which each memory cell has two bits per memory cell. At step 3410, 'T hole tunneling is used from the gate terminal of the SONOS-type or TFT-SONOS memory, and the SONOS-type or D-FT-SONOS with high dielectric material is applied by applying a positive-interpole voltage +Vg. The fe body structure is erased to a negative threshold voltage _Vt. At step 3420, the SONOS type or TFT-SONOS memory is programmed by channel hot electrons to the left and right bits of the memory cell. At step 343, the s〇N〇s type or TFT-SONOS memory is erased by a hole injection technique or a band-to-band thermal hole technique. Alternatively, at step 3410 in some embodiments, the pre-programmed erase is performed using a band-to-band hot hole erase without using hole tunneling techniques. In other embodiments, at step 3410, the hole tunneling technique in the pre-programmed erase erases the s〇N〇s type or the TFT-S0N0S memory to a voltage level lower than the initial threshold voltage vt (i). Bit. In a further embodiment, at step 3410, by applying a negative gate voltage -Vg, using a hole tunneling erase from the substrate 38 200805679 P940260 19580twf.doc/e of the SONOS type or TFT-SONOS memory, The s〇N〇s type or the TFT-SONOS § memory structure with multi-layer stacking is erased to a negative threshold voltage. The invention has been described with reference to specific exemplary embodiments. For example, the method of the present invention is applicable to any type or variation of nitride trap memory and floating stub memory including N-channel and p-channel SONOS type elements. Various modifications, changes and variations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as the BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a diagram showing a simplified structure of a memory cell according to the structure of the present invention. According to the present invention, the structure of the charge trapped in the memory cell is privately converted by the channel of the right bit. Figure ic is a diagram illustrating the stylization of charge trapping memory through the left bit characterization according to the present invention. ^Sub-Process Figure 1D is a block diagram showing the hole injection erase of the charge trap in accordance with the present invention. FIG. 2 is a diagram illustrating the wiping method according to the present invention. The erase method is performed by using a hole from the s〇N〇s memory. Extreme pressure between the two. /, * is a negative criticality diagram 3 is a diagram illustrating the erasing pattern according to the present invention, which is transmitted through a substrate from the s〇N〇St^ two structures of the 6U stomach. 200805679 P940260 19580twf.doc/e The negative gate voltage is widely used by the hole penetration

4A-FIG. 4A illustrates the tampering voltage according to the present invention. The structure of the example 'the erase method is smeared by the implementation of the thermal band division between the band and the conduction band, FIG. 5 is a diagram illustrating the transmission through the positive closed pole & f according to the present invention. ink. The flow of the first embodiment of the steep erase method is a flow chart of the second embodiment of the erase method for the negative 替 根据 according to the present invention.仃 祠 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图Structured diagram. The private figure 8 is a corresponding diagram illustrating the second bit effect (referring to the right bit in this example) in accordance with the present invention. Figure 9A to Figure 9A are diagrams illustrating a second bit margin of a MNOS g's memory having a critical electrical power of about zero volts, which is represented by the symbol Vt in Figure 9A, and FIG. 10A is a graph illustrating a second bit margin of a MNOS memory cell having a threshold voltage of a negative threshold voltage level according to the present invention, FIG. 10A and FIG. 10B are diagrams illustrating a threshold voltage of a MNOS memory cell having a threshold voltage of a negative threshold voltage level according to the present invention. This is indicated by the symbol vt in Fig. 10A and by the symbol Vt offset in Fig. 10B. Figure 11 is a diagram illustrating a first embodiment implemented in MNOS-SOI memory in accordance with the present invention. 40 200805679 P940260 19580twf.d〇c/e Figure n is a schematic diagram illustrating a second embodiment implemented in accordance with the present invention. ^ Ji3A to Fig. 13 (A diagram of the structure of the first embodiment of the erasing operation by which the hole is erased in 丽08·^01 = 根据 according to the present invention. Figs. 14A to 14D are diagrams according to Fig. 14A to Fig. 14D In the memory of the present invention, the structure diagram of the energy band-guide band (four) church, the door 4, and the social (10) (10) embodiment is carried out. The finite element diagram ISA of the erase erasing operation of the thermal erasing is to explain (10) according to the present invention. Stylized structure diagram. The Fu r 7 inter-complement diagram is a phase diagram illustrating the second bit effect of the right bit according to the present invention. I6 is said to be a hybrid operation. The first embodiment of the top oxide of the MNONOS thin film transistor memory device. The layer ",", and the mouth structure - Figure 17 illustrates the use of the ONONOS in the on mode operation according to the present invention. The first oxidization of the top layer of the material in the middle layer of the shovel is the second layer of the dielectric structure used in the open mode. (4) The structural diagram of the first method of the two secrets, which applies to the MNONOS memory and the MNONONOSI memory. The second embodiment is both, and to FIG. 19C is a method for increasing the thickness of the (4) two-part secret in the 多层-part multilayer dielectric structure in the turn-on mode (4) according to the present invention. A structural diagram of the method, which is applicable to both the first and second embodiments of the MN〇N〇s memory and the MNONONOS memory. • Figure 20 is a diagram illustrating the left position in the MNONOS memory of the MNONOS memory according to the present invention. A stylized structural diagram of a meta-element is a corresponding diagram illustrating the second bit effect of the right bit according to the present invention. Figure 21 illustrates a book T applied to the MONONS memory used in the on mode operation in accordance with the present invention. A first embodiment of a bottom oxide of a multilayer dielectric structure in a body. Figure 22 illustrates a second embodiment of a bottom oxide having a multilayer dielectric structure implemented in a MONOOS memory for use in an on mode operation in accordance with the present invention. Embodiment 23. Figure 23 illustrates a third embodiment of a bottom oxide having a multilayer dielectric structure implemented on a polycrystalline substrate in a MONONS TFT memory for use in an on mode operation in accordance with the present invention. Figure 24 says A fourth embodiment of a bottom oxide having a multilayer dielectric structure implemented on a polycrystalline substrate in a M〇N〇N〇S TFT memory for use in an on mode operation in accordance with the present invention. A first embodiment of a %(hk)nos FF structure used in an on-mode operation in accordance with the present invention, the m(hk)n〇s memory structure having two bits per-memory cell and A high dielectric material stack layer is on the dream substrate. Figure 26 illustrates a second embodiment of a Μ (HK) NOS memory structure used in an on mode operation in accordance with the present invention, in the % (dish) 42 200805679 P940260 19580twf .doc/e NOS Memory Structure The high dielectric material stack is layered on a polycrystalline 14 substrate. 27A to FIG. 7C are structural diagrams illustrating a first method for increasing the second bit margin of the M (HK) memory structure used in the turn-on mode operation according to the present invention. The (HK) N0S memory structure has a high dielectric material stack layer on the germanium or polysilicon substrate. 28A to 28C are structural diagrams illustrating a second method for increasing a second bit margin of a Μ (HK) NOS memory structure used in an on mode operation in accordance with the present invention, Μ (HK) NOS is a high-dielectric material stack layer on a germanium or polycrystalline substrate. 〜 σ Figure 29A is a structural diagram illustrating the materialization of the left bit of M (HK) N 〇 s memory or % (HK) NQS TFT memory according to the present invention. Figure 29B is a corresponding diagram illustrating the second bit effect of the right bit in accordance with the present invention. Figure 30 is a diagram showing the process of erasing a SONOS-type or TFT_S0N0S memory by applying a positive gate voltage in accordance with the present invention. Figure 31 is a flow chart showing the process of erasing SONOS-type or TFT_S0N0S memory by pre-programming a negative gate voltage in accordance with the present invention. Figure 32 is a flow chart showing the process of pre-programming the S〇N〇S type or TFT-SONOS memory having a top oxide structure in accordance with the present invention. Figure 33 is a flow chart showing the process of pre-programming the SONOS-type or TFT_SONOS memory having a bottom oxide structure in accordance with the present invention. Figure 34 is a flow chart illustrating the process of pre-programming the SONOS-type or TFT-SONOS memory including the high dielectric material 43 200805679 P940260 19580 twf.doc/e material in accordance with the present invention. [Description of main component symbols] 100: Charge trapped in memory cell 110: P-type substrate 112, 114, 1620, 1622, 1720, 1722, 2120, 2122, 2220, 2222, 2320, 2322, 2420, 2422, 2520, 2522, 2620 2622: n+ doped regions 120, 1630, 1730, 2130, 2230, 2330, 2430, 2530, 2630: bottom dielectric structures 130, 212, 312, 410: charge trapping structures 140, 1660, 1760, 2160, 2260, 2360, 2460, 2560, 2660: p-type polycrystalline layer 150, 230, 330, 430, 1670, 1770, 2170, 2270, 2370, 2470, 2570, 2670: gate voltage Vg 152, 232, 332, 432 , 1672, 1772, 2176, 2276, 2376, 2476, 2576, 2676: substrate voltage Vsub 156, 234, 334, 434, 1674, 1774, 2172, 2272, 2372, 2472, 2572, 2672: drain voltage Vd 158, 236 '336, 436, 1676, 1776, 2174, 2274, 2374, 2474, 2574, 2674: source voltage Vs 160, 170, 240a, 240b, 340a, 340b, 420, 422, 1310, 1330, 1360, 1410, , 1430, 1460, 1480, 1810, 1830, 1850, 1910, 1930, 1950, 2710, 2730, 2750, 2810, 2830, 2850: arrow 4 4 200805679 P940260 19580twf.doc/e 162, 814, 1514, 2014, 2914: right bits 172, 1320, 1340, 1420, 1440, 1820, 1840, 1920, 1940, 2720, 2740, 2820, 2840: electrons 180, 1350, 1450, 1470: holes 200, 300: SONOS memory 210, 310: first dielectric layer 214, 314: second dielectric layer 220, 320: n-type polysilicon layer 500, 600, 700, 3000, 3100 3200, 3300, 3400: processes 510, 520, 610, 620, 710, 720, 3Ό10, 3020, 3030, 3110, 3120, 3130, 3210, 3220, 3230, 3310, 3320, 3330, 3410, 3420, 3430: Step numbers 810, 1510, 2010, 2910: Charges 812, 1512, 2012, 2912: Left bits 820, 1520, 2020, 2920: Curve 1100: MNOS-SOI memory 1110, 1210: 矽 substrate 1120, 1140, 1220, 1652, 1752, 1756, 2134, 2150, 2232, 2236, 2250, 2334, 2350, 2432, 2436, 2450: oxide layer 1130, 1230: channel 1132, 1232: n + source region 1134, 1234: n + bungee region 45 200805679 P940260 19580twf.doc/e 1640, 2540: Charge trapping layer polysilicon gate gate 曰 gate bias source voltage is not The thickness t of the substrate voltage of the voltage

1200 : MONOS-SOI memory 1240 : bottom oxide layer 1260 : top oxide layer 1600 : MNONOS memory 1610 , 1710 , 2110 , 2210 , 2310 , 2410 , 2510 , 2610 : P type germanium substrate 1650 , 1750 : top Electrical structures 1654, 1740, 1754, 2132, 2140, 2234, 2240, 2332

1150 1160 1170 1172 1174 1176 1190 1250 1270 1280 1282 1284 1286 1290 2340, 2434, 2440, 2640: nitride layer 1700, 2200: MONONOS memory 1860a, 1860b, 1960a, 1960b, 2760a, 2760b, 2860a, 2860b: electricity Hole Charge 2100 : MONONS Memory, 2300 : MONONS TFT Memory 2400 : MONONOS TFT Memory 2500, 2600 : Μ (HK) NOS Memory 2550, 2650 : High Dielectric Material Stack Layer 46

Claims (1)

200805679 F940260 19580twf.doc/e X. Patent application scope: 1. A memory element having a plurality of bits has a left bit and a right bit, including: ^ Soul memory element substrate; < I is placed in the foregoing The bottom dielectric on the substrate has one or more dielectric layers; the bottom dielectric junction covering the bottom dielectric structure is disposed on the top surface of the first charge trapping layer to cover the top dielectric structure a conductive layer, a layer; and wherein the aforementioned memory element has a transmissive voltage level. : ? The skin is erased to the negative 2. As described in the application, there are t pieces of 'the aforementioned bottom dielectric structure including the cover nitride; the memory of the voxel bit · (5) the first dielectric layer and The first structure includes a second charge trapping layer. 4. The aforementioned second charge trapping layer of the first-f electrical layer of the patent application. The body element, wherein the aforementioned memory has a plurality of bits. , 靴 型 专 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The conductive layer comprises a plurality of bits of memory. The memory substrate having a plurality of bits is described in the item. The device has a plurality of cells. The memory element having a plurality of bits as described in claim 1 wherein the foregoing substrate comprises a polycrystalline germanium substrate. 9. The memory device having a plurality of bits as described in claim 1 The aforementioned right bit is stylized through a highly stylized operation of the channel. A memory element having a plurality of bits as described in claim 9 wherein said left bit is programmed by said channel high-tune operation. 11) as claimed in claim 1 a memory device having a plurality of bits in which the memory device is erased by a tunneling erase operation. The tunneling erase operation is performed by moving a hole from the conductive layer to the first The memory element is erased to the aforementioned negative voltage level. The memory element having a plurality of bits as described in claim 10, wherein the memory element passes through the hole tunneling Except for the erase operation, the hole tunneling erase operation is performed by moving the hole from the substrate to the first charge trapping structure to the memory cell 2 = the aforementioned negative voltage level. ^ J 13· a memory element having a plurality of bits having a plurality of bits, said θ 丨 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The bottom dielectric structure has one or more layers; 48 200805679 P940260 ] 9580twi: doc / e cover the aforementioned bottom dielectric dream configuration in front of the first climbing 0, - charge trapping layer; covering the aforementioned top dielectric: two (b) the top dielectric layer; and the memory element therein; the voltage threshold of the initial critical voltage level = the second 钚 操作 operation is erased to be lower than the initial 14. As claimed in the patent range 1 - ;: component, wherein the aforementioned bottom Dielectric structure = the dielectric layer of the bit. I includes the 盍 化 化 化 · · · · · · · · · · · · · · · · · · · · · · · , , , , , , , , , , , , , , , The electric layer and the second dielectric layer cover the body = medium: ^ Li Weiwei said that there are more than one of the only ones mentioned in Item 13 of the 祀 Λ Λ 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 极 极 极 极A plurality of memory elements having a plurality of memory elements, wherein the conductive layer comprises a p-type 70, as described in claim 13 of the patent application, wherein the conductive layer comprises a metallographic phase. pole. A note of 70. A plurality of memory elements as described in claim ls, wherein the aforementioned substrate comprises a stone substrate. A note of k. A plurality of memory elements as recited in claim 13 wherein said substrate comprises a polycrystalline substrate. The record of Lifan 21. As described in the scope of claim patent item n, there are multiple-"memory elements, in which the above-mentioned right-bit transmission channel is highly stylized operation === 49 200805679 P940260 19580twf.doc/e ZZ•Ge Mouth 绢 绢 和 和 和 厣 和 和 和 和 和 和 和 和 和 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 绢 厣 厣 厣 厣 厣 厣 厣 厣 厣 厣 厣 厣 厣The component, wherein one of the aforementioned memory locations is erased, and the foregoing electrical 祠 wears the erase erase operation:: the layer moves to the foregoing charge trapping structure, so that the gas hole is electrically conductive from the front: the bulk component is erased To the lower than the initial initial; =: 3⁄4 24. If the application of the Su Sui Shouyi element, the memory of the above memory element is erased, the above-mentioned electric 祠 wear and erase operation = electric / 5 teeth Moving to the aforementioned first-charge trapping structure with the erasing operation = causing the hole from the aforementioned substrate to be lower than the aforementioned initial criticality problem: the eraser element is erased to have a plurality of tit: level. The memory element has a memory cell substrate; ~工7^right bit, including: ^ The charge of the bottom dielectric layer of the ruthenium layer on the substrate. The ancient octa-', a layer of high dielectric material disposed on the aforementioned charge trapping layer And the memory component is erased to the negative threshold by wiping. 26. As described in claim 25, there are multiple bits of the record 50 200805679 ry4UZ〇u 19580twf.doc/e The memory element includes an n-type polysilicon gate. The memory element having a plurality of bits as recited in claim 25, wherein the conductive layer comprises a p-type polysilicon gate. A memory element having a plurality of bits as described in claim 25, wherein the conductive layer comprises a metal gate. 29. A memory element having a plurality of bits as recited in claim 25 The foregoing substrate includes a germanium substrate. 30. The memory device having a plurality of bits according to claim 25, wherein the substrate comprises a polycrystalline germanium substrate. 31. Multiple bit records And a memory element having a plurality of bits as described in claim 31, wherein the left bit passes through the channel is high. 33. A memory element having a plurality of bits as described in claim 32, wherein the memory element is erased by a tunneling erase operation, the through hole The tunnel erase operation erases the memory device to the aforementioned negative threshold voltage level by moving the hole from the conductive layer to the charge trapping structure. 34. The memory device having a plurality of bits according to claim 32, wherein the memory device is erased by a tunneling erase operation, and the tunneling erase operation is performed by using a hole. The hole is moved from the aforementioned substrate to the aforementioned charge trapping structure to erase the aforementioned memory device to the aforementioned negative threshold voltage level of 51 200805679 P940260 19580 twf.doc/e. 35. A memory element having a plurality of bits having a plurality of bits, the memory element having a left bit and a right bit, comprising: a substrate; a bottom dielectric layer disposed on the substrate; a charge trapping layer of the bottom dielectric structure; a high dielectric material layer disposed on the charge trapping layer; and a conductive layer covering the high dielectric material layer; wherein the memory device is erased by an erase operation A voltage level below the initial threshold voltage level. 36. A memory element having a plurality of bits as recited in claim 35, wherein said conductive layer comprises an n-type polysilicon gate. 37. A memory element having a plurality of bits as recited in claim 35, wherein said conductive layer comprises a p-type polysilicon gate. 38. A memory element having a plurality of bits as recited in claim 35, wherein said conductive layer comprises a metal gate. #39. A memory element having a plurality of bits as recited in claim 35, wherein the substrate comprises a germanium substrate. 40. A memory element having a plurality of bits as recited in claim 35, wherein the substrate comprises a polycrystalline substrate. 41. A memory element having a plurality of bits as recited in claim 35, wherein said right bit is programmed by a channel high program operation. 42. As described in claim 41, there are multiple bits of the record 52 200805679 P940260 19580twf.doc / em body is programmed /, ^ bit through the aforementioned channel high stylization operation 43 · apply The scope of the patent is the a-thmemory element, and the note of the above-mentioned reporter and the one-piece of the shirt is erased, and the hole is worn by the second hole, and the layer is moved to the aforementioned charge. Reading the above-mentioned electrical conductivity in the aforementioned initial gg boundary, the first component is erased to a low level * as applied for a patent/level. a memory element in which the aforementioned mark = red has a plurality of bits erased. The aforementioned hole piercing with the hole is moved to the aforementioned charge trapping structure with the hole erasing operation and the second hole is from the base of the substrate. The aforementioned element is erased to less than 45. For example, if the patent application is for a dry component, the blue element has a plurality of bits as described in the arrow item of Fig. 46. If the application material includes the Griffin 20" ^ Component, straight + meaning, '% item has a number of bits / '1 ^ 4 high media _ material package secretization to the incentive 2. ^ 53