200805387 九、發明說明： 【發明所屬之技術領域】 本發明為關於一種記憶體電路，特別是一種具有一資 料轉換電路的記憶體電路，可使得寫入記憶體電路内的預 備f線上的資料與直接由預備字線所補的記憶胞上直 接項取到的資料相同。 【先前技術】 記^體電路在製造時，為避免其中少數的記憶胞損壞 而使侍i個記憶體無法使用，在電路設計上 電路，用以修補損壞的記憶胞。在；：體： =或=記憶輯財，記缝由—字線與—位元線所驅 動:而母-字線耗接第-位元線（bit line，bl) 位元線（inversecj bit line W) ^ > 〆、、 的記憶胞時係將該記憶胞賴接的用 列電路中_料線整絲代。 _礼體陣 的执因十為因第^與第二位元線在設計上係成組成組 也："二/的第一位元線與第二位元線的設計上 貝壞記憶胞的字線制記憶體電 ^ ::線：因此在替換時會一次替換兩條字線。雖以： 方式可以達到修補的目的，但是可能 "" =的字線或·接第二位元線的字線= 客戶編號·· 922617/13/20Ό6 本所編號：0548-A50294tw/final/brent :二ΐ::,接第一位元線的字線或1 ㈣二二 =2,61=w計更多的預備字線，增 5 200805387 路面積。 習知另一種修補損壞的字線的方法就是將受損的字 線，直接替換預備的字線，這樣的修補方式對使用者而言 不會造成資料儲存上的問題，但對測試機台來說，因為無 法得知修補受彳貝的子線是屬於輕接弟一位兀線的字線或 柄接弟二位元線的字線，而用以替換的預備子線所輕接的 位元線是否為相同狀態（BL或亙），在對記憶體進行測試 時造成對結果錯誤的判斷，使得應該是正常的記憶體被判 讀為不正常的記憶體而被報廢，增加公司的損失。 • 舉例來說，若有一筆資料為【00101】寫入耦接第一 位元線的字線，則在該字線上可直接讀取到【00101】的 資料。若今天是儲存在耦接在第二位元線的字線，則直接 讀取該字線上的資料則可能讀取到【11010】的資料。而 記憶體的測試過程中是會不斷輸入0或1，並觀察記憶體 内部位元線上是否讀到相同的0或1，若今天修補的位元 線與損壞的位元線為不同狀態，可能造成輸入0而讀取到 1，但是記憶體卻是正常的情形。因此如何設立一機制以 Φ 避免這種情形發生是必需的。 【發明内容】 本發明的目的為解決記憶體電路中損壞字線所耦接 的位元線與修補字線所耦接的位元線狀態不同時，資料在 寫入修補字線後無法得知其確實的資料内容的問題。 本發明提供一種記憶體電路，包括一主要記憶矩 陣、一主要解碼電路、一主要驅動電路、一備用記憶矩陣、 一備用解碼電路、一備用驅動電路以及一資料處理電路。 客戶編號：922617/13/2006 6 本所編號：0548-A50294tw/final/brent 200805387 該主要記憶矩陣，包括複數條主要字線、複數條200805387 IX. Description of the Invention: [Technical Field] The present invention relates to a memory circuit, and more particularly to a memory circuit having a data conversion circuit for enabling data written on a preliminary f line in a memory circuit The data obtained directly from the direct items on the memory cell supplemented by the preliminary word line are the same. [Prior Art] In the manufacture of the circuit, in order to avoid a small number of memory cell damage, the memory can not be used, and the circuit is designed to repair the damaged memory cell. In the :: body: = or = memory memory, the seam is driven by the word line and the bit line: and the mother-word line consumes the bit line, bl bit line (inversecj bit Line W) ^ > The memory cell time of 〆, , is the whole line of the line in the memory circuit. _ The role of the ritual array is due to the design of the ^ and the second bit line in the group also: "two / the first bit line and the second bit line design of the upper bad memory cell Word Line Memory Memory :: Line: Therefore, two word lines are replaced at a time when replacing. Although the method can be used for repairing, it is possible that the word line of the "" = or the word line of the second bit line = customer number·· 922617/13/20Ό6 The number of the office: 0548-A50294tw/final /brent : 二ΐ::, the word line of the first bit line or 1 (four) two two = 2,61=w count more preparatory word lines, increase 5 200805387 road area. Another way to repair a damaged word line is to replace the damaged word line directly with the prepared word line. Such a repair method does not cause problems in data storage for the user, but comes to the test machine. Said, because it is impossible to know that the sub-line of the repaired mussel is the word line of the one-line line of the light-handed brother or the word line of the two-dimensional line of the handle, and the bit of the spare line to be replaced is replaced. Whether the meta-line is in the same state (BL or 亘), when testing the memory, causes a judgment of the result error, so that the normal memory is judged to be abnormal memory and is scrapped, increasing the company's loss. • For example, if a piece of data is written to [00101] a word line coupled to the first bit line, the data of [00101] can be directly read on the word line. If today is stored in the word line coupled to the second bit line, then directly reading the data on the word line may read the data of [11010]. In the memory test process, it will continuously input 0 or 1, and observe whether the same 0 or 1 is read on the memory part of the memory. If the repaired bit line and the damaged bit line are in different states, it may be Causes input 0 and reads 1 but the memory is normal. So how to set up a mechanism to avoid this situation is necessary. SUMMARY OF THE INVENTION The object of the present invention is to solve the problem that when the bit line coupled between the damaged word line and the bit line connected by the repair word line is different in the memory circuit, the data cannot be known after being written into the repair word line. The question of its exact content. The present invention provides a memory circuit comprising a primary memory matrix, a primary decoding circuit, a primary drive circuit, a spare memory matrix, a spare decode circuit, a spare drive circuit, and a data processing circuit. Customer ID: 922617/13/2006 6 Our number: 0548-A50294tw/final/brent 200805387 The main memory matrix, including a plurality of main word lines, a plurality of lines
線以f複數個主要記憶元件，該主要記憶元料㈣H 要子線與該寺主要位元線控制，用以 :要，= 條第-位元線與複數條第幺^ 線，母一该主要子線熬接該等第—位元線或 線。該主要解碼電路’接收複數個主要字線盘主要位元線 =貧料’並解碼成複數魅要位元線㈣與複數個主要 子線位址。該主要驅動電路，根據 線^複數^用巨I -，備用5己憶矩陣’包括複數條備用字 線稷數“備用位兀線以及複數個備用 用記=件接受該等備用字線與該等備用位二=寻: :元，壞之主要字線與主要 第一位元線與複數條第二 :==該等第一位元線或該等第二位元線。該 複數個備用字線與複數個備用位元線 線位址與複數個備用 該等主要字^ ί線備用以替換 主要字錄的你'、、寸以備用子線的位址與該 用驅動電路，根據被=存在—溶絲盒中。該備 r元線與備用字線以驅動該備用記憶矩 7地電路，根據該轉換資料使寫入該圮,!#體電 與該位元資料編記憶元件= 客戶編號：922617/13/2006 本所編號：Q54^A5G294tw/final/brent ? 200805387 陳么务明更提供一種記憶體電路，包括-主要纪，矩 一備；解t二:電路、一主要驅動電路、-備用記憶矩陣、 j用％碼％路、一備用驅動電路 料處理電路。該主要㈣㈣w u路以及一一貝 數條主要付-綠車’包括複數條主要字線、複 致裇主要位兀線以及複數個主要記憶元 ί接要字線與料主要位元線控制，用以館ί ΐ ί:ϊ ίτ要字線輕接該等第-位元線或該等 擇解碼電路’接收複數個主要字線與主 二要子線位址。該主要驅動電路，根據該 =址與料主要字線位址選擇料主要位 二=、Λ備用位元線以及複數個備用記憶元 :二ΐ 接受該等備用字線與該等備用位元 it:::儲存資料’且該備用矩陣用以提辑 ^線兵備用位元線供損壞之主要字線與主要位元線使 第^位元1專備用位元線包括複數條第一位元線與複數條 _用字_接該等第一位元線或該等 該備用解碼電路用以接收複數個備用字線與 位址Γ ::線選擇資料’並解碼成複數個備用位元線 =與複數個備用字線位址。當該等備用字線中的一條備 用以替換該等主要字線中的—主要字線時，該備 】予:=咖主要字線的位址的一轉換資 該備用_電路’根據該等備用位元線位 止^該專備用字線位址選擇該等備用位元線.與備用字線 客戶編號：922617/13/2006 ： 〇548-A50294tw/final/brent 8 200805387 備用子線所耦接的位元線同為第一或第二位元二2:、 制信號具有一第一電壓準位·告 口寸“控 位：線不同為第一或第二位元線時，該控制信號具 1寫入;Jit該一資料處理電路根據該控制信號料 呓情元：;ί电路的一位元資料與該位元資料儲存的 忑k兀件上碩取到的位元資料相同。 ^發明更提供-種記憶體電路内資料轉換方法，包括 ^ Y W .提供—損壞字線的位址資料；提供對應該損壞 :^一修補位it線的位址資料；比較該損壞字線的位址 貝料：、該修補字線的位址資料，並輸出—比較結果；以及 根據該，較結果產生—控制信號’並輸出至—資料轉換電 路，使得寫入該修補字線的位元資料與該修 到的位元資料相同。 貝取 ；讓本發明之上述和其他目的、特徵、和優點能更明 ”、、頁易丨董，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： " 【實施方式】 第1圖為根據本發明的一實施例的流程圖。步驟Si〇 為接收損壞的字線的位址資料。步驟S11為接收用以修補 該損壞的字線的備用字線的位址資料。步驟S12為比較該 損壞的字線的位址資料以及該備用字線的位址資料，以判 斷該損壞的字線與該備用字線所耦接的位元線是否同為 第一位元線或第二位元線。步驟S13為根據比較結果輸出 客戶編號：922617/13/2_ 柄編獍：Q548-A5C)294tw/final/brent 9 200805387 一控制信號，若該損壞的字線與該備用字線所耦接的位元 線同為第一位元線或第二位元線，則輸出一邏輯準位〇的 控制信號;若該損壞的字線與該備用字線所耦接的位元線 不同為第一位元線或第二位元線，則輸出一邏輯準位1的 控制信號。一資料轉換電路接收該控制信號，使得寫入備 用字線的位元資料與直接由該備用字線所驅動的記憶胞 上讀取到的位元資料相同。 第2圖為根據本發明之一實施例的方塊示意圖。當資 料要寫入記憶裝置20或自記憶裝置20讀取資料時，必須 • 透過一資料轉換裝置27。資料轉換裝置27耦接主要解碼 電路25與備用解碼電路26，以便將位址資訊傳送至對應 的主要解碼電路25或與備用解碼電路26。解碼電路將解 碼後的貧料傳送至主要驅動電路23或備用驅動電路24 5 用以驅動主要記憶矩陣21或備用記憶矩陣22中對應的位 元線。當自主要記憶矩陣21或備用記憶矩陣讀取資料 時，會先透過第一級感測放大器29以及第二級感測放大 器28將信號放大後傳送至資料轉換裝置27。 φ 資料轉換裝置27内有一熔絲盒（圖上未繪出），儲 存有主要記憶矩陣21中損壞的字線以及位於備用記憶矩 陣中用以替換該損壞的字線的備用字線的位址資料。當為 寫入狀態時，若資料轉換裝置27發現寫入的資料其原先 對應的字線損壞而以備用記憶體矩陣22中備用字線替代 時，資料轉換裝置27會先去判斷損壞的字線與替代的字 線所耦接的位元線是否為相同狀態。若狀態相同，則使寫 入資料直接寫入；若狀態不相同，則使第二級感测放大器 28接收到的資料與資料轉換裝置27接受到的資料反向。 客戶編號：922617/13/2006 本戶斤編號：0548-A50294tw/final/brent 10 200805387 當為讀取狀態時，若資料轉換裝 士 替代時，資料轉換裝置27會先去彳齡 中備用子線 的字線職接的位元線是否為的字線與替代 直接綠敌筮-你式、日丨a 狀恶。若狀態相同，則 接靖取弟—級感測放大器28傳 同，則資料轉換裝置27在接 〕貝科，右狀悲不相 送的資料時，對該資料反向。 及感測放大器28傳 弟3圖為第2圖中資料韓拖奘娶 意圖。資料轉換裝置27包^資^一實施例的示 有一溶絲盒（圖上未緣出），儲存有主要記^陣21^ 線以及位於備用記憶矩陣中用以^ 轉ΓΐΓί用子線的位址資料。#要寫人或讀取資料時， 31會檢查要寫入或讀取的資料的位址 ^於441内的位址資料，若無則直接透過寫入/讀 取電路Γ寫入或讀取資料。若欲寫入或讀取的資料的i 址位於丈谷絲盒内的位址資料時，則傳送該位址資料至比較 ::I”交電路32會_位址資料判斷損壞的字線以 及備用子線是否同為第一位元線或第二位元線，並輸出對 應的控制信號至寫入/讀取電路33。寫入/讀取電路33合 根據控制信號決定是否要使第二級感職Α|| 28接收~ 輸出，資料與寫人/讀取電路33所寫人/讀取反向。 第4圖為第3圖中寫入/讀取電路33的一實施例的示 意圖。寫入/讀取電路33包括互斥或閘44與互斥或閘必。 互斥或閘44具有輸入端41與42，輸入端41甩以接收比 較電路32產生的控制信號，輸入端42用以接收寫入資 客戶編號·· 922617/13/2006 本所編號·· 0548-A50294tw/finai/brent 11 200805387 料’互斥或間44亦具有一輸出端48，輕接至弟二級感測 放大器28。互斥或閘45具有輸入端46與47，輸入端46 用以接收比較電路32產生的控制信號，輸入端47耦接第 二級感測放大器28，用以接收資料，輸出端43則用以輸 出第二級感測放大器28傳送的資料。當比較電路32判斷 損壞的位元線以及備用位元線同為第一位元線或第二位 元線時，輸出一邏輯準位0的信號，此時輸入端42與輸 出端48的資料相同，輸入端47與輸出端43的資料相同。 當比較電路32判斷損壞的位元線以及備用位元線不同為 • 第一位元線或第二位元線時，輸出一邏輯準位1的信號， 此時輸入端42與輸出端48的資料便互為反相，輸入端 47與輸出端43的資料亦互為反相。利用這樣的寫入/讀取 機制便可使得讀取或寫入的資料不因為損壞的位元線與 其替換的位元線的狀態不同，而造成在記憶體的儲存的資 料與實際寫入的資料不同的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 φ 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 客戶編號：922617/13/2006 本所編號：0548-A50294tw/final/brent 12 200805387 【圖式簡單說明】 f ^圖為根據本發明的一實施例的流程圖。 二圖為=據本發明之一實施例的方塊示意 弟圖為第2圖中資料轉換裝置27 :: 意圖。 J貝施例的示 第4圖為第3圖中寫入/讀取電路3 — 意圖。 貝施例的示The line is divided into a plurality of main memory elements, and the main memory element (4) H is to be controlled by the main line of the temple, and is used to: =, the first bit line and the plurality of lines, the mother line The main sub-line is connected to the first bit line or line. The main decoding circuit 'receives a plurality of main word line disc main bit lines = poor material' and decodes into a plurality of fascinating bit lines (4) and a plurality of main sub-line addresses. The main driving circuit, according to the line ^ complex number ^ using the giant I -, the standby 5 memory matrix 'including a plurality of spare word line parameters "alternate bit line and a plurality of spare words = accept the alternate word line and the Equal spare bit 2 = seek: : yuan, bad main word line and main first bit line and plural number second: == the first bit line or the second bit line. The plural number of spare Word line and a plurality of spare bit line address and a plurality of spare main words ^ ί line spare to replace the main word record of your ',, inch with the address of the spare line and the drive circuit, according to = exists - in the solution box. The standby r-element line and the spare word line are used to drive the circuit of the spare memory moment 7, and the circuit is written according to the conversion data, !# body power and the bit data editing memory element = Customer ID: 922617/13/2006 The number of the firm: Q54^A5G294tw/final/brent ? 200805387 Chen Mowu Ming provides a memory circuit, including - the main discipline, the moment of preparation; the solution of two: the circuit, a main drive Circuit, - spare memory matrix, j with % code % way, a spare drive circuit material processing circuit. (4) (4) w u road and one-to-one number of main pay-green vehicles 'including a plurality of main word lines, Fuzhi 裇 main line and a plurality of main memory elements ί connect the main line and material main bit line control, use The main drive circuit, according to the =, ί ί ί ί τ ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί Address and material main word line address selection material main bit 2 =, Λ spare bit line and a plurality of spare memory elements: 2 接受 accept the alternate word line and the spare bits it::: store data 'and The spare matrix is used to provide the main word line and the main bit line for the damage of the spare bit line for the damage. The first bit line and the plural number of the first bit line are included in the first bit line. The first bit line or the alternate decoding circuit is configured to receive a plurality of spare word lines and address Γ :: line selection data 'and decode into a plurality of spare bit lines = and a plurality of spare word lines Address. When one of the alternate word lines is reserved to replace the main word line in the main word lines The preparation is: = a conversion of the address of the main word line of the coffee. The standby_circuit 'selects the spare bit line according to the spare bit line address. Line customer number: 922617/13/2006: 〇548-A50294tw/final/brent 8 200805387 The bit line to which the spare sub-wire is coupled is the first or second bit 2:, the signal has a first voltage Position and suffix "control position: when the line is different for the first or second bit line, the control signal has 1 write; Jit a data processing circuit according to the control signal 呓 呓:; One meta-data is the same as the bit data obtained from the 忑k file stored in the bit data. ^Inventor provides a method for data conversion in a memory circuit, including ^YW. Providing - address data of the damaged word line; providing address information corresponding to the damage: ^ repairing the bit line; comparing the damaged word line Bit address material: the address data of the repair word line, and output-comparison result; and according to the result, the control signal is generated and output to the data conversion circuit, so that the bit of the repair word line is written The information is the same as the repaired bit data. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. Embodiments Fig. 1 is a flow chart according to an embodiment of the present invention, in which step Si is receiving address data of a damaged word line, and step S11 is receiving a bit of an alternate word line for repairing the damaged word line. Step S12 is to compare the address data of the damaged word line and the address data of the spare word line to determine whether the damaged word line and the bit line coupled to the spare word line are the same as the first a bit line or a second bit line. Step S13 is to output a customer number according to the comparison result: 922617/13/2_handle: Q548-A5C) 294tw/final/brent 9 200805387 A control signal if the damaged word line The bit line coupled to the spare word line is the first bit line or the second bit line, and outputs a logic level control signal; if the damaged word line is coupled to the spare word line The bit line connected is different from the first bit line or the second bit line, then a control signal of a logic level 1. A data conversion circuit receives the control signal such that the bit data written to the spare word line is the same as the bit data read directly from the memory cell driven by the spare word line Figure 2 is a block diagram showing an embodiment of the present invention. When data is to be written to or read from the memory device 20, it must pass through a data conversion device 27. The data conversion device 27 is coupled to the main The decoding circuit 25 and the alternate decoding circuit 26 are configured to transmit the address information to the corresponding primary decoding circuit 25 or to the alternate decoding circuit 26. The decoding circuit transmits the decoded poor material to the primary driving circuit 23 or the backup driving circuit 24 5 To drive the corresponding bit line in the main memory matrix 21 or the spare memory matrix 22. When reading data from the main memory matrix 21 or the spare memory matrix, the first stage sense amplifier 29 and the second stage sense amplifier are first transmitted. The signal is amplified and transmitted to the data conversion device 27. The φ data conversion device 27 has a fuse box (not shown) in which the main memory matrix 21 is stored. The damaged word line and the address data of the spare word line in the spare memory matrix for replacing the damaged word line. When in the write state, if the data conversion device 27 finds the written data, the original corresponding word line When the damage is replaced by the spare word line in the spare memory matrix 22, the data conversion device 27 first determines whether the damaged word line and the bit line to which the alternate word line are coupled are in the same state. If the states are the same, Write data is directly written; if the status is different, the data received by the second-stage sense amplifier 28 is reversed with the data received by the data conversion device 27. Customer ID: 922617/13/2006 0548-A50294tw/final/brent 10 200805387 When it is in the read state, if the data conversion device is replaced, the data conversion device 27 will first go to the word line of the word line of the spare sub-line in the age group. Line and substitute direct green enemies - your style, sundial a. If the state is the same, then the data is transferred to the squad-level sense amplifier 28, and the data conversion device 27 reverses the data when it is connected to the data. And the sensor amplifier 28 is shown in Figure 2 as the information in the second picture. The data conversion device 27 includes a fuse box (not shown) in the embodiment, and stores a main memory 21 line and a bit in the spare memory matrix for transferring the 子 用Address information. #When writing or reading data, 31 will check the address of the data to be written or read ^ address data in 441, if not, write or read directly through the write/read circuit data. If the address of the data to be written or read is located in the address data in the Zhanggu box, then the address data is transmitted to the comparison:: I" intersection circuit 32 will address the damaged word line and Whether the spare sub-line is the same as the first bit line or the second bit line, and outputs a corresponding control signal to the write/read circuit 33. The write/read circuit 33 determines whether to make the second according to the control signal Level sense job||28 Receive~ Output, data and write/read circuit 33 written by person/read reverse. Fig. 4 is a schematic diagram of an embodiment of write/read circuit 33 in Fig. 3. The write/read circuit 33 includes a mutex or gate 44 and a mutex or gate. The mutex or gate 44 has inputs 41 and 42 that receive the control signal generated by the comparator circuit 32. Used to receive the written customer number·· 922617/13/2006 The number of the company·· 0548-A50294tw/finai/brent 11 200805387 It is expected that the 'mutual exclusion' or the inter-44 also has an output 48, which is lightly connected to the second level. Amplifier 28. Mutant or gate 45 has inputs 46 and 47, and input 46 is used to receive the control signal generated by comparator circuit 32. 47 is coupled to the second stage sense amplifier 28 for receiving data, and the output end 43 is for outputting the data transmitted by the second stage sense amplifier 28. When the comparison circuit 32 determines that the damaged bit line and the spare bit line are the same When it is the first bit line or the second bit line, a signal of logic level 0 is output. At this time, the data of the input terminal 42 and the output terminal 48 are the same, and the data of the input terminal 47 and the output terminal 43 are the same. 32: When the damaged bit line and the spare bit line are different from the first bit line or the second bit line, a logic level 1 signal is output, and the data of the input end 42 and the output end 48 are mutually In order to invert, the data of the input terminal 47 and the output terminal 43 are also mutually inverted. With such a write/read mechanism, the read or written data can be made free of damaged bit lines and their replaced bits. The state of the line is different, resulting in a problem that the stored data in the memory is different from the actually written data. Although the present invention has been disclosed in the preferred embodiments as above, it is not intended to limit the present invention, and anyone skilled in the art is familiar with the art. Without departing from the spirit of the invention And the scope of protection of the present invention is defined by the scope of the appended claims. Customer Number: 922617/13/2006 Number: 0548-A50294tw/final /brent 12 200805387 [Brief Description of the Drawings] FIG. 4 is a flow chart according to an embodiment of the present invention. FIG. 2 is a block diagram showing a data conversion device 27 according to an embodiment of the present invention. :: Intent. Figure 4 of the example of J is the write/read circuit 3 in Fig. 3 - intent. Description of the example
【主要元件符號說明】 S10〜接收損壞的字線的位址資料。 S11〜接收用以修補該損壞的字線 S12〜比較該損壞的字線的位址資 並輸出比較結果。 ' 的備用字線的位址資料。 料以及該備用字線的_， SJ3〜根據比較結果輸出—控制信號，使得寫用 位元貢料與蝴制位元線上讀取刺位元 ^心線的 2〇〜記憶裝置； …主要記憶矩陣/ 24〜備用驅動電路；25〜主要解碼電路； 26〜備用解碼電路；27〜資料轉換裝置； 28〜第二級感測放大器；29〜第一級感測放大哭. 31〜轉換資料處理電路；32〜比較電路； 22〜備用記憶矩陣21 ; 23〜主要驅動電路；[Main component symbol description] S10~ Receives the address data of the damaged word line. S11~ receives the word line S12 for repairing the damage, compares the address of the damaged word line, and outputs a comparison result. Address data for the alternate word line. _, SJ3~ according to the comparison result output-control signal, so that the write bit tribute and the butterfly bit line read the punctual bit ^2 line to the memory device; ... main memory Matrix / 24 ~ spare drive circuit; 25 ~ main decoding circuit; 26 ~ spare decoding circuit; 27 ~ data conversion device; 28 ~ second-level sense amplifier; 29 ~ first-stage sense amplification amplification crying 31~ conversion data processing Circuit; 32~ comparison circuit; 22~ spare memory matrix 21; 23~ main drive circuit;
33〜寫入/讀取電路； 48、43〜輸出端； 41、42、46、47〜輸入端； 44、45〜互斥或閘。 客戶編號：922617/13/2006 本所編號：〇548-A50294tw/finai/brent 1333~ write/read circuit; 48, 43~output; 41, 42, 46, 47~ input; 44, 45~ mutually exclusive or gate. Customer ID: 922617/13/2006 Our number: 〇 548-A50294tw/finai/brent 13