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Application filed by Powerchip Semiconductor CorpfiledCriticalPowerchip Semiconductor Corp
Priority to TW095120519ApriorityCriticalpatent/TW200746368A/en
Publication of TW200746368ApublicationCriticalpatent/TW200746368A/en
Manufacturing method of non-volatile memory is provided. A substrate having a stacked layer formed thereon is provided. The stacked layer is patterned, and then a plurality of first openings is formed in the stacked layer to expose the substrate. A dielectric layer is formed on the substrate. A plurality of conductive spacers is formed on the sidewalls of the stacked layer exposed by the first openings. A patterned mask layer is formed on the substrate to fill the first openings. The patterned mask layer has a plurality of second opening therein to expose a part of the stacked layer. A part of the stacked layer is removed to form a plurality of stacked gate structures by using the patterned mask layer as a mask. The stacked gate structures form a memory cell array between two conductive spacers.
TW095120519A2006-06-092006-06-09Manufacturing method of non-volatile memory
TW200746368A
(en)