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Application filed by Macronix Int Co LtdfiledCriticalMacronix Int Co Ltd
Priority to TW94130639ApriorityCriticalpatent/TWI286822B/en
Publication of TW200713511ApublicationCriticalpatent/TW200713511A/en
Application grantedgrantedCritical
Publication of TWI286822BpublicationCriticalpatent/TWI286822B/en
A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stacked gate structures are formed on a substrate, and a plurality of doped regions are formed in the substrate beside the stacked gate structures. Then, a plurality of spacers are formed on the sidewalls of the stacked gate structures. After that, a plurality of conductive pad layers are formed on the exposed doped regions. By forming conductive pad layers, the resistance of doped regions in the memory cell can be reduced.
TW94130639A2005-09-072005-09-07Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory
TWI286822B
(en)
Method of manufacturing a sonos memory device with optimized shallow trench isolation, a sonos memory device with optimized shallow trench isolation and a semiconductor device comprising such a sonos memory device