TW200746167A - Memory systems capable of reducing electromagnetic interference in data lines - Google Patents
Memory systems capable of reducing electromagnetic interference in data linesInfo
- Publication number
- TW200746167A TW200746167A TW096102862A TW96102862A TW200746167A TW 200746167 A TW200746167 A TW 200746167A TW 096102862 A TW096102862 A TW 096102862A TW 96102862 A TW96102862 A TW 96102862A TW 200746167 A TW200746167 A TW 200746167A
- Authority
- TW
- Taiwan
- Prior art keywords
- data lines
- electromagnetic interference
- reducing electromagnetic
- memory systems
- systems capable
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060010915A KR100744125B1 (ko) | 2006-02-04 | 2006-02-04 | 데이터 라인들의 전자파 간섭을 감소시킬 수 있는 메모리시스템 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200746167A true TW200746167A (en) | 2007-12-16 |
Family
ID=38289004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096102862A TW200746167A (en) | 2006-02-04 | 2007-01-25 | Memory systems capable of reducing electromagnetic interference in data lines |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070186072A1 (zh) |
KR (1) | KR100744125B1 (zh) |
DE (1) | DE102007006293A1 (zh) |
TW (1) | TW200746167A (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8207976B2 (en) * | 2007-03-15 | 2012-06-26 | Qimonda Ag | Circuit |
KR100910446B1 (ko) * | 2007-12-03 | 2009-08-04 | 주식회사 동부하이텍 | 디스플레이 장치용 i2c 타임 콘트롤러의 데이터 동기화구현 회로 및 방법 |
KR100942942B1 (ko) * | 2008-04-30 | 2010-02-22 | 주식회사 하이닉스반도체 | 다양한 입/출력 모드를 갖는 반도체장치 |
KR101188264B1 (ko) * | 2010-12-01 | 2012-10-05 | 에스케이하이닉스 주식회사 | 반도체 시스템, 반도체 메모리 장치 및 이를 이용한 데이터 출력 방법 |
US11513725B2 (en) * | 2019-09-16 | 2022-11-29 | Netlist, Inc. | Hybrid memory module having a volatile memory subsystem and a module controller sourcing read strobes to accompany read data from the volatile memory subsystem |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010011501A (ko) * | 1999-07-28 | 2001-02-15 | 김영환 | 메모리셀 어레이의 프로그램 간섭 방지회로 |
KR100587052B1 (ko) * | 2000-06-30 | 2006-06-07 | 주식회사 하이닉스반도체 | 고속 인터페이스용 장치 |
JP2002324398A (ja) * | 2001-04-25 | 2002-11-08 | Mitsubishi Electric Corp | 半導体記憶装置、メモリシステムおよびメモリモジュール |
WO2003098637A1 (en) * | 2002-05-22 | 2003-11-27 | Koninklijke Philips Electronics N.V. | Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference |
TW576976B (en) * | 2002-06-26 | 2004-02-21 | Via Tech Inc | Output circuit of strobe signal or parallel data signal |
US7486702B1 (en) * | 2003-08-11 | 2009-02-03 | Cisco Technology, Inc | DDR interface for reducing SSO/SSI noise |
US6975557B2 (en) * | 2003-10-02 | 2005-12-13 | Broadcom Corporation | Phase controlled high speed interfaces |
KR20060056509A (ko) * | 2004-11-22 | 2006-05-25 | 주식회사 하이닉스반도체 | 반도체 장치 |
KR100674953B1 (ko) * | 2005-02-05 | 2007-01-26 | 학교법인 포항공과대학교 | 반도체 메모리의 등화 수신기 |
-
2006
- 2006-02-04 KR KR1020060010915A patent/KR100744125B1/ko not_active IP Right Cessation
-
2007
- 2007-01-19 US US11/655,194 patent/US20070186072A1/en not_active Abandoned
- 2007-01-25 TW TW096102862A patent/TW200746167A/zh unknown
- 2007-02-01 DE DE102007006293A patent/DE102007006293A1/de not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
DE102007006293A1 (de) | 2007-08-23 |
KR100744125B1 (ko) | 2007-08-01 |
US20070186072A1 (en) | 2007-08-09 |
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