TW200745842A - Securing scan test architecture - Google Patents

Securing scan test architecture

Info

Publication number
TW200745842A
TW200745842A TW095136358A TW95136358A TW200745842A TW 200745842 A TW200745842 A TW 200745842A TW 095136358 A TW095136358 A TW 095136358A TW 95136358 A TW95136358 A TW 95136358A TW 200745842 A TW200745842 A TW 200745842A
Authority
TW
Taiwan
Prior art keywords
securing
scan test
test architecture
scan
architecture
Prior art date
Application number
TW095136358A
Other languages
English (en)
Other versions
TWI325534B (en
Inventor
Andrew Morgan
David Dunn
Original Assignee
Transmeta Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transmeta Corp filed Critical Transmeta Corp
Publication of TW200745842A publication Critical patent/TW200745842A/zh
Application granted granted Critical
Publication of TWI325534B publication Critical patent/TWI325534B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/50—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using hash chains, e.g. blockchains or hash trees
TW095136358A 2005-09-29 2006-09-29 Securing scan test architecture TWI325534B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/241,104 US7334173B2 (en) 2005-06-28 2005-09-29 Method and system for protecting processors from unauthorized debug access

Publications (2)

Publication Number Publication Date
TW200745842A true TW200745842A (en) 2007-12-16
TWI325534B TWI325534B (en) 2010-06-01

Family

ID=37906495

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095136358A TWI325534B (en) 2005-09-29 2006-09-29 Securing scan test architecture

Country Status (3)

Country Link
US (2) US7334173B2 (zh)
TW (1) TWI325534B (zh)
WO (1) WO2007041356A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104346583A (zh) * 2013-07-23 2015-02-11 阿尔特拉公司 用于保护可编程器件的配置扫描链的方法和装置

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FR2888433A1 (fr) * 2005-07-05 2007-01-12 St Microelectronics Sa Protection d'une quantite numerique contenue dans un circuit integre comportant une interface jtag
CN101238381A (zh) * 2005-08-10 2008-08-06 Nxp股份有限公司 测试包含秘密信息的集成电路的方法
FR2897439A1 (fr) * 2006-02-15 2007-08-17 St Microelectronics Sa Circuit elelctronique comprenant un mode de test securise par l'utilisation d'un identifiant, et procede associe
US7529993B1 (en) * 2006-06-08 2009-05-05 Xilinx, Inc. Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions
FR2903497A1 (fr) * 2006-07-07 2008-01-11 St Microelectronics Sa Circuit electronique comprenant un mode de test securise par insertion de donnees leurres dans la chaine de test,procede associe.
US20080028263A1 (en) * 2006-07-25 2008-01-31 Noemi Fernandez Apparatus and method for protection of JTAG scan chains in a microprocessor
US20080082879A1 (en) * 2006-09-29 2008-04-03 Amar Guettaf JTAG boundary scan compliant testing architecture with full and partial disable
US20090172420A1 (en) * 2007-12-31 2009-07-02 Kabushiki Kaisha Toshiba Tamper resistant method and apparatus for a storage device
US8214630B2 (en) * 2009-02-24 2012-07-03 General Instrument Corporation Method and apparatus for controlling enablement of JTAG interface
US8276199B2 (en) * 2009-04-09 2012-09-25 Freescale Semiconductor, Inc. Method and device for secure test port authentication
US20100263553A1 (en) * 2009-04-17 2010-10-21 Allen Nemeth Grilling Apparatus and Methods of Making and Using the Same
JP2010261768A (ja) * 2009-05-01 2010-11-18 Sony Corp 半導体集積回路、情報処理装置、および出力データ拡散方法、並びにプログラム
US8881301B2 (en) * 2009-10-05 2014-11-04 Asset Intertech, Inc. Protection of proprietary embedded instruments
FR2958063B1 (fr) * 2010-03-26 2012-04-20 Thales Sa Dispositif permettant de securiser un bus de type jtag
US8438436B1 (en) * 2010-06-04 2013-05-07 Xilinx, Inc. Secure design-for-test scan chains
US8495443B1 (en) 2011-05-31 2013-07-23 Apple Inc. Secure register scan bypass
US9224012B2 (en) * 2013-05-20 2015-12-29 Advanced Micro Devices, Inc. Debug functionality in a secure computing environment
KR102228454B1 (ko) 2014-02-24 2021-03-16 삼성전자주식회사 보안 디버깅 회로를 갖는 디바이스 및 그것에 대한 디버깅 방법
CN106556792B (zh) 2015-09-28 2021-03-19 恩智浦美国有限公司 能够进行安全扫描的集成电路
KR102538258B1 (ko) 2016-07-25 2023-05-31 삼성전자주식회사 데이터 저장 장치 및 이를 포함하는 데이터 처리 시스템
US10481205B2 (en) 2017-07-27 2019-11-19 Seagate Technology Llc Robust secure testing of integrated circuits
US11443071B2 (en) * 2020-02-13 2022-09-13 SiFive, Inc. Secure debug architecture

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Publication number Priority date Publication date Assignee Title
JP3856651B2 (ja) 2001-01-29 2006-12-13 松下電器産業株式会社 半導体装置
US6968420B1 (en) * 2002-02-13 2005-11-22 Lsi Logic Corporation Use of EEPROM for storage of security objects in secure systems
US7117352B1 (en) * 2002-02-13 2006-10-03 Lsi Logic Corporation Debug port disable mechanism
US7185249B2 (en) * 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
US7672452B2 (en) 2002-05-03 2010-03-02 General Instrument Corporation Secure scan
US7080789B2 (en) * 2003-05-09 2006-07-25 Stmicroelectronics, Inc. Smart card including a JTAG test controller and related methods
US20050066189A1 (en) 2003-09-18 2005-03-24 MOSS Robert Methods and structure for scan testing of secure systems
US7730545B2 (en) * 2005-05-23 2010-06-01 Arm Limited Test access control for secure integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104346583A (zh) * 2013-07-23 2015-02-11 阿尔特拉公司 用于保护可编程器件的配置扫描链的方法和装置

Also Published As

Publication number Publication date
WO2007041356A1 (en) 2007-04-12
US20070022341A1 (en) 2007-01-25
US20080148118A1 (en) 2008-06-19
US7634701B2 (en) 2009-12-15
TWI325534B (en) 2010-06-01
US7334173B2 (en) 2008-02-19

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