TW200731307A - Capacitor structure - Google Patents

Capacitor structure

Info

Publication number
TW200731307A
TW200731307A TW095104505A TW95104505A TW200731307A TW 200731307 A TW200731307 A TW 200731307A TW 095104505 A TW095104505 A TW 095104505A TW 95104505 A TW95104505 A TW 95104505A TW 200731307 A TW200731307 A TW 200731307A
Authority
TW
Taiwan
Prior art keywords
conductive
layers
adjacent
patterns
dielectric layer
Prior art date
Application number
TW095104505A
Other languages
Chinese (zh)
Other versions
TWI267882B (en
Inventor
Hung Cheng-Chou
Liang Victor-Chiang
Tseng Hua-Chou
Tseng Chih-Yu
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW95104505A priority Critical patent/TWI267882B/en
Application granted granted Critical
Publication of TWI267882B publication Critical patent/TWI267882B/en
Publication of TW200731307A publication Critical patent/TW200731307A/en

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

A capacitor structure including a plurality of conductive layers, a dielectric layer and a plurality of contacts is disclosed. The conductive layers are stacked, and each conductive layer has a first conductive pattern and a second conductive pattern. The dielectric layer is disposed between the first conductive pattern and the second conductive pattern and between two adjacent conductive layers. The contacts are disposed in the dielectric layer, and electrically connected to the first conductive patterns in two adjacent conductive layers and electrically connected to the second conductive patterns in two adjacent conductive layers. Wherein, the contact electrically connecting to the first conductive patterns in two adjacent conducive layers is a first strip contact, which extends between the first conductive patterns in two adjacent conductive layers, and the boundary of the first strip contact is located within the boundary of the first conductive pattern.
TW95104505A 2006-02-10 2006-02-10 Capacitor structure TWI267882B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95104505A TWI267882B (en) 2006-02-10 2006-02-10 Capacitor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95104505A TWI267882B (en) 2006-02-10 2006-02-10 Capacitor structure

Publications (2)

Publication Number Publication Date
TWI267882B TWI267882B (en) 2006-12-01
TW200731307A true TW200731307A (en) 2007-08-16

Family

ID=38220477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95104505A TWI267882B (en) 2006-02-10 2006-02-10 Capacitor structure

Country Status (1)

Country Link
TW (1) TWI267882B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11489039B2 (en) 2020-05-11 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11489039B2 (en) 2020-05-11 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
TWI803828B (en) * 2020-05-11 2023-06-01 台灣積體電路製造股份有限公司 Semiconductor device and manufacturing method thereof
US12009388B2 (en) 2020-05-11 2024-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
TWI267882B (en) 2006-12-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees