TW200731126A - System and method for memory array access with fast address decoder - Google Patents
System and method for memory array access with fast address decoderInfo
- Publication number
- TW200731126A TW200731126A TW095137550A TW95137550A TW200731126A TW 200731126 A TW200731126 A TW 200731126A TW 095137550 A TW095137550 A TW 095137550A TW 95137550 A TW95137550 A TW 95137550A TW 200731126 A TW200731126 A TW 200731126A
- Authority
- TW
- Taiwan
- Prior art keywords
- memory array
- pgzo
- address decoder
- array access
- fast address
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/257,932 US7669034B2 (en) | 2005-10-25 | 2005-10-25 | System and method for memory array access with fast address decoder |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200731126A true TW200731126A (en) | 2007-08-16 |
Family
ID=37968342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095137550A TW200731126A (en) | 2005-10-25 | 2006-10-12 | System and method for memory array access with fast address decoder |
Country Status (3)
Country | Link |
---|---|
US (2) | US7669034B2 (zh) |
TW (1) | TW200731126A (zh) |
WO (1) | WO2007050316A2 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8380779B2 (en) * | 2009-05-29 | 2013-02-19 | Freescale Semiconductor, Inc. | Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand |
AU2010280369A1 (en) * | 2009-08-02 | 2012-03-22 | Yael Ben Zvi | Phytoremediation for desalinated water post-processing |
US9542334B2 (en) | 2011-08-19 | 2017-01-10 | Nxp Usa, Inc. | Memory management unit TAG memory with CAM evaluate signal |
US9367475B2 (en) * | 2012-04-05 | 2016-06-14 | Freescale Semiconductor, Inc. | System and method for cache access |
US9367437B2 (en) | 2013-03-15 | 2016-06-14 | Freescale Semiconductor, Inc. | Method and apparatus for reducing the number of speculative accesses to a memory array |
US9323534B2 (en) | 2013-03-15 | 2016-04-26 | Freescale Semiconductor, Inc. | Method and apparatus for detecting a collision between multiple threads of execution for accessing a memory array |
US9116799B2 (en) | 2013-06-30 | 2015-08-25 | Freescale Semiconductor, Inc. | Method for detecting bank collision at a memory and device therefor |
US9563573B2 (en) * | 2013-08-20 | 2017-02-07 | Advanced Micro Devices, Inc. | Precharge disable using predecoded address |
US20170192780A1 (en) * | 2015-12-30 | 2017-07-06 | Robert Valentine | Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3265876A (en) * | 1962-12-24 | 1966-08-09 | Honeywell Inc | Parallel data accumulator for operating in either a binary or decimal mode |
US5754819A (en) * | 1994-07-28 | 1998-05-19 | Sun Microsystems, Inc. | Low-latency memory indexing method and structure |
US6813628B2 (en) * | 1999-12-23 | 2004-11-02 | Intel Corporation | Method and apparatus for performing equality comparison in redundant form arithmetic |
US6865590B2 (en) * | 2001-12-10 | 2005-03-08 | Infineon Technologies Ag | Three input variable subfield comparation for fast matching |
US6944088B2 (en) * | 2002-09-30 | 2005-09-13 | International Business Machines Corporation | Apparatus and method for generating memory access signals, and memory accessed using said signals |
US20050050278A1 (en) * | 2003-09-03 | 2005-03-03 | Advanced Micro Devices, Inc. | Low power way-predicted cache |
-
2005
- 2005-10-25 US US11/257,932 patent/US7669034B2/en active Active
-
2006
- 2006-10-11 WO PCT/US2006/040017 patent/WO2007050316A2/en active Application Filing
- 2006-10-12 TW TW095137550A patent/TW200731126A/zh unknown
- 2006-10-25 US US11/552,817 patent/US8943292B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20070094480A1 (en) | 2007-04-26 |
US7669034B2 (en) | 2010-02-23 |
US8943292B2 (en) | 2015-01-27 |
WO2007050316A3 (en) | 2009-04-23 |
US20070094479A1 (en) | 2007-04-26 |
WO2007050316A2 (en) | 2007-05-03 |
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