TW200725797A - Semiconductor device having capacitor and fabricating method thereof - Google Patents

Semiconductor device having capacitor and fabricating method thereof

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Publication number
TW200725797A
TW200725797A TW094145771A TW94145771A TW200725797A TW 200725797 A TW200725797 A TW 200725797A TW 094145771 A TW094145771 A TW 094145771A TW 94145771 A TW94145771 A TW 94145771A TW 200725797 A TW200725797 A TW 200725797A
Authority
TW
Taiwan
Prior art keywords
capacitor
dielectric layer
diffusion region
located over
mos
Prior art date
Application number
TW094145771A
Other languages
Chinese (zh)
Other versions
TWI263297B (en
Inventor
Jung-Ching Chen
Chin-Hung Liu
Chien-Ming Lin
Ming-Tsung Tung
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW94145771A priority Critical patent/TWI263297B/en
Application granted granted Critical
Publication of TWI263297B publication Critical patent/TWI263297B/en
Publication of TW200725797A publication Critical patent/TW200725797A/en

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  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device which has a capacitor is provided and includes a substrate, a metal oxide semiconductor (MOS) transistor and the capacitor. The MOS) transistor is disposed in a MOS transistor region with a first bottom diffusion region. The capacitor is disposed in a capacitor region, and it includes a second bottom diffusion region located in the substrate, a first dielectric layer located over the second bottom diffusion region, a bottom conductor layer located over the first dielectric layer, a second dielectric layer located over the bottom conductor layer, and a top conductor layer located over the second dielectric layer. The second bottom diffusion region and the first bottom diffusion region have different conductive type. The capacitor can get different capacitance according to the thickness of the dielectric layer, and the threshold voltage (Vt) of the MOS transistor can free from the influence of the voltage provided to the capacitor.
TW94145771A 2005-12-22 2005-12-22 Semiconductor device having capacitor and fabricating method thereof TWI263297B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94145771A TWI263297B (en) 2005-12-22 2005-12-22 Semiconductor device having capacitor and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94145771A TWI263297B (en) 2005-12-22 2005-12-22 Semiconductor device having capacitor and fabricating method thereof

Publications (2)

Publication Number Publication Date
TWI263297B TWI263297B (en) 2006-10-01
TW200725797A true TW200725797A (en) 2007-07-01

Family

ID=37966323

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94145771A TWI263297B (en) 2005-12-22 2005-12-22 Semiconductor device having capacitor and fabricating method thereof

Country Status (1)

Country Link
TW (1) TWI263297B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI399833B (en) * 2009-12-29 2013-06-21 Taiwan Memory Company A method of fabricating a memory capacitor

Also Published As

Publication number Publication date
TWI263297B (en) 2006-10-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees