TW200713458A - Method for forming a capping layer on a semiconductor device - Google Patents
Method for forming a capping layer on a semiconductor deviceInfo
- Publication number
- TW200713458A TW200713458A TW095129934A TW95129934A TW200713458A TW 200713458 A TW200713458 A TW 200713458A TW 095129934 A TW095129934 A TW 095129934A TW 95129934 A TW95129934 A TW 95129934A TW 200713458 A TW200713458 A TW 200713458A
- Authority
- TW
- Taiwan
- Prior art keywords
- cavities
- forming
- semiconductor device
- diffusion barrier
- patterned dielectric
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000004888 barrier function Effects 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/215,375 US20070049008A1 (en) | 2005-08-26 | 2005-08-26 | Method for forming a capping layer on a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200713458A true TW200713458A (en) | 2007-04-01 |
Family
ID=37772126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095129934A TW200713458A (en) | 2005-08-26 | 2006-08-15 | Method for forming a capping layer on a semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US20070049008A1 (zh) |
JP (1) | JP2009506536A (zh) |
KR (1) | KR20080047541A (zh) |
TW (1) | TW200713458A (zh) |
WO (1) | WO2007024470A2 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4755545B2 (ja) * | 2006-07-11 | 2011-08-24 | 新光電気工業株式会社 | 基板の製造方法 |
KR102306796B1 (ko) | 2011-11-04 | 2021-09-30 | 인텔 코포레이션 | 자기 정렬 캡의 형성 방법 및 장치 |
KR102274848B1 (ko) * | 2014-10-17 | 2021-07-12 | 에이씨엠 리서치 (상하이) 인코포레이티드 | 배리어층 제거 방법 및 반도체 구조체 형성 방법 |
US10741748B2 (en) * | 2018-06-25 | 2020-08-11 | International Business Machines Corporation | Back end of line metallization structures |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW571005B (en) * | 2000-06-29 | 2004-01-11 | Ebara Corp | Method and apparatus for forming copper interconnects, and polishing liquid and polishing method |
US6528409B1 (en) * | 2002-04-29 | 2003-03-04 | Advanced Micro Devices, Inc. | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration |
US20030227091A1 (en) * | 2002-06-06 | 2003-12-11 | Nishant Sinha | Plating metal caps on conductive interconnect for wirebonding |
US7241696B2 (en) * | 2002-12-11 | 2007-07-10 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer |
US6893959B2 (en) * | 2003-05-05 | 2005-05-17 | Infineon Technologies Ag | Method to form selective cap layers on metal features with narrow spaces |
US20050048768A1 (en) * | 2003-08-26 | 2005-03-03 | Hiroaki Inoue | Apparatus and method for forming interconnects |
US6924232B2 (en) * | 2003-08-27 | 2005-08-02 | Freescale Semiconductor, Inc. | Semiconductor process and composition for forming a barrier material overlying copper |
US20050161338A1 (en) * | 2004-01-26 | 2005-07-28 | Applied Materials, Inc. | Electroless cobalt alloy deposition process |
-
2005
- 2005-08-26 US US11/215,375 patent/US20070049008A1/en not_active Abandoned
-
2006
- 2006-08-08 WO PCT/US2006/030823 patent/WO2007024470A2/en active Application Filing
- 2006-08-08 JP JP2008527951A patent/JP2009506536A/ja active Pending
- 2006-08-08 KR KR1020087004490A patent/KR20080047541A/ko not_active Application Discontinuation
- 2006-08-15 TW TW095129934A patent/TW200713458A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
WO2007024470A3 (en) | 2007-09-27 |
JP2009506536A (ja) | 2009-02-12 |
WO2007024470A2 (en) | 2007-03-01 |
US20070049008A1 (en) | 2007-03-01 |
KR20080047541A (ko) | 2008-05-29 |
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