TW200709338A - Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same - Google Patents

Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same

Info

Publication number
TW200709338A
TW200709338A TW095115593A TW95115593A TW200709338A TW 200709338 A TW200709338 A TW 200709338A TW 095115593 A TW095115593 A TW 095115593A TW 95115593 A TW95115593 A TW 95115593A TW 200709338 A TW200709338 A TW 200709338A
Authority
TW
Taiwan
Prior art keywords
via structures
methods
structures
backside
depths
Prior art date
Application number
TW095115593A
Other languages
English (en)
Inventor
Hooman Kazemi
Original Assignee
Rockwell Scient Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell Scient Licensing Llc filed Critical Rockwell Scient Licensing Llc
Publication of TW200709338A publication Critical patent/TW200709338A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
TW095115593A 2005-05-03 2006-05-02 Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same TW200709338A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/121,504 US20060252262A1 (en) 2005-05-03 2005-05-03 Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same

Publications (1)

Publication Number Publication Date
TW200709338A true TW200709338A (en) 2007-03-01

Family

ID=36791797

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095115593A TW200709338A (en) 2005-05-03 2006-05-02 Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same

Country Status (3)

Country Link
US (1) US20060252262A1 (zh)
TW (1) TW200709338A (zh)
WO (1) WO2006119023A1 (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
JP4170313B2 (ja) * 2005-05-24 2008-10-22 シャープ株式会社 半導体装置の製造方法
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7560813B2 (en) 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7354799B2 (en) * 2005-11-08 2008-04-08 Intel Corporation Methods for anchoring a seal ring to a substrate using vias and assemblies including an anchored seal ring
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
KR101259535B1 (ko) * 2006-09-27 2013-05-06 타이코에이엠피(유) 커넥터
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
SG152086A1 (en) * 2007-10-23 2009-05-29 Micron Technology Inc Packaged semiconductor assemblies and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8242593B2 (en) * 2008-01-27 2012-08-14 International Business Machines Corporation Clustered stacked vias for reliable electronic substrates
US20090321861A1 (en) * 2008-06-26 2009-12-31 Micron Technology, Inc. Microelectronic imagers with stacked lens assemblies and processes for wafer-level packaging of microelectronic imagers
US7935571B2 (en) * 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8344503B2 (en) 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
JP5619542B2 (ja) * 2010-09-08 2014-11-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体基板の処理方法及び半導体装置の製造方法
US20120083129A1 (en) 2010-10-05 2012-04-05 Skyworks Solutions, Inc. Apparatus and methods for focusing plasma
US9478428B2 (en) 2010-10-05 2016-10-25 Skyworks Solutions, Inc. Apparatus and methods for shielding a plasma etcher electrode
CN103165566B (zh) 2011-12-19 2016-02-24 先进封装技术私人有限公司 基板结构、半导体封装件及半导体封装件的制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4008273A (en) * 1971-06-01 1977-02-15 Pennwalt Corporation Tertiary alkyl semicarbazides and their method of preparation
US4808273A (en) * 1988-05-10 1989-02-28 Avantek, Inc. Method of forming completely metallized via holes in semiconductors
US5166097A (en) * 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
JP4364358B2 (ja) * 1999-10-12 2009-11-18 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP4098673B2 (ja) * 2003-06-19 2008-06-11 新光電気工業株式会社 半導体パッケージの製造方法
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias

Also Published As

Publication number Publication date
WO2006119023A1 (en) 2006-11-09
US20060252262A1 (en) 2006-11-09

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