TW200709043A - Method for performing subroutine return operation and processor-readable storage medium - Google Patents

Method for performing subroutine return operation and processor-readable storage medium

Info

Publication number
TW200709043A
TW200709043A TW095120621A TW95120621A TW200709043A TW 200709043 A TW200709043 A TW 200709043A TW 095120621 A TW095120621 A TW 095120621A TW 95120621 A TW95120621 A TW 95120621A TW 200709043 A TW200709043 A TW 200709043A
Authority
TW
Taiwan
Prior art keywords
processor
storage medium
readable storage
return operation
subroutine return
Prior art date
Application number
TW095120621A
Other languages
English (en)
Inventor
Erik K Renno
Oyvind Strom
Morten W Lund
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of TW200709043A publication Critical patent/TW200709043A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
  • Microcomputers (AREA)
TW095120621A 2005-06-10 2006-06-09 Method for performing subroutine return operation and processor-readable storage medium TW200709043A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/149,611 US20060282821A1 (en) 2005-06-10 2005-06-10 Efficient subprogram return in microprocessors

Publications (1)

Publication Number Publication Date
TW200709043A true TW200709043A (en) 2007-03-01

Family

ID=37525517

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095120621A TW200709043A (en) 2005-06-10 2006-06-09 Method for performing subroutine return operation and processor-readable storage medium

Country Status (7)

Country Link
US (2) US20060282821A1 (zh)
EP (1) EP1891519B1 (zh)
JP (1) JP2009508180A (zh)
KR (1) KR20080014062A (zh)
CN (1) CN101194228B (zh)
TW (1) TW200709043A (zh)
WO (1) WO2006135549A2 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060282821A1 (en) * 2005-06-10 2006-12-14 Renno Erik K Efficient subprogram return in microprocessors
CN100442226C (zh) * 2007-07-02 2008-12-10 美的集团有限公司 微波炉返回键的设定方法
US10802990B2 (en) * 2008-10-06 2020-10-13 International Business Machines Corporation Hardware based mandatory access control
CN101551749B (zh) * 2009-05-11 2012-08-22 中国科学院计算技术研究所 随机测试程序生成方法和系统以及设计验证方法
WO2012103253A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Multilevel conversion table cache for translating guest instructions to native instructions
WO2012103367A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Guest to native block address mappings and management of native code storage
WO2012103359A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Hardware acceleration components for translating guest instructions to native instructions
EP2972798B1 (en) 2013-03-15 2020-06-17 Intel Corporation Method and apparatus for guest return address stack emulation supporting speculation
WO2014151652A1 (en) 2013-03-15 2014-09-25 Soft Machines Inc Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor

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US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
US4926355A (en) * 1987-07-02 1990-05-15 General Datacomm, Inc. Digital signal processor architecture with an ALU and a serial processing section operating in parallel
US4891754A (en) * 1987-07-02 1990-01-02 General Datacomm Inc. Microinstruction sequencer for instructing arithmetic, logical and data move operations in a conditional manner
US5193205A (en) * 1988-03-01 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
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JP3499252B2 (ja) * 1993-03-19 2004-02-23 株式会社ルネサステクノロジ コンパイル装置及びデータ処理装置
US5925125A (en) * 1993-06-24 1999-07-20 International Business Machines Corporation Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions
GB2281986B (en) * 1993-09-15 1997-08-06 Advanced Risc Mach Ltd Data processing reset
JP3543181B2 (ja) * 1994-11-09 2004-07-14 株式会社ルネサステクノロジ データ処理装置
US5701493A (en) * 1995-08-03 1997-12-23 Advanced Risc Machines Limited Exception handling method and apparatus in data processing systems
JP3720371B2 (ja) * 1995-10-06 2005-11-24 アドバンスト・マイクロ・デバイシズ・インコーポレイテッド スーパースケーラープロセッサにおけるｏｕｔ−ｏｆ−ｏｒｄｅｒ実行のための統一化された機能オペレーションスケジューラ
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5778208A (en) * 1995-12-18 1998-07-07 International Business Machines Corporation Flexible pipeline for interlock removal
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US20060282821A1 (en) * 2005-06-10 2006-12-14 Renno Erik K Efficient subprogram return in microprocessors

Also Published As

Publication number Publication date
US20060282821A1 (en) 2006-12-14
WO2006135549A2 (en) 2006-12-21
EP1891519A4 (en) 2010-05-19
CN101194228B (zh) 2011-10-19
JP2009508180A (ja) 2009-02-26
US8555041B2 (en) 2013-10-08
WO2006135549A3 (en) 2007-08-16
EP1891519A2 (en) 2008-02-27
KR20080014062A (ko) 2008-02-13
CN101194228A (zh) 2008-06-04
US20100250904A1 (en) 2010-09-30
WO2006135549A8 (en) 2008-01-10
EP1891519B1 (en) 2016-12-07

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