TW200707726A - Semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween - Google Patents
Semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetweenInfo
- Publication number
- TW200707726A TW200707726A TW095122066A TW95122066A TW200707726A TW 200707726 A TW200707726 A TW 200707726A TW 095122066 A TW095122066 A TW 095122066A TW 95122066 A TW95122066 A TW 95122066A TW 200707726 A TW200707726 A TW 200707726A
- Authority
- TW
- Taiwan
- Prior art keywords
- regions
- sti
- semiconductor device
- superlattice
- trench isolation
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69210105P | 2005-06-20 | 2005-06-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200707726A true TW200707726A (en) | 2007-02-16 |
TWI311374B TWI311374B (en) | 2009-06-21 |
Family
ID=37192316
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW95122066A TWI311374B (en) | 2005-06-20 | 2006-06-20 | Semiconductor device including shallow trench isolation (sti) regions with a superlattice therebetween |
TW95122068A TWI308376B (en) | 2005-06-20 | 2006-06-20 | Method for making a semiconductor device including shallow trench isolation (sti) regions with a superlattice therebetween |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW95122068A TWI308376B (en) | 2005-06-20 | 2006-06-20 | Method for making a semiconductor device including shallow trench isolation (sti) regions with a superlattice therebetween |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1900021A1 (en) |
JP (1) | JP2009529780A (en) |
CN (1) | CN101371349B (en) |
AU (1) | AU2006262416A1 (en) |
CA (1) | CA2612213A1 (en) |
TW (2) | TWI311374B (en) |
WO (1) | WO2007002043A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9899479B2 (en) | 2015-05-15 | 2018-02-20 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7943450B2 (en) | 2007-09-04 | 2011-05-17 | Texas Instruments Incorporated | Gated resonant tunneling diode |
US7910918B2 (en) | 2007-09-04 | 2011-03-22 | Texas Instruments Incorporated | Gated resonant tunneling diode |
CN111247640B (en) * | 2017-08-18 | 2023-11-03 | 阿托梅拉公司 | Semiconductor device and method including non-single crystal stringers adjacent to superlattice STI interfaces |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174522A (en) * | 1996-12-19 | 1999-03-16 | Texas Instr Inc <Ti> | Method and device for forming planar field effect transistor with source and drain on insulator |
CN1395316A (en) * | 2001-07-04 | 2003-02-05 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
US6703271B2 (en) * | 2001-11-30 | 2004-03-09 | Taiwan Semiconductor Manufacturing Company | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer |
US6583000B1 (en) * | 2002-02-07 | 2003-06-24 | Sharp Laboratories Of America, Inc. | Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation |
JP4750342B2 (en) * | 2002-07-03 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | MOS-FET, manufacturing method thereof, and semiconductor device |
JP2004047844A (en) * | 2002-07-15 | 2004-02-12 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
US6846720B2 (en) * | 2003-06-18 | 2005-01-25 | Agency For Science, Technology And Research | Method to reduce junction leakage current in strained silicon on silicon-germanium devices |
WO2005018005A1 (en) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Semiconductor device including mosfet having band-engineered superlattice |
US6958486B2 (en) * | 2003-06-26 | 2005-10-25 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
US20050167777A1 (en) * | 2004-01-30 | 2005-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Microelectronic device with active layer bumper |
-
2006
- 2006-06-20 CN CN2006800220664A patent/CN101371349B/en not_active Expired - Fee Related
- 2006-06-20 JP JP2008517222A patent/JP2009529780A/en active Pending
- 2006-06-20 AU AU2006262416A patent/AU2006262416A1/en not_active Abandoned
- 2006-06-20 EP EP06785154A patent/EP1900021A1/en not_active Withdrawn
- 2006-06-20 WO PCT/US2006/023918 patent/WO2007002043A1/en active Application Filing
- 2006-06-20 TW TW95122066A patent/TWI311374B/en active
- 2006-06-20 CA CA002612213A patent/CA2612213A1/en not_active Abandoned
- 2006-06-20 TW TW95122068A patent/TWI308376B/en active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9899479B2 (en) | 2015-05-15 | 2018-02-20 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
TWI621264B (en) * | 2015-05-15 | 2018-04-11 | 安托梅拉公司 | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
Also Published As
Publication number | Publication date |
---|---|
JP2009529780A (en) | 2009-08-20 |
WO2007002043A9 (en) | 2007-05-24 |
EP1900021A1 (en) | 2008-03-19 |
TWI308376B (en) | 2009-04-01 |
TW200717701A (en) | 2007-05-01 |
CA2612213A1 (en) | 2007-01-04 |
AU2006262416A1 (en) | 2007-01-04 |
WO2007002043A1 (en) | 2007-01-04 |
CN101371349B (en) | 2011-04-13 |
TWI311374B (en) | 2009-06-21 |
CN101371349A (en) | 2009-02-18 |
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