TW200705630A - Electrical connection structure of semiconductor chip in carrier board and method for fabricating the same - Google Patents

Electrical connection structure of semiconductor chip in carrier board and method for fabricating the same

Info

Publication number
TW200705630A
TW200705630A TW094124648A TW94124648A TW200705630A TW 200705630 A TW200705630 A TW 200705630A TW 094124648 A TW094124648 A TW 094124648A TW 94124648 A TW94124648 A TW 94124648A TW 200705630 A TW200705630 A TW 200705630A
Authority
TW
Taiwan
Prior art keywords
semiconductor chip
carrier board
fabricating
electrical connection
connection structure
Prior art date
Application number
TW094124648A
Other languages
Chinese (zh)
Other versions
TWI309464B (en
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW094124648A priority Critical patent/TWI309464B/en
Publication of TW200705630A publication Critical patent/TW200705630A/en
Application granted granted Critical
Publication of TWI309464B publication Critical patent/TWI309464B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An electrical connection structure of a semiconductor chip in a carrier board and a method for fabricating the same are proposed. The carrier board has at least one through opening, and at least one semiconductor chip with an active surface and an inactive surface is disposed in the opening. The active surface has electrically connecting pads thereon. A dielectric layer is formed on the carrier board and the active surface of the semiconductor chip and has a plurality of openings for exposing the electrically connecting pads of the semiconductor chip. A plurality of metal pads are formed on the surface of the dielectric layer that does not have the semiconductor chip disposed thereon, and are electrically connected to the electrically connecting pads of the semiconductor chip. Thus, it meets the requirement of a fin circuit, reduces difficulty in registration and raises yield by disposing the metal connecting pads.
TW094124648A 2005-07-21 2005-07-21 Electrical connection structure of semiconductor chip in carrier board and method for fabricating the same TWI309464B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094124648A TWI309464B (en) 2005-07-21 2005-07-21 Electrical connection structure of semiconductor chip in carrier board and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094124648A TWI309464B (en) 2005-07-21 2005-07-21 Electrical connection structure of semiconductor chip in carrier board and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200705630A true TW200705630A (en) 2007-02-01
TWI309464B TWI309464B (en) 2009-05-01

Family

ID=45072048

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094124648A TWI309464B (en) 2005-07-21 2005-07-21 Electrical connection structure of semiconductor chip in carrier board and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI309464B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426589B (en) * 2007-10-31 2014-02-11 Alpha & Omega Semiconductor A solder-top enhanced semiconductor device and method for low parasitic impedance packaging
TWI447972B (en) * 2010-12-28 2014-08-01 Biao Qin LED chip and LED chip and chip manufacturing methods

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI441292B (en) 2011-03-02 2014-06-11 矽品精密工業股份有限公司 Semiconductor structure and fabrication method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426589B (en) * 2007-10-31 2014-02-11 Alpha & Omega Semiconductor A solder-top enhanced semiconductor device and method for low parasitic impedance packaging
TWI447972B (en) * 2010-12-28 2014-08-01 Biao Qin LED chip and LED chip and chip manufacturing methods

Also Published As

Publication number Publication date
TWI309464B (en) 2009-05-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees