TW200641996A - Method for fabricating right-angle holes in a substrate - Google Patents

Method for fabricating right-angle holes in a substrate

Info

Publication number
TW200641996A
TW200641996A TW095105996A TW95105996A TW200641996A TW 200641996 A TW200641996 A TW 200641996A TW 095105996 A TW095105996 A TW 095105996A TW 95105996 A TW95105996 A TW 95105996A TW 200641996 A TW200641996 A TW 200641996A
Authority
TW
Taiwan
Prior art keywords
dielectric layer
contact
substrate
dimension
via hole
Prior art date
Application number
TW095105996A
Other languages
English (en)
Other versions
TWI267919B (en
Inventor
Cheng-Yao Lo
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Application granted granted Critical
Publication of TW200641996A publication Critical patent/TW200641996A/zh
Publication of TWI267919B publication Critical patent/TWI267919B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
TW095105996A 2005-05-31 2006-02-22 Method for fabricating right-angle holes in a substrate TWI267919B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/141,791 US7381654B2 (en) 2005-05-31 2005-05-31 Method for fabricating right-angle holes in a substrate

Publications (2)

Publication Number Publication Date
TW200641996A true TW200641996A (en) 2006-12-01
TWI267919B TWI267919B (en) 2006-12-01

Family

ID=37463939

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095105996A TWI267919B (en) 2005-05-31 2006-02-22 Method for fabricating right-angle holes in a substrate

Country Status (2)

Country Link
US (1) US7381654B2 (zh)
TW (1) TWI267919B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US10658184B2 (en) * 2016-12-15 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Pattern fidelity enhancement with directional patterning technology
US11171052B2 (en) 2019-04-29 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby
US11024533B2 (en) * 2019-05-16 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures using via holes filled with dielectric film

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242770A (en) 1992-01-16 1993-09-07 Microunity Systems Engineering, Inc. Mask for photolithography
US5466639A (en) 1994-10-06 1995-11-14 Micron Semiconductor, Inc. Double mask process for forming trenches and contacts during the formation of a semiconductor memory device
JP3146962B2 (ja) * 1995-12-14 2001-03-19 日本電気株式会社 半導体記憶装置およびその製造方法
KR0172794B1 (ko) * 1995-12-29 1999-03-30 김주용 반도체 소자의 미세패턴 형성방법
US5888897A (en) * 1996-10-31 1999-03-30 Intel Corporation Process for forming an integrated structure comprising a self-aligned via/contact and interconnect
US6562544B1 (en) * 1996-11-04 2003-05-13 Applied Materials, Inc. Method and apparatus for improving accuracy in photolithographic processing of substrates
JPH10289861A (ja) 1997-04-16 1998-10-27 Nikon Corp マスクパターン形成方法
US6190989B1 (en) * 1998-07-15 2001-02-20 Micron Technology, Inc. Method for patterning cavities and enhanced cavity shapes for semiconductor devices
US6514648B2 (en) 1998-08-28 2003-02-04 International Business Machines Corporation Method to produce equal sized features in microlithography
US6120952A (en) 1998-10-01 2000-09-19 Micron Technology, Inc. Methods of reducing proximity effects in lithographic processes
US6303272B1 (en) 1998-11-13 2001-10-16 International Business Machines Corporation Process for self-alignment of sub-critical contacts to wiring
US6121155A (en) * 1998-12-04 2000-09-19 Advanced Micro Devices Integrated circuit fabrication critical dimension control using self-limiting resist etch
US6204187B1 (en) 1999-01-06 2001-03-20 Infineon Technologies North America, Corp. Contact and deep trench patterning
US6306558B1 (en) 1999-04-29 2001-10-23 Taiwan Semiconductor Manufacturing Company Method of forming small contact holes using alternative phase shift masks and negative photoresist
US6410453B1 (en) 1999-09-02 2002-06-25 Micron Technology, Inc. Method of processing a substrate
US6586142B1 (en) 1999-09-30 2003-07-01 Taiwan Semiconductor Manufacturing Company Method to overcome image distortion of lines and contact holes in optical lithography
US6194104B1 (en) 1999-10-12 2001-02-27 Taiwan Semiconductor Manufacturing Company Optical proximity correction (OPC) method for improving lithography process window
US6428936B1 (en) 1999-12-16 2002-08-06 Intel Corporation Method and apparatus that compensates for phase shift mask manufacturing defects
US6350390B1 (en) * 2000-02-22 2002-02-26 Taiwan Semiconductor Manufacturing Company, Ltd Plasma etch method for forming patterned layer with enhanced critical dimension (CD) control
US6423455B1 (en) 2000-06-01 2002-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a multiple masking layer photomask
TW526395B (en) * 2000-09-29 2003-04-01 United Microelectronics Corp Method to improve side profile of photoresist pattern
US6599665B1 (en) 2000-10-10 2003-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a semiconductor wafer imaging mask having uniform pattern features
US6578190B2 (en) 2001-01-11 2003-06-10 International Business Machines Corporation Process window based optical proximity correction of lithographic images
US6537708B2 (en) 2001-01-31 2003-03-25 Photronics, Inc. Electrical critical dimension measurements on photomasks
US6764795B2 (en) 2001-08-27 2004-07-20 Texas Instruments Incorporated Method and system for mask pattern correction
US6824931B2 (en) 2001-08-29 2004-11-30 Taiwan Semiconductor Manufacturing Co., Ltd Verification photomask
US6686129B2 (en) 2001-10-11 2004-02-03 Taiwan Semiconductor Manufacturing Co. Ltd. Partial photoresist etching
DE10154820B4 (de) 2001-11-08 2005-06-02 Infineon Technologies Ag Verfahren zum Herstellen einer Maske für Halbleiterstrukturen
US6489237B1 (en) 2001-12-04 2002-12-03 Taiwan Semiconductor Manufacturing Company Method of patterning lines in semiconductor devices
US6664011B2 (en) 2001-12-05 2003-12-16 Taiwan Semiconductor Manufacturing Company Hole printing by packing and unpacking using alternating phase-shifting masks
JP3953982B2 (ja) * 2002-06-28 2007-08-08 富士通株式会社 半導体装置の製造方法及びパターンの形成方法
US6649469B1 (en) * 2002-10-11 2003-11-18 Micron Technology, Inc. Methods of forming capacitors
TWI235282B (en) 2003-07-03 2005-07-01 Nanya Technology Corp Method of correcting optical proximity effect of contact hole
US20050136335A1 (en) * 2003-12-17 2005-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Patterned microelectronic mask layer formation method employing multiple feed-forward linewidth measurement

Also Published As

Publication number Publication date
US20060270068A1 (en) 2006-11-30
TWI267919B (en) 2006-12-01
US7381654B2 (en) 2008-06-03

Similar Documents

Publication Publication Date Title
TW200735188A (en) Method for forming storage node contact plug in semiconductor device
TW200509403A (en) Semiconductor device including a capacitor having improved structural stability and enhanced capacitance, and method of manufacturing the semiconductor device
TW200623474A (en) Method for manufacturing a small pin on integrated circuits or other devices
EP1391924A4 (en) SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE, CIRCUIT BOARD, AND ELECTRICAL APPARATUS
TW200501216A (en) Organic semiconductor device and method of manufacture of same
TW200633000A (en) Method for forming dual damascene structure with tapered via portion and improved performance
TW200723474A (en) High thermal conducting circuit substrate and manufacturing process thereof
WO2007068714A3 (en) Method of making a contact in a semiconductor device
WO2005050700A3 (en) Line edge roughness reduction for trench etch
TW200634983A (en) Method of forming a plug
TW200623338A (en) Method for fabricating capacitor of semiconductor device
TW200517752A (en) Manufacturing method of liquid crystal display (LCD)
TW200515478A (en) Method for fabricating semiconductor device with fine patterns
TW200501262A (en) Method of fabricating gate structures having a high-k gate dielectric layer
SG155041A1 (en) Method of forming contact plug on silicide structure
TW200703524A (en) Method for fabricating conductive line
TW200641996A (en) Method for fabricating right-angle holes in a substrate
TW200606998A (en) Method of making dual damascene with via etch through
JP2007173816A5 (zh)
TW200701396A (en) Method for forming contact hole in semiconductor device
TW200727293A (en) Method for manufacturing a semiconductor device, method for manufacturing magnetic random access memory and device thereof
TW200511587A (en) Semiconductor device, method for manufacturing the semiconductor device, and integrated circuit including the semiconductor device
WO2004003980A3 (en) Interconnect structure and method for forming
TW200507173A (en) Method for manufacturing semiconductor device
EP1530233A3 (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees