TW200634951A - Multi-bump semiconductor carrier structure and its production method - Google Patents

Multi-bump semiconductor carrier structure and its production method

Info

Publication number
TW200634951A
TW200634951A TW094109761A TW94109761A TW200634951A TW 200634951 A TW200634951 A TW 200634951A TW 094109761 A TW094109761 A TW 094109761A TW 94109761 A TW94109761 A TW 94109761A TW 200634951 A TW200634951 A TW 200634951A
Authority
TW
Taiwan
Prior art keywords
bump
partition
production method
carrier structure
semiconductor carrier
Prior art date
Application number
TW094109761A
Other languages
Chinese (zh)
Other versions
TWI258828B (en
Inventor
wen-feng Zheng
Yi-Jr Lin
Bo Sun
Huen-Ren Wang
Original Assignee
Boardtek Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boardtek Electronics Corp filed Critical Boardtek Electronics Corp
Priority to TW94109761A priority Critical patent/TWI258828B/en
Application granted granted Critical
Publication of TWI258828B publication Critical patent/TWI258828B/en
Publication of TW200634951A publication Critical patent/TW200634951A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

This invention provides a multi-bump semiconductor carrier structure and its production method, in which multiple etching/deep-control forming is utilized on a metal plate containing a 1st surface and a 2nd surface to form a plurality of notches on the 1st surface and form a plurality of bump arrangements on the 2nd surface, and install a partition within the metal plate and adjacent to the bumps. The partition is exposed within each notch, such that by means of different partition material, every bump has conductivity/non-conductivity. Thus, the present invention has characteristics of the pre-formed conductive bump and excellent thermal dissipation, and utilizes preparation of the partition and the supporting structure such that the layout of chip becomes more diversified; and the pre-formed conductive bump can reduce the production costs and the number of steps.
TW94109761A 2005-03-29 2005-03-29 Multi-bump semiconductor carrier structure and its production method TWI258828B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94109761A TWI258828B (en) 2005-03-29 2005-03-29 Multi-bump semiconductor carrier structure and its production method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94109761A TWI258828B (en) 2005-03-29 2005-03-29 Multi-bump semiconductor carrier structure and its production method

Publications (2)

Publication Number Publication Date
TWI258828B TWI258828B (en) 2006-07-21
TW200634951A true TW200634951A (en) 2006-10-01

Family

ID=37765411

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94109761A TWI258828B (en) 2005-03-29 2005-03-29 Multi-bump semiconductor carrier structure and its production method

Country Status (1)

Country Link
TW (1) TWI258828B (en)

Also Published As

Publication number Publication date
TWI258828B (en) 2006-07-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees