TW200625518A - Fabrication of semiconductor integrated circuit chips - Google Patents

Fabrication of semiconductor integrated circuit chips

Info

Publication number
TW200625518A
TW200625518A TW094100617A TW94100617A TW200625518A TW 200625518 A TW200625518 A TW 200625518A TW 094100617 A TW094100617 A TW 094100617A TW 94100617 A TW94100617 A TW 94100617A TW 200625518 A TW200625518 A TW 200625518A
Authority
TW
Taiwan
Prior art keywords
active circuit
circuit die
overcoat
line region
fabrication
Prior art date
Application number
TW094100617A
Other languages
Chinese (zh)
Other versions
TWI255006B (en
Inventor
Zong-Huei Lin
Hung-Min Liu
Jui-Meng Jao
Wen-Tung Chang
Kuo-Ming Chen
Kai Kuang Ho
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW94100617A priority Critical patent/TWI255006B/en
Application granted granted Critical
Publication of TWI255006B publication Critical patent/TWI255006B/en
Publication of TW200625518A publication Critical patent/TW200625518A/en

Links

Landscapes

  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.
TW94100617A 2005-01-10 2005-01-10 Fabrication of semiconductor integrated circuit chips TWI255006B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94100617A TWI255006B (en) 2005-01-10 2005-01-10 Fabrication of semiconductor integrated circuit chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94100617A TWI255006B (en) 2005-01-10 2005-01-10 Fabrication of semiconductor integrated circuit chips

Publications (2)

Publication Number Publication Date
TWI255006B TWI255006B (en) 2006-05-11
TW200625518A true TW200625518A (en) 2006-07-16

Family

ID=37607574

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94100617A TWI255006B (en) 2005-01-10 2005-01-10 Fabrication of semiconductor integrated circuit chips

Country Status (1)

Country Link
TW (1) TWI255006B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162072A (en) * 2018-11-07 2020-05-15 南亚科技股份有限公司 Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162072A (en) * 2018-11-07 2020-05-15 南亚科技股份有限公司 Semiconductor device and method for manufacturing the same
TWI701716B (en) * 2018-11-07 2020-08-11 南亞科技股份有限公司 Semiconductor device and the method of manufacturing the same

Also Published As

Publication number Publication date
TWI255006B (en) 2006-05-11

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