TW200623325A - Methods for forming dual damascene wiring using porogen containing sacrificial via filler material - Google Patents

Methods for forming dual damascene wiring using porogen containing sacrificial via filler material

Info

Publication number
TW200623325A
TW200623325A TW094143335A TW94143335A TW200623325A TW 200623325 A TW200623325 A TW 200623325A TW 094143335 A TW094143335 A TW 094143335A TW 94143335 A TW94143335 A TW 94143335A TW 200623325 A TW200623325 A TW 200623325A
Authority
TW
Taiwan
Prior art keywords
methods
dual damascene
filler material
damascene wiring
forming dual
Prior art date
Application number
TW094143335A
Other languages
Chinese (zh)
Other versions
TWI278064B (en
Inventor
Kyoung-Woo Lee
Hong-Jae Shin
Jae-Hak Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040103088A external-priority patent/KR100745986B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200623325A publication Critical patent/TW200623325A/en
Application granted granted Critical
Publication of TWI278064B publication Critical patent/TWI278064B/en

Links

Abstract

Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer dielectric layer such that the sacrificial material can be transformed to porous material that can be quickly and efficiently removed from the via holes without damaging or removing the interlayer dielectric layer.
TW94143335A 2004-12-08 2005-12-08 Methods for forming dual damascene wiring using porogen containing sacrificial via filler material TWI278064B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040103088A KR100745986B1 (en) 2004-12-08 2004-12-08 Fabrication method of dual damascene interconnections of microelectronics device using filler having porogen
US11/223,310 US20060121721A1 (en) 2004-12-08 2005-09-09 Methods for forming dual damascene wiring using porogen containing sacrificial via filler material

Publications (2)

Publication Number Publication Date
TW200623325A true TW200623325A (en) 2006-07-01
TWI278064B TWI278064B (en) 2007-04-01

Family

ID=38626104

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94143335A TWI278064B (en) 2004-12-08 2005-12-08 Methods for forming dual damascene wiring using porogen containing sacrificial via filler material

Country Status (1)

Country Link
TW (1) TWI278064B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI767096B (en) * 2017-12-13 2022-06-11 日商東京威力科創股份有限公司 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI767096B (en) * 2017-12-13 2022-06-11 日商東京威力科創股份有限公司 Method for manufacturing semiconductor device
US11495490B2 (en) 2017-12-13 2022-11-08 Tokyo Electron Limited Semiconductor device manufacturing method

Also Published As

Publication number Publication date
TWI278064B (en) 2007-04-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees