TW200614481A - Wafer level process for manufacturing leadframe and device from the same - Google Patents
Wafer level process for manufacturing leadframe and device from the sameInfo
- Publication number
- TW200614481A TW200614481A TW093131686A TW93131686A TW200614481A TW 200614481 A TW200614481 A TW 200614481A TW 093131686 A TW093131686 A TW 093131686A TW 93131686 A TW93131686 A TW 93131686A TW 200614481 A TW200614481 A TW 200614481A
- Authority
- TW
- Taiwan
- Prior art keywords
- lead portions
- wafer
- level process
- mask
- leadframe
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title abstract 2
- 239000008393 encapsulating agent Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093131686A TWI250633B (en) | 2004-10-19 | 2004-10-19 | Wafer level process for manufacturing leadframe and device from the same |
US11/163,134 US20060084202A1 (en) | 2004-10-19 | 2005-10-06 | Wafer Level Process for Manufacturing Leadframes and Device from the Same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093131686A TWI250633B (en) | 2004-10-19 | 2004-10-19 | Wafer level process for manufacturing leadframe and device from the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI250633B TWI250633B (en) | 2006-03-01 |
TW200614481A true TW200614481A (en) | 2006-05-01 |
Family
ID=36181282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093131686A TWI250633B (en) | 2004-10-19 | 2004-10-19 | Wafer level process for manufacturing leadframe and device from the same |
Country Status (2)
Country | Link |
---|---|
US (1) | US20060084202A1 (zh) |
TW (1) | TWI250633B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI460837B (zh) * | 2012-06-19 | 2014-11-11 | Chipbond Technology Corp | 半導體封裝結構及其導線架 |
TWI550704B (zh) * | 2014-07-14 | 2016-09-21 | 國立屏東科技大學 | 半導體製程及其晶片結構與晶片組合結構 |
TWI550793B (zh) * | 2014-08-05 | 2016-09-21 | 國立屏東科技大學 | 晶片製程及其結構 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9136213B2 (en) * | 2012-08-02 | 2015-09-15 | Infineon Technologies Ag | Integrated system and method of making the integrated system |
US9892952B2 (en) | 2014-07-25 | 2018-02-13 | Semiconductor Components Industries, Llc | Wafer level flat no-lead semiconductor packages and methods of manufacture |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5331235A (en) * | 1991-06-01 | 1994-07-19 | Goldstar Electron Co., Ltd. | Multi-chip semiconductor package |
US6407333B1 (en) * | 1997-11-04 | 2002-06-18 | Texas Instruments Incorporated | Wafer level packaging |
US6355555B1 (en) * | 2000-01-28 | 2002-03-12 | Advanced Micro Devices, Inc. | Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer |
US6770971B2 (en) * | 2002-06-14 | 2004-08-03 | Casio Computer Co., Ltd. | Semiconductor device and method of fabricating the same |
-
2004
- 2004-10-19 TW TW093131686A patent/TWI250633B/zh not_active IP Right Cessation
-
2005
- 2005-10-06 US US11/163,134 patent/US20060084202A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI460837B (zh) * | 2012-06-19 | 2014-11-11 | Chipbond Technology Corp | 半導體封裝結構及其導線架 |
TWI550704B (zh) * | 2014-07-14 | 2016-09-21 | 國立屏東科技大學 | 半導體製程及其晶片結構與晶片組合結構 |
TWI550793B (zh) * | 2014-08-05 | 2016-09-21 | 國立屏東科技大學 | 晶片製程及其結構 |
Also Published As
Publication number | Publication date |
---|---|
TWI250633B (en) | 2006-03-01 |
US20060084202A1 (en) | 2006-04-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |