TW200613993A - Method to provide cache management commands for a dma controller - Google Patents
Method to provide cache management commands for a dma controllerInfo
- Publication number
- TW200613993A TW200613993A TW094107376A TW94107376A TW200613993A TW 200613993 A TW200613993 A TW 200613993A TW 094107376 A TW094107376 A TW 094107376A TW 94107376 A TW94107376 A TW 94107376A TW 200613993 A TW200613993 A TW 200613993A
- Authority
- TW
- Taiwan
- Prior art keywords
- cache
- commands
- cache management
- management commands
- dma
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/809,553 US7657667B2 (en) | 2004-03-25 | 2004-03-25 | Method to provide cache management commands for a DMA controller |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200613993A true TW200613993A (en) | 2006-05-01 |
TWI334540B TWI334540B (en) | 2010-12-11 |
Family
ID=34991472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094107376A TWI334540B (en) | 2004-03-25 | 2005-03-10 | Method to provide cache management commands for a dma controller |
Country Status (4)
Country | Link |
---|---|
US (1) | US7657667B2 (zh) |
JP (1) | JP2005276199A (zh) |
CN (1) | CN100407169C (zh) |
TW (1) | TWI334540B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8892825B2 (en) | 2008-10-29 | 2014-11-18 | Silicon Image, Inc. | Method and system for improving serial port memory communication latency and reliability |
TWI467381B (zh) * | 2008-10-23 | 2015-01-01 | Silicon Image Inc | 用於降低記憶體潛時之方法、裝置及系統 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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US7200689B2 (en) * | 2003-07-31 | 2007-04-03 | International Business Machines Corporation | Cacheable DMA |
US20060100997A1 (en) * | 2004-10-27 | 2006-05-11 | Wall Gary C | Data caching |
US7644198B2 (en) * | 2005-10-07 | 2010-01-05 | International Business Machines Corporation | DMAC translation mechanism |
US7752350B2 (en) * | 2007-02-23 | 2010-07-06 | International Business Machines Corporation | System and method for efficient implementation of software-managed cache |
US8006039B2 (en) | 2008-02-25 | 2011-08-23 | International Business Machines Corporation | Method, system, and computer program product for merging data |
CN101676887B (zh) * | 2008-08-15 | 2012-07-25 | 北京北大众志微系统科技有限责任公司 | 一种基于ahb总线结构的总线监听方法及装置 |
JP2011076232A (ja) * | 2009-09-29 | 2011-04-14 | Fujitsu Ltd | 演算処理装置,半導体集積回路および演算処理方法 |
US8352646B2 (en) * | 2010-12-16 | 2013-01-08 | International Business Machines Corporation | Direct access to cache memory |
US9575898B2 (en) * | 2013-03-28 | 2017-02-21 | Hewlett Packard Enterprise Development Lp | Implementing coherency with reflective memory |
US10248567B2 (en) | 2014-06-16 | 2019-04-02 | Hewlett-Packard Development Company, L.P. | Cache coherency for direct memory access operations |
US9904626B2 (en) * | 2014-08-29 | 2018-02-27 | Samsung Electronics Co., Ltd. | Semiconductor device, semiconductor system and system on chip |
US10049052B2 (en) | 2014-10-27 | 2018-08-14 | Nxp Usa, Inc. | Device having a cache memory |
US10210088B2 (en) | 2015-12-28 | 2019-02-19 | Nxp Usa, Inc. | Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache invalidation unit in a computing system |
US11372645B2 (en) * | 2020-06-12 | 2022-06-28 | Qualcomm Incorporated | Deferred command execution |
US20230195490A1 (en) * | 2021-12-16 | 2023-06-22 | International Business Machines Corporation | Adjunct processor (ap) domain zeroize |
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US5263142A (en) * | 1990-04-12 | 1993-11-16 | Sun Microsystems, Inc. | Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices |
JPH08263424A (ja) | 1995-03-20 | 1996-10-11 | Fujitsu Ltd | コンピュータ装置 |
US5893165A (en) | 1996-07-01 | 1999-04-06 | Sun Microsystems, Inc. | System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO |
US5953538A (en) | 1996-11-12 | 1999-09-14 | Digital Equipment Corporation | Method and apparatus providing DMA transfers between devices coupled to different host bus bridges |
US6015279A (en) * | 1996-11-15 | 2000-01-18 | Hitachi Metals, Ltd. | Vane and method for producing same |
US6381657B2 (en) | 1997-01-31 | 2002-04-30 | Hewlett-Packard Company | Sharing list for multi-node DMA write operations |
JP4134357B2 (ja) | 1997-05-15 | 2008-08-20 | 株式会社日立製作所 | 分散データ管理方法 |
US6658537B2 (en) | 1997-06-09 | 2003-12-02 | 3Com Corporation | DMA driven processor cache |
US6178533B1 (en) | 1997-06-30 | 2001-01-23 | Sun Microsystems, Inc. | Method and system for design verification |
US5890271A (en) | 1997-07-30 | 1999-04-06 | Davco Packing And Seals, Inc. | Insertion tool |
JPH1165989A (ja) * | 1997-08-22 | 1999-03-09 | Sony Computer Entertainment:Kk | 情報処理装置 |
JP3289661B2 (ja) | 1997-11-07 | 2002-06-10 | 日本電気株式会社 | キャッシュメモリシステム |
US6247094B1 (en) | 1997-12-22 | 2001-06-12 | Intel Corporation | Cache memory architecture with on-chip tag array and off-chip data array |
US6205409B1 (en) | 1998-06-26 | 2001-03-20 | Advanced Micro Devices, Inc. | Predictive failure monitoring system for a mass flow controller |
US6401193B1 (en) | 1998-10-26 | 2002-06-04 | Infineon Technologies North America Corp. | Dynamic data prefetching based on program counter and addressing mode |
EP1059589B1 (en) * | 1999-06-09 | 2005-03-30 | Texas Instruments Incorporated | Multi-channel DMA with scheduled ports |
DE19939763A1 (de) | 1999-08-21 | 2001-02-22 | Philips Corp Intellectual Pty | Multiprozessorsystem |
US6363906B1 (en) * | 2000-03-06 | 2002-04-02 | Detroit Diesel Corporation | Idle shutdown override with defeat protection |
US6859862B1 (en) * | 2000-04-07 | 2005-02-22 | Nintendo Co., Ltd. | Method and apparatus for software management of on-chip cache |
US6636906B1 (en) | 2000-04-28 | 2003-10-21 | Hewlett-Packard Development Company, L.P. | Apparatus and method for ensuring forward progress in coherent I/O systems |
EP1182561B1 (en) | 2000-08-21 | 2011-10-05 | Texas Instruments France | Cache with block prefetch and DMA |
US6874039B2 (en) | 2000-09-08 | 2005-03-29 | Intel Corporation | Method and apparatus for distributed direct memory access for systems on chip |
JP3681647B2 (ja) | 2001-02-21 | 2005-08-10 | 株式会社半導体理工学研究センター | キャッシュメモリシステム装置 |
US6526491B2 (en) | 2001-03-22 | 2003-02-25 | Sony Corporation Entertainment Inc. | Memory protection system and method for computer architecture for broadband networks |
US20030154349A1 (en) | 2002-01-24 | 2003-08-14 | Berg Stefan G. | Program-directed cache prefetching for media processors |
US6842822B2 (en) | 2002-04-05 | 2005-01-11 | Freescale Semiconductor, Inc. | System and method for cache external writing |
DE10223178B4 (de) | 2002-05-24 | 2004-11-04 | Infineon Technologies Ag | Schaltungsanordnung mit einer Ablaufsteuerung, integrierter Speicher sowie Testanordnung mit einer derartigen Schaltungsanordnung |
US6711650B1 (en) | 2002-11-07 | 2004-03-23 | International Business Machines Corporation | Method and apparatus for accelerating input/output processing using cache injections |
US20050210204A1 (en) | 2003-01-27 | 2005-09-22 | Fujitsu Limited | Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method |
US20040193754A1 (en) | 2003-03-27 | 2004-09-30 | International Business Machines Corporation | DMA prefetch |
JP2004326633A (ja) | 2003-04-28 | 2004-11-18 | Hitachi Ltd | 階層型メモリシステム |
US7114042B2 (en) | 2003-05-22 | 2006-09-26 | International Business Machines Corporation | Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment |
US7200689B2 (en) | 2003-07-31 | 2007-04-03 | International Business Machines Corporation | Cacheable DMA |
US7287101B2 (en) * | 2003-08-05 | 2007-10-23 | Intel Corporation | Direct memory access using memory descriptor list |
-
2004
- 2004-03-25 US US10/809,553 patent/US7657667B2/en not_active Expired - Fee Related
-
2005
- 2005-03-04 CN CN2005100541094A patent/CN100407169C/zh not_active Expired - Fee Related
- 2005-03-10 TW TW094107376A patent/TWI334540B/zh not_active IP Right Cessation
- 2005-03-16 JP JP2005076047A patent/JP2005276199A/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI467381B (zh) * | 2008-10-23 | 2015-01-01 | Silicon Image Inc | 用於降低記憶體潛時之方法、裝置及系統 |
US8892825B2 (en) | 2008-10-29 | 2014-11-18 | Silicon Image, Inc. | Method and system for improving serial port memory communication latency and reliability |
US10056123B2 (en) | 2008-10-29 | 2018-08-21 | Lattice Semiconductor Corporation | Method and system for improving serial port memory communication latency and reliability |
Also Published As
Publication number | Publication date |
---|---|
US7657667B2 (en) | 2010-02-02 |
TWI334540B (en) | 2010-12-11 |
US20050216610A1 (en) | 2005-09-29 |
CN1673980A (zh) | 2005-09-28 |
CN100407169C (zh) | 2008-07-30 |
JP2005276199A (ja) | 2005-10-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |