TW200609985A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

Info

Publication number
TW200609985A
TW200609985A TW094126519A TW94126519A TW200609985A TW 200609985 A TW200609985 A TW 200609985A TW 094126519 A TW094126519 A TW 094126519A TW 94126519 A TW94126519 A TW 94126519A TW 200609985 A TW200609985 A TW 200609985A
Authority
TW
Taiwan
Prior art keywords
impurity
introducing
gate electrode
semiconductor device
forming
Prior art date
Application number
TW094126519A
Other languages
Chinese (zh)
Inventor
Cheng-Guo Jin
Yuichiro Sasaki
Hiroyuki Ito
Bunji Mizuno
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200609985A publication Critical patent/TW200609985A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method is provided for manufacturing a highly accurate fine transistor having source/drain regions (310, 320) in an area wherein an impurity is introduced. The method includes a step of forming a gate electrode (340) on a front plane of a semiconductor substrate, a step of introducing the impurity so as to sandwich the gate electrode (340), and a step of activating the impurity. The step of introducing the impurity includes a plasma irradiation step, and prior to the activation step, a step of forming a reflection preventing film (400) is included so as to have a small light reflectance of the area wherein the impurity is introduced.
TW094126519A 2004-08-04 2005-08-04 Semiconductor device manufacturing method TW200609985A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004228198 2004-08-04

Publications (1)

Publication Number Publication Date
TW200609985A true TW200609985A (en) 2006-03-16

Family

ID=35787179

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094126519A TW200609985A (en) 2004-08-04 2005-08-04 Semiconductor device manufacturing method

Country Status (5)

Country Link
US (1) US20090023262A1 (en)
JP (1) JPWO2006013898A1 (en)
CN (1) CN1993818A (en)
TW (1) TW200609985A (en)
WO (1) WO2006013898A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7569463B2 (en) * 2006-03-08 2009-08-04 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
JP2008021827A (en) * 2006-07-13 2008-01-31 Renesas Technology Corp Manufacturing method for semiconductor device
JP6560653B2 (en) 2015-12-21 2019-08-14 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ Selective heating method for elongated nanoscale structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3297770B2 (en) * 1993-10-15 2002-07-02 ソニー株式会社 Method for manufacturing semiconductor device
JP3535871B2 (en) * 2002-06-13 2004-06-07 キヤノン株式会社 Electron emitting device, electron source, image display device, and method of manufacturing electron emitting device
JP2004087583A (en) * 2002-08-23 2004-03-18 Seiko Epson Corp Semiconductor device, its manufacturing method and heat treatment method of thin film
US20060024938A1 (en) * 2004-07-29 2006-02-02 Texas Instruments, Incorporated Method for reducing metal silicide excessive encroachment defects in the manufacture of a semiconductor device having silicided source/drain regions

Also Published As

Publication number Publication date
CN1993818A (en) 2007-07-04
WO2006013898A1 (en) 2006-02-09
US20090023262A1 (en) 2009-01-22
JPWO2006013898A1 (en) 2008-05-01

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