TW200601511A - Method for manufacturing stacked multi-chip package - Google Patents
Method for manufacturing stacked multi-chip packageInfo
- Publication number
- TW200601511A TW200601511A TW093118578A TW93118578A TW200601511A TW 200601511 A TW200601511 A TW 200601511A TW 093118578 A TW093118578 A TW 093118578A TW 93118578 A TW93118578 A TW 93118578A TW 200601511 A TW200601511 A TW 200601511A
- Authority
- TW
- Taiwan
- Prior art keywords
- chip
- bonding
- stacked multi
- chip package
- bonding pad
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093118578A TWI236744B (en) | 2004-06-25 | 2004-06-25 | Method for manufacturing stacked multi-chip package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093118578A TWI236744B (en) | 2004-06-25 | 2004-06-25 | Method for manufacturing stacked multi-chip package |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI236744B TWI236744B (en) | 2005-07-21 |
TW200601511A true TW200601511A (en) | 2006-01-01 |
Family
ID=36675027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093118578A TWI236744B (en) | 2004-06-25 | 2004-06-25 | Method for manufacturing stacked multi-chip package |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI236744B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI478250B (zh) * | 2007-12-12 | 2015-03-21 | Stats Chippac Ltd | 具有可設置的積體電路晶粒之可設置的積體電路封裝件系統 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG130055A1 (en) | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
US7687897B2 (en) * | 2006-12-28 | 2010-03-30 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system with adhesive spacing structures |
TWI383509B (zh) * | 2007-01-05 | 2013-01-21 | Univ Chang Gung | A method of stacking solar cells |
TW200917431A (en) | 2007-10-05 | 2009-04-16 | Advanced Semiconductor Eng | Stacked-type chip package structure and method of fabricating the same |
-
2004
- 2004-06-25 TW TW093118578A patent/TWI236744B/zh active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI478250B (zh) * | 2007-12-12 | 2015-03-21 | Stats Chippac Ltd | 具有可設置的積體電路晶粒之可設置的積體電路封裝件系統 |
Also Published As
Publication number | Publication date |
---|---|
TWI236744B (en) | 2005-07-21 |
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