TW200601436A - Process for 2-D buckled SiGe quantum wells of elastic film on semiconductors - Google Patents

Process for 2-D buckled SiGe quantum wells of elastic film on semiconductors

Info

Publication number
TW200601436A
TW200601436A TW093119773A TW93119773A TW200601436A TW 200601436 A TW200601436 A TW 200601436A TW 093119773 A TW093119773 A TW 093119773A TW 93119773 A TW93119773 A TW 93119773A TW 200601436 A TW200601436 A TW 200601436A
Authority
TW
Taiwan
Prior art keywords
buckled
substrate
quantum wells
layer
sige quantum
Prior art date
Application number
TW093119773A
Other languages
Chinese (zh)
Other versions
TWI247348B (en
Inventor
Chee-Wee Liu
Cheng-Yeh Yu
Po-Wen Chen
Original Assignee
Univ Nat Taiwan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Taiwan filed Critical Univ Nat Taiwan
Priority to TW93119773A priority Critical patent/TWI247348B/en
Publication of TW200601436A publication Critical patent/TW200601436A/en
Application granted granted Critical
Publication of TWI247348B publication Critical patent/TWI247348B/en

Links

Abstract

The present invention provides a process for 2-D buckled SiGe quantum wells, which includes the following steps: providing a first substrate; growing a semiconductor layer on the first substrate, and the material of the semiconductor layer is different from that of the first substrate; growing a first capping layer on the semiconductor layer to form a first wafer structure; conducting ion implantation on the first wafer structure to form an ion implantation layer; providing a second substrate; growing a second capping layer on the second substrate to form a second wafer structure; aligning the first and the second capping layers as face-to-face and bonding the first and the second wafer structures; conducting the first high temperature process to separate the first and the second wafer structures at the ion implantation layer; and, conducting the second high temperature process to generate the 2-D buckled SiGe quantum wells on the separated surface.
TW93119773A 2004-06-30 2004-06-30 Process for two-dimensional buckled quantum well TWI247348B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW93119773A TWI247348B (en) 2004-06-30 2004-06-30 Process for two-dimensional buckled quantum well

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW93119773A TWI247348B (en) 2004-06-30 2004-06-30 Process for two-dimensional buckled quantum well

Publications (2)

Publication Number Publication Date
TW200601436A true TW200601436A (en) 2006-01-01
TWI247348B TWI247348B (en) 2006-01-11

Family

ID=37399840

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93119773A TWI247348B (en) 2004-06-30 2004-06-30 Process for two-dimensional buckled quantum well

Country Status (1)

Country Link
TW (1) TWI247348B (en)

Also Published As

Publication number Publication date
TWI247348B (en) 2006-01-11

Similar Documents

Publication Publication Date Title
SG125932A1 (en) Method of forming strained silicon on insulator substrate
WO2009019837A1 (en) Silicon carbide semiconductor device and method for producing the same
WO2007142911A3 (en) Semiconductor on insulator structure made using radiation annealing
TW200608455A (en) Semiconductor film manufacturing method and substrate manufacturing method
TW200729343A (en) Method for fabricating controlled stress silicon nitride films
WO2004006311A3 (en) Transfer of a thin layer from a wafer comprising a buffer layer
TW200629352A (en) Hetero-integrated strained silicon n- and p- MOSFETS
WO2008042732A3 (en) Recessed sti for wide transistors
WO2011109146A3 (en) Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
TW200746430A (en) Method of manufacturing semiconductor device, and semiconductor device
WO2014020906A1 (en) Method for manufacturing composite substrate and method for manufacturing semiconductor crystal layer formation substrate
WO2008033508A3 (en) Image sensor using thin-film soi
AU2003247130A1 (en) Method of transferring of a layer of strained semiconductor material
TW200701335A (en) Nitride semiconductor device and manufacturing mathod thereof
TW200511578A (en) Self-aligned SOI with different crystal orientation using wafer bonding and simox processes
WO2012052257A3 (en) Optoelectronic semiconductor chip and method for the production thereof
WO2014017063A1 (en) Semiconductor substrate, method for manufacturing semiconductor substrate, and method for manufacturing composite substrate
WO2006012838A3 (en) Method for producing semiconductor chips using thin-film technology and a semiconductor chip produced using thin-film technology
WO2011139875A3 (en) Tce compensation for ic package substrates for reduced die warpage assembly
JP2013080897A (en) Composite substrate manufacturing method
WO2007072655A3 (en) Lateral soi semiconductor devices and manufacturing method thereof
TW200746262A (en) Method of manufacturing nitride semiconductor substrate and composite material substrate
WO2007044530A3 (en) Methods and apparatus for epitaxial film formation
TW200631078A (en) A method of making a semiconductor structure for high power semiconductor devices
WO2007142865A3 (en) Thin film photovoltaic structure and fabrication

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees