TW200601338A - Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory - Google Patents

Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory

Info

Publication number
TW200601338A
TW200601338A TW093136825A TW93136825A TW200601338A TW 200601338 A TW200601338 A TW 200601338A TW 093136825 A TW093136825 A TW 093136825A TW 93136825 A TW93136825 A TW 93136825A TW 200601338 A TW200601338 A TW 200601338A
Authority
TW
Taiwan
Prior art keywords
charge
threshold voltage
memory device
work function
high work
Prior art date
Application number
TW093136825A
Other languages
Chinese (zh)
Other versions
TWI250526B (en
Inventor
Yen-Hao Shih
Hang-Ting Lue
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/876,374 external-priority patent/US7164603B2/en
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Publication of TW200601338A publication Critical patent/TW200601338A/en
Application granted granted Critical
Publication of TWI250526B publication Critical patent/TWI250526B/en

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory device with a charge trapping layer has multiple bias arrangements to cange the threshold voltage of the memory device and record digital signal, 0 or 1, through the change of the threshold voltage. In the conventional memory device, multiple cycles of applying the bias arrangements lowering and raising a threshold voltage leave a distribution of charge in the charge trapping layer. The distribution of charge interferes with the achievable lowest threshold voltage. This distribution of charge is balanced by applying a charge balancing bias arrangement, and thus the operative range of the lowest threshold voltage is recoved. The memory device having a high work function gate can reduce the lowest threshold voltage in the equilibrium state of the charge balancing bias arrangement.
TW093136825A 2004-06-24 2004-11-30 Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory TWI250526B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/876,374 US7164603B2 (en) 2004-04-26 2004-06-24 Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory

Publications (2)

Publication Number Publication Date
TW200601338A true TW200601338A (en) 2006-01-01
TWI250526B TWI250526B (en) 2006-03-01

Family

ID=35718919

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093136825A TWI250526B (en) 2004-06-24 2004-11-30 Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory

Country Status (2)

Country Link
CN (1) CN100391000C (en)
TW (1) TWI250526B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572015B (en) * 2007-05-25 2017-02-21 賽普拉斯半導體公司 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
TWI660271B (en) * 2018-04-24 2019-05-21 群聯電子股份有限公司 Trim command recording method, memory control circuit unit and memory storage apparatus

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102298971B (en) * 2011-08-29 2014-05-21 南京大学 Operation method for high-density multilevel storage of non-volatile flash memory
US10049750B2 (en) * 2016-11-14 2018-08-14 Micron Technology, Inc. Methods including establishing a negative body potential in a memory cell
CN110442300B (en) * 2018-05-03 2022-12-13 群联电子股份有限公司 Sorting instruction recording method, memory control circuit unit and memory device
CN111370046B (en) * 2020-03-19 2022-04-19 中国科学院微电子研究所 Programming method and programming system of three-dimensional memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL125604A (en) * 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6436768B1 (en) * 2001-06-27 2002-08-20 Advanced Micro Devices, Inc. Source drain implant during ONO formation for improved isolation of SONOS devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572015B (en) * 2007-05-25 2017-02-21 賽普拉斯半導體公司 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
TWI660271B (en) * 2018-04-24 2019-05-21 群聯電子股份有限公司 Trim command recording method, memory control circuit unit and memory storage apparatus

Also Published As

Publication number Publication date
TWI250526B (en) 2006-03-01
CN1713391A (en) 2005-12-28
CN100391000C (en) 2008-05-28

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