TW200539358A - Method for preventing short-circuit caused by soldering pin of semiconductor component - Google Patents

Abstract

A kind of method for preventing short-circuit caused by soldering a pin of semiconductor component, in which the pin is soldered on a circuit board; the disclosed method can selectively forms a solder resistant area on the circuit board or on the pin so as to form a solder resist coating thereon. Therefore, when the pin is soldered, the solder is blocked by the solder resist existing in the solder resistant area, thereby preventing the short-circuit arising from the solder residue while soldering the pin.

Description

200539358 V. Description of the invention (1) [Technical collar city to which the invention belongs] The present invention relates to a soldering method, and more particularly, to a method for preventing short-circuiting of the pins of semiconductor components. [Previous technology] With the rapid development of science and technology, the functions of semiconductor devices have become increasingly powerful, but the volume has continued to decrease. As a result, the number of pins of semiconductor devices has increased greatly, the distance between pins has become smaller and smaller, and the density has increased Bigger. However, in the conventional technology, when soldering the pins of a semiconductor component to a circuit board, appropriate protective measures have not been taken to prevent the pins from being leaked between the pins and causing the pins. Electrical conduction between the two; further short-circuiting of the semiconductor element, and even worse, burnout of the circuit board.

Please refer to FIG. 1. A pin through hole (PTH) package semiconductor device 100 includes a plurality of pins 100, wherein the pin through hole package semiconductor device may include a dual-row package ( Duan I n ~ 1 i ne Package (DIP) components, Shrink DIp (SDIP) components, Thin Film DIP (SK-DIP) components' Single In-line Package SIP) components, Zig-Zag In-iine package (ZIP) components, and Pin Grid Array (pGA) package components. The semiconductor device 100 is connected to a circuit through its plural pins 丨 20: plug? Within 13 ° of the hole ’, soldering is then used to install the circuit. 辉 During the twisting process, the 'Hui Tin 140 is extremely easy to lift from the insertion hole 13 to the circuit board surface in the direction of M in the figure.

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The phenomenon of tin overflow. As soon as the glow tins overflowing from the adjacent pins 120 are turned on to each other, a short circuit of the semiconductor device 100 will be caused. Please refer to Figure 2 and Figure 3 'for a surface mount technology (SMT) package semiconductor device 2 0 0 including a plurality of pins 2 2 0, wherein the surface mount package semiconductor device may include a miniaturized package (Small Out-line Package; S0P) components, Quad Flat Package (QFP) components, Leadless Chip carrier (LCC) components, Plastic Leadless Chip Carrier (PLCC) ) Components, Leadless Chip carrier (LCC) components, small outline j lead package (small

Out-Line J-Lead (SOJ) components, Ball Grid Array (BGA) components, Tape Automated Bonding (TAB) components, and Chip Scale Package (CSP) element. The semiconductor device 2 0 0 is connected to a circuit board 2 1 0 by a plurality of pins 2 2 0 of the semiconductor device 2 0 through a plurality of glow tin 2 4 0. However, since the distance between the plural pins 2 2 0 is relatively small, it is extremely easy for tin overflow to occur between adjacent pins 2 2 0, thereby causing the adjacent pins 2 2 0 to be turned on and short-circuited. Please refer to FIG. 4. In the figure, a solder ball array packaged on a circuit board 3 1 0 and a semiconductor ball 3 400 is also extremely prone to solder overflow; even as shown in FIG. 5, Setting a plurality of solder pads 3 1 0 on the circuit board 3 10 cannot effectively prevent the occurrence of tin overflow. Therefore, the inventors have proposed a method for effectively preventing semiconductors in view of this.

17916 Yingyeda.ptd Page 5 200539358 V. Description of the invention (3) The component pin 纟 f is connected to a short circuit. [Abstract] In order to overcome the above defects. The purpose of the present invention is to provide a method for semiconductor device pin soldering short circuit, which is simple and can effectively prevent the present invention from preventing semiconducting engraving. The two pins described above are soldered to a thunderbolt f element. A method for short-to-foot soldering includes the following: setting a contact £ j, one of the preferred states of the method Γ iL: dagger: the splice area is located at the periphery of the contact area to improve; a; 枓? The pin is soldered to the contact and a resistance is placed on it. # 中 ， 此: Shrink the "peripheral" to provide-solder resist coverage ^ ^ The human area, zinc area, and solder resist area are circular, rectangular, or other different geometric shapes. The solder system Tin, the solder resist is white paint or green paint. The solder resist is covered on the solder area by any method selected from spray coating, coating, and printing. The semiconductor element is a pin through hole type (Pin Through Hole; PTH) packaged semiconductor components can be Duan In-line Package (DIP) components, Shrink DIP (SDIP) components, Skinny DIP (SK-DIP) components , Single In-line Package (SIP) components, Zig-Zag In-line Package (ZIP) components, and Pin-in-Grid Array (P in G rid A rr ay; PG A) packages Any one of the components. The semiconductor device can also be a surface mount technology (SMT) packaged semiconductor device, which can be a Small Out-line Package (S0P) device.

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V. Description of the invention (4) (Quad Flat Package; QFP) components, Leadless Chip carrier (LCC) components, Plastic Leadless Chip Carrier (PLCC) components, Leading Chip Carrier Package (Lead less Chip carrier; LCC) components, small outline J-lead package (Small Out-Line J-Lead; SOJ) component reels self-contained, with the conductor element pins soldered in the pieces up to the state, the Body parts cover all the plug holes above the plug-in surface; or Ball Grid Array (BGA) components, Tape Automated Bonding (TAB), and Chip Scale Package CSP) element. The solder ball array is dynamically bonded and packaged. The present invention prevents the pin through hole from being short-circuited. In this method, at least a part of the circuit board is provided thereon; and inside the hole, such that. Among them, on the pin; or on the pin. In this way, making the solder resist invention prevent semi-single and implement semiconductor packaging effect may include: having at least the solder resist on the pin to space the conductor element below the semi-conductive solder resist area is cheap The component connection semiconductor is provided with a conductor element and a partial resistance system in the same way as described above. The lower edge of the body component has a pin, and the pin is connected to the corresponding solder mask area when the component is soldered. The soldering area is located in the half of the pin edge provided in the half of the method suitable for a large short circuit below the electrical welding short to prevent another preferred implementation of the semiconductor component from being soldered to a circuit board plug hole; to provide a pin plug The method of connecting to the electrical conductor element, the semiconductor plug to the circuit board, and the surface of the circuit board is to produce a semiconductor mask on the surface of the circuit board at least in part and at least the surface of the circuit board. Has the advantage of implementation.

17916 Yingyeda.ptd Page 7 200539358 V. Description of the invention (5) ~ ----------- [Embodiment] The following is a description of specific examples of the present invention. What is disclosed in this specification is ^ =, which is another advantage and effect of the present invention. The present invention can also be implemented or applied through direct understanding of specific examples. The details in this specification have different perspectives and applications, without departing from the spirit of the present invention: based on and changed. In particular, in order to show the characteristics of the semiconducting structure of the present invention simply and clearly, the drawings in this case only show the important components: drawings; in actual applications, the shape and connection of these elements Potential ^ = complex, the number of related components can also vary with different types of packages 2

Please refer to FIG. 6. The first embodiment of the method for preventing soldering shorting of the pins of the semiconductor element according to the present invention includes a semiconductor board to be soldered on a circuit board. The contact area 2, the two j contact area 14 ′, and a solder resist area 16. The above semiconductor components can be pin through hole (PTH) packaged semiconductor components, including i Dual In-line Package (DIP) components, and Shrink DIP (SDIP) components. , Thin film in-line package & (Skinny DIP; SK-DIP) components, single-line package (Single "

In-line Package (SIP) components, Zig-Zag In-line Package (ZIP) components, and pin Grid Array (PGA) package components; also surface-mountable (Surface Mount Technology; SMT)

17916 Yingyeda.ptd Page 8 200539358 V. Description of the Invention (6) Includes Small Out-line Package (SOP) components, Quad Flat Package (QFP) components, and lead chip carrier package ( Leadless Chip carrier (LCC) components, Plastic Leadless Chip Carrier (PLCC) components, Leadless Chip carrier packaging (Leadless

Chip carrier (LCC) components, Small Outline-Line J-Lead (SOJ) components, Ball Grid Array (BGA) components, Tape Automated Bonding; TAB ) Components, and Chip Scale Package (CSP) components. The contact area 12 is used for bonding the semiconductor element pins, that is, an area where the semiconductor element pins are in direct contact with the circuit board 10. In Figure 6, the contact area 2 is a

An area such as a circular geometric pattern. Zone 12 is external to a solder (generally firmly attached to the circuit board 10. In areas such as a circular geometric pattern. Zone 14 is externally sprayed, coated, or painted or green-lacquered) on Thereby, when the pins are on the circuit board, the pins are connected and connected to each other, which causes the pin short components and even the circuit board 10. In the area of the circular geometric pattern. The soldering area 14 is arranged on the contact as tin) The semiconductor component pin is shown in FIG. 6, the soldering area 14 is a solder resisting area 16 is disposed on the soldering and printing a layer of solder resist (generally white) The solder between the above-mentioned semiconductor components is flashed, and the semiconductor 3 is more severely burned. The solder resist 16 is a component such as

3 To understand that when contacting a 7L 1-series needle element, the contact area 12 may be a plug hole.

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200539358 V. Description of the invention (7) Please refer to FIG. 7. As a second embodiment of the short-circuiting method of the present invention, a two-way board 10 ′ is used to stop the semiconductor element pins and to solder the body element pins (not shown). The above-mentioned welding semiconductor 12 ', a welding area 14, and a solder resist are provided outside the "contact area". The first embodiment differs from the following: the two "f 6 °" and this embodiment are different from this and a resistance The pad 16 'is provided as a region such as a pad 2', a pad 14, and a pattern. > Several (including square) It can also be understood that when the bumper conductor element, the contact area i ^ # is a pin through-hole package half ^ ^ ^ is a plug slot. # The contact area ι 2, 1 4 ′, and the solder resist area 16, i 6, the zinc bonding area 1 4, and the pattern area of the embodiment of the second and third embodiments; also based on the half body: : Shapes, rectangles, and other geometric patterns other than circles or rectangles P $ = Shapes are set to contact areas 12, 12, and fresh areas ", M," = said = Η, rectangular geometric patterns or other Figures of different shapes,, and the combination of the two. The above-mentioned shape (geometric pattern) or: The contact-seeking areas 12, 12, welding areas 14, 14, and solder resist / area f satisfy 16 The conditions set inside and outside can achieve the effect of preventing the shorting of the soldering of the lead pins of the lead. Figure 8 shows the semi-conductor, which is widely shown when the semiconductor component is a pin through-hole package. A third embodiment made according to the present invention to prevent the semiconductor element: the concept of the law. A pin through-hole seal: The element 20 includes a plurality of pins 22, and the glow region 24 'is held at each pin 22. To spray, coat, or print a layer of light-blocking agent (= white

179] 6 Yingye Da. Pit (3 Page 10 200539358 V. Description of Invention (8) Lacquer or green paint) on it. Cage addiction, a yoke of the thunderbolt yoke 30, when you read the figure 9 to plug these pins 22 into the plug holes 32 of the circuit board, so that the circuit board of the solder mask area 24 The surface alignment is like 筮】 ^ 円 所-, ', below the person 24, the real end is identified as shown in the figure 10, which makes these solder resist areas 24 ,,, and 彖 slightly lower. On the surface of the circuit board 30. In this way, the semiconductor component pin can be short-circuited. Even during the soldering process, ^ / (generally tin) rises along the insertion hole 32 of the circuit board 30 to the surface of the addiction, and a tin overflow occurs on the surface. Pin 22 is also protected by the solder resist of 30, 30, and does not lead to electrical continuity, so that these pins / pins are 24 way, and then the semiconductor element 20 or the circuit board 3 is burned. Please refer to FIG. 11. In the fourth embodiment of the method for preventing a semiconductor element according to the present invention, the solder resist regions 24 can also be set in a proper position on the pins 22. Similarly, the two pins of PffiJ and other pins 22 may not be electrically turned on and short-circuited, and then the function of f to protect the 20 or the circuit board 30 is burned. It can be understood that when the semiconductor element is a pin-through-hole type seal, the present invention prevents the soldering of the semiconductor element pin from being short-circuited. = V body element 3. The fourth embodiment can also be applied to the first, Act No. 1 to achieve better results. -In the embodiments, the above-mentioned embodiments only exemplify the principle of the present invention and are not intended to limit the present invention. Anyone who is familiar with this technique ^ effects, but does not violate the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as follows: The scope is listed. Claim patent

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200539358 Brief description of the drawings [Schematic fs] single description] Figures 1 to 5 are conventional schematic diagrams of soldering of semiconductor component pins; Figure 6 is a first embodiment of the method for preventing shorting of semiconductor component pin soldering according to the present invention. Schematic diagram; FIG. 7 is an unintended example of the second embodiment of the method for preventing short-circuiting of semiconductor component pin soldering according to the present invention, and FIGS. 8 to 10 are the third implementation of the method for preventing short-circuiting of semiconductor component pin soldering according to the present invention; The schematic diagram of the example; and FIG. 11 are schematic diagrams of the fourth embodiment of the method for preventing the short circuit of the soldering of the pin of the semiconductor element according to the present invention. (Description of component symbols) 10 '10, 30 ^ 110, 210, 310 Circuit board 12 ^ W Contact area 14, 14' Solder area 16, 16, 24 Block resistance 20, 100 > 2 0 0 > 300 Semiconductor component 11, 120 ^ 220 pin 32 > 130 plug hole 40 solder 140, 240 solder 312 solder pad 340 fresh ball

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Claims (1)

200539358 6. Scope of patent application1. A method for preventing soldering of semiconductor component pins to a circuit board by short-circuit welding. The method includes: < wanfa, the pin is provided with a contact area, and the pin is provided in the contact area. Peripheral two contact area; the pin is welded in the soldering area to provide a soldering arrangement-the "," located on the periphery of the fresh soldering area; and the solder is covered thereon. Fresh to provide a resistance 2. The method for preventing short circuit as described in item 丨 of the scope of patent application, wherein the contact area and the pins of the + conductor are welded with geometric figures respectively. In the acquisition area and solder resist area 3. If the scope of patent application is 帛The method for preventing short circuit as described in item 2, wherein the pins of the geometrical figure conductor are welded. 4. The prevention as described in item 2 of the scope of patent application) ° A method for short circuit, where the geometric figure is the body of V Pin Welding 5. Prevention as described in item i of the scope of patent application: 'Semi-conducting body. 0 Short circuit method, where the contact area, production / pin welding are different geometries. ^ Area, and Solder mask 6 The method of preventing short-circuits as described in item 丨 of the scope of patent application, wherein the solder is used to weld the pins of all limbs. 7. The method of semi-short-circuit W as described in the scope of patent application, where the resistance is The freshener is composed of several pins of the conductor by soldering, coating, and printing. It is self-contained and covered by spraying on the soldering area. One of the group 8. As the scope of the patent application Prevents welding of 7C pins on half limbs 17916 Inventec.ptd 200539358 6. The party applying for a patent short circuit 9. The party applying for a short circuit 10. The party applying for a short circuit Through 1 1. The party applying for a short circuit is selected from the group consisting of) components, pieces, and thin film in-line sealed cross pins Pieces, and the method of forming the solder resist is white paint. The scope of the first item # + R described above is to prevent the soldering of the pins of the semiconductor components. 8 τ δ solder resist is a green paint. The scope of the first item is m, +, > Beans to prevent the soldering of semiconductor device pins, and the semiconductor device is a pin through hole (pin PTH) packaged semiconductor device. The method for preventing pin soldering of semiconductor elements according to the tenth item of the scope of interest, wherein the pin-through-hole package semiconductor element is a dual inline package (Duan In-line Package; Dlp Shrink DIP; SD IP) Skinny DIP (SK-DIP) element, Single in-line Package (SIp) element, Zig-Zag In-line Package (ZIP) element pin grid array Array; PGA) One of the group of package elements. 1 2 · The method for preventing soldering short circuit of a semiconductor element pin as described in item 1 of the scope of patent application, wherein the semiconductor element is a surface mount type (Surface Mount Technology) SMT) package semiconductor components. 1 3. The method for preventing soldering short circuit of the semiconductor component pins as described in item No. 2 of the patent application scope, wherein the surface-adhesive packaged semiconductor components are included in the miniaturized package (Small Out -line Package; SOP) components' Quacj Flat Package (QFP) components, Lead less Chip carrier; 200539358 VI. Application scope of patent (LCC) components, Plastic Leadless Chip Carrier (PLCC) components, Leadless Chip carrier (LCC) components, Small Outer Guide Foot Package (Small Out -Line J-Lead (S0J) components, Ball Grid Array (BGA) components, Tape Automated Bonding (TAB) components, and Chip Scale Package (CSP) components One of the formed groups. 14. The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 1 of the scope of the patent application, wherein the contact area is a plug hole. 15. The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 1 of the scope of the patent application, further comprising the step of providing a second solder resist area on at least a part of the pins of the semiconductor element to provide a solder resist. Cover it. '1 6 · The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 5 of the scope of the patent application, wherein the solder is disposed on at least a part of each pin of the semiconductor element. 17 · The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 5 of the scope of the patent application, wherein the soldering flux is disposed on at least part of the pins of the semiconductor element in a spaced manner. 1 8 · The method for preventing short circuit of the soldering of the pin of the semiconductor element as described in item 5 of the scope of the patent application, wherein, 'the pin of the semiconductor element is inserted into the circuit board, so that the second solder resist area The lower edge is flush with the surface of the circuit board. 200539358 VI. Application scope of patent 19. The method for preventing soldering short circuit of the pin of a semiconductor element as described in item 15 of the scope of patent application, wherein the pin of the semiconductor element is inserted into the circuit board, so that The lower edge of the second solder mask area is slightly lower than the surface of the circuit board. 20. The method for preventing short circuit of the soldering of the pin of a semiconductor element according to item 16 or item 17 of the scope of patent application, wherein the solder resist is composed of a method selected from spray coating, coating, and printing. One of the groups covers the second solder region. 2 1. The method for preventing the short circuit of the soldering of the pin of a semiconductor element as described in item 20 of the scope of patent application, wherein the solder resist is white paint. 2 2. The method for preventing a short circuit in the soldering of a pin of a semiconductor element as described in item 20 of the scope of patent application, wherein the solder resist is a green paint. 2 3. A method for preventing soldering short circuit of the pins of semiconductor components, the pins are soldered on a circuit board, and the circuit board is provided with plug holes corresponding to the pins, and the method includes: A solder mask is provided on at least part of the pins of the component to provide a solder resist to cover it; and the pins of the semiconductor component are inserted into the plug holes of the circuit board so that at least part of the solder mask is located The element is above the surface of the circuit board. 24. The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 23 of the scope of the patent application, wherein the semiconductor element is a pin-through-hole (PTT) packaged semiconductor element. 2 5. Prevent semiconductor component pin soldering as described in item 24 of the scope of patent application 17916 英 业 达 .ptd page 16 200539358 VI. Patent application method for short circuit connection, wherein the pin-through-hole package semiconductor component is selected from the group consisting of a dual inline package (Duan In-1ine Package; DIP) component, Shrink DIP (SDIP) components, thin film DIP (SK-DIP) components, Single In_line Package (SIP) components, Zig-Zag In- One of the groups consisting of line package (ZIP) components and pin grid array (PGA) package components. 26. The method for preventing short circuit of the soldering of the pin of the semiconductor element according to item 23 of the scope of the patent application, wherein the solder resist is provided on each pin of at least a part of the semiconductor element. 27. The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 23 of the scope of the patent application, wherein the solder resist is disposed on at least part of the pins of the semiconductor element in a spaced manner. 2 8 · The method for preventing short circuit of the soldering of a pin of a semiconductor element as described in item 23 of the scope of the patent application, wherein the pin of the semiconductor element is inserted into the insertion hole of the circuit board, so that the solder resist The lower edge of the area is flush with the surface of the circuit board. 29. The method for preventing fresh short-circuiting of the pins of the semiconductor element as described in item 23 of the scope of the patent application, wherein the pins of the semiconductor element are inserted into the insertion holes of the circuit board so that the solder resist The area is below the surface of the circuit board. % M 3 0 · The method for preventing short circuit of the soldering of the pin of a semiconductor element as described in item 23 of the scope of the patent application, wherein the solder resist is selected from 17916 Inventec. Ptd Page 17 200539358 VI. Scope of Patent Application One of the groups consisting of coating, coating, and printing is covered on the solder area. 31. The method for preventing the short circuit of the soldering of the pin of the semiconductor element as described in item 30 of the scope of patent application, wherein the solder resist is white paint. 32. The method for preventing the short circuit of the soldering of the pin of the semiconductor element as described in item 30 of the scope of patent application, wherein the solder resist is a green paint. 17916 Inventec.ptd Page 18