200537691 九、發明說明： 【發明所屬之技術領域】 本發明有關如主動矩陣電致 口口 ^光^員不态的主動矩陳德 裝置，該裝置在1俊音雷枚山， 勒兜丨旱像素 n、像素電路中併入光感測器 明有關此種裝置的製造，尤i " 有關（仁非專門）包含且右 晶矽通道之薄膜電晶體的主動矩陣像素裝置。-【先前技術】 採用發光顯示元件的主動矩陣電致發光顯示裝置係為眾 所皆知。顯示元件包含：有機薄膜電致發光元件，例如使 用聚合物材料；或另外使用傳__v半導體化合物的發光 二極體（LED)。最近有機電致發光材料（特別是聚合物材 :)的發展已展現它們實際上用於視訊顯示裝置的能力。 适些材料-般包括夾在一對電極之間的一或更多層半導電 共輛聚合物’其中一個電極透明，另一個則是適合注入電 洞或電子至聚合物層的材料。 主動矩陣電致發光顯示裝置一般包含像素的列與行陣 列。通常包含薄膜電晶體（TFT)的個別像素電路可控制對 各像素的顯示元件供應電流。在各像素電路中，會採用通 常稱為「驅動電晶體」的丁”之至少一個調整通過顯示元 件的電流。重要的是，驅動電晶體的電特性在整個顯示器 的操作中都报穩定。具有非晶矽通道的TFT已知在用於控 制連續電流時會遭遇如定限電壓漂移等問題。因此，在驅 動電晶體的使用上，具有多晶矽通道的TFT優於非晶矽 TFT。然而，TFT間多晶矽通道的結構差異將導致其電特 98223.doc 200537691 性上的差異。 除了有關多晶矽TFT特性之不均勻性的問題之外，已知 電致發光顯示元件還會遭遇老化效應。例如，「燒機（burn_ in)」係因陣列中特定像素的延長操作所造成，而且儘管均 以相同的#唬驅動’卻仍會在像素之間導致不均勻的輸出 強度。 為了校正像素輸出中的不均句十生，已知會在個別像素電 路的各像素電路中併入光感測器。各光感測器可用來測量 =個別像素的光輸A，且在像素電路巾的連接方式可以補 b上述的不均句性問題。上述範例請參考w〇_〇1/2〇59i， 二内谷在此以提及的方式併入本文中。圖丨顯示採用所述 光回饋機構的範例像素電路。應明白，像素電路係為相同 電路陣列内數百個之_。各像素係定義於-組資料導體2 之一及一組選擇導體4之一的交點處。導體2、4各組的各 個依彼此實質上正交的方向延伸橫跨支撐基板上。電源線 6可提t、電机給電致發光顯示元件8，此電流則由驅動電晶 體10加以η周變。像素電路進一步包含光感測器12以測量或 偵測顯示元件8的光輸出，及用以按照所測量的光強度調 變、調整流動通過驅動電晶體10的電流。 曰光感測器、，如ΡΙΝ二極體，以非晶矽形成的較佳於以多 :矽形成的’目為非晶矽的光吸收比可見光範圍的部分高 :干數Ϊ級。#晶矽光感測器因此可在相關的校正電路中 提供較高的信號對雜訊比。 土於上述原因，向品質主動矩陣電致發光顯示裝置中的 98223.doc 200537691 各像素電路較佳包含多晶矽TFT及非晶矽光感測器。圖2顯 示截取自圖1之TFT10及光感測器12之像素電路之部分的截 面圖。所示的TFT 10是具有含相鄰摻雜多晶矽源極及汲極 〔（1 6及1 7)之多晶碎通道15的頂部閘極型。可將這歧源極 及汲極區摻雜成n型或p型。然而，通常會在相同的基板上 形成η型及ρ型TFT。閘極絕緣層18可分開通道15和金屬閘 極20。 在圖案化閘極2〇後，還可以使用相同的金屬層定義光感 測器接觸22。然後可在光感測器接觸22上形成堆疊， 以提供垂直非晶矽PIN二極體12。此堆疊包含一層η型非晶 夕24 層較尽的本質非晶石夕25、及一層ρ型非晶石夕26。 這些層係連續沉積，然後再經圖案化成島。 然後在非晶矽堆疊之上，以透明導電材料，如氧化銦錫 (ΙΤΟ)，形成頂部二極體接觸28。這可讓覆蓋之電致發光 顯示元件（未顯示）的光線1〇〇通到光感測器的本質矽。 有關形成η-ι-ρ堆疊的一個明顯問題是在沉積程序期間摻 雜Ρ型層26的難度。摻雜一般係藉由氣相摻雜來執行。為 了執行氣相摻雜必須使用專用的設備及氣體，以避免沉積 室中不想要的污染。還有，所需的氣體，如Β2η6，被歸類 為特別危險的處理氣體，因此為了健康及安全等考量，從 工作場所移除此種氣體的壓力漸增。這對具有含多晶矽 TFT之非日日日砍光感測器之主動矩陣電致發光顯示裝置的大 ϊ製造造成極大的障礙。 US-5,589,694揭露—種其中在基板上形成咖及薄膜二 98223.doc 200537691 桎體(TFD)的半導體裝置。沉積及圖案化200537691 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to an active matrix Chen De device such as an active matrix electro-optic mouthpiece, a light beam, and a stateless person. The integration of light sensors in pixels n and pixel circuits is particularly relevant to the manufacture of such devices, especially for active matrix pixel devices that include (Ren Fei special) thin-film transistors containing and right-crystal silicon channels. -[Prior art] Active matrix electroluminescence display devices using light-emitting display elements are well known. Display elements include: organic thin film electroluminescence elements, such as using polymer materials; or light emitting diodes (LEDs) that additionally use semiconductor compounds. Recent developments in organic electroluminescent materials (especially polymer materials :) have demonstrated their ability to be practically used in video display devices. Suitable materials generally include one or more layers of semi-conductive polymer polymers sandwiched between a pair of electrodes. One of the electrodes is transparent and the other is a material suitable for injecting holes or electrons into the polymer layer. An active matrix electroluminescent display device generally includes a column and a row array of pixels. An individual pixel circuit, which typically includes a thin film transistor (TFT), controls the supply of current to the display elements of each pixel. In each pixel circuit, at least one of what is commonly referred to as a "driving transistor" is used to adjust the current through the display element. It is important that the electrical characteristics of the driving transistor are stable throughout the operation of the display. Amorphous silicon channel TFTs are known to encounter problems such as constant voltage drift when used to control continuous current. Therefore, TFTs with polycrystalline silicon channels are superior to amorphous silicon TFTs in the use of driving transistors. However, TFTs Differences in the structure of polycrystalline silicon channels will result in differences in their electrical characteristics. 98223.doc 200537691. In addition to the issues related to the non-uniformity of polycrystalline silicon TFT characteristics, known electroluminescent display elements also experience aging effects. For example, " "Burn_in" is caused by the extended operation of specific pixels in the array, and even though they are all driven with the same #bluff, it will still cause uneven output intensity between pixels. In order to correct unevenness in pixel output, it is known to incorporate a light sensor in each pixel circuit of an individual pixel circuit. Each light sensor can be used to measure the light input A of an individual pixel, and the connection method in the pixel circuit towel can make up for the above-mentioned uneven sentence problem. For the above examples, please refer to w〇_〇1 / 2〇59i, Erinu Valley is incorporated herein by reference. Figure 丨 shows an exemplary pixel circuit using the light feedback mechanism. It should be understood that the pixel circuits are hundreds of pixels within the same circuit array. Each pixel is defined at the intersection of one of the set of data conductors 2 and one of the set of selection conductors 4. Each of the groups of conductors 2 and 4 extends across the support substrate in a direction substantially orthogonal to each other. The power line 6 can lift t and the motor gives the electroluminescence display element 8, and this current is cycled by the driving transistor 10. The pixel circuit further includes a light sensor 12 to measure or detect the light output of the display element 8 and to adjust and adjust the current flowing through the driving transistor 10 according to the measured light intensity. That is, light sensors, such as PIN diodes, are better formed with amorphous silicon than polycrystalline silicon, and the light absorption of the amorphous silicon is higher than that in the visible light range: a few orders of magnitude. The #Silicon light sensor can therefore provide a higher signal-to-noise ratio in the associated correction circuit. For the above reasons, each pixel circuit of 98223.doc 200537691 in a high-quality active matrix electroluminescent display device preferably includes a polycrystalline silicon TFT and an amorphous silicon light sensor. FIG. 2 shows a cross-sectional view of a portion of a pixel circuit taken from the TFT 10 and the light sensor 12 of FIG. The TFT 10 shown is a top gate type having a polycrystalline broken channel 15 containing adjacently doped polycrystalline silicon sources and drains [(16 and 17). The source and drain regions can be doped to n-type or p-type. However, n-type and p-type TFTs are usually formed on the same substrate. The gate insulating layer 18 may separate the channel 15 and the metal gate 20. After patterning the gate 20, the same metal layer can also be used to define the light sensor contact 22. A stack may then be formed on the photo sensor contacts 22 to provide a vertical amorphous silicon PIN diode 12. This stack includes a layer of n-type amorphous silicon, 24 layers of essentially amorphous stone, and a layer of p-type amorphous stone, 26. These layers are deposited successively and then patterned into islands. A top conductive diode 28 is then formed on top of the amorphous silicon stack with a transparent conductive material, such as indium tin oxide (ITO). This allows the light from the covered electroluminescent display element (not shown) to pass through to the intrinsic silicon of the light sensor. An obvious problem with forming η-ι-ρ stacks is the difficulty of doping the P-type layer 26 during the deposition process. Doping is generally performed by gas phase doping. To perform vapor phase doping, special equipment and gases must be used to avoid unwanted contamination in the deposition chamber. Also, the required gas, such as B2η6, is classified as a particularly hazardous process gas, so for health and safety considerations, the pressure to remove this gas from the workplace is increasing. This poses a significant obstacle to the manufacture of active matrix electroluminescent display devices with non-day-to-day light-sensors containing polycrystalline silicon TFTs. US-5,589,694 discloses a semiconductor device in which a substrate and a thin film are formed on a substrate. 98223.doc 200537691 TDF. Deposition and patterning
广提供分開的半導體島。採用電聚換雜;:為各 及TFD島中摻雜n J在TFT 構。有關依此方式二二的形成具有平面結 所 化成咖的一個問題是，二極體的非晶 貝區必須經得起處理多晶矽TFT島時的高溫。在非曰 石夕和要加熱的電晶體堆疊緊鄰時，要保護非晶梦不合受^ 熱度的損壞相當困難。us_5,589,694之配置的另一個問題 疋’必須為個別電晶體及二極體定義一連串分開的島。 【發明内容】 根據本發明的-個方面提供—種用於製造—主動矩陣像 素裝置的方法’該裝置包含：—包括—多晶料道及換雜 源極/汲極區的薄膜電晶體；及一包括為一非晶矽本質區 所分開之一p型摻雜區及一n型摻雜區的piN二極體；該方 法包括以下步驟： (a) -在一基板上形成複數個多晶矽島，其中之一提供電 晶體通道及源極/汲極區；及 (b) -沉積及圖案化一層非晶矽，以提供該piN二極體的本 質區’致使該本質區覆蓋及接觸提供該p型或η型摻雜區之 一之該等多晶矽島之一之至少一部分。在處理多晶矽島之 後藉由沉積非晶矽，該非晶矽便不會受到有壞之熱處理的 影響’藉此得以製造較高品質的ΡΙΝ二極體。 源極/沒極區及ΡΙΝ二極體之ρ型或η型摻雜區中之該一個 較佳以相同的多晶矽島提供。這有利於不用形成分開的摻 雜接觸，藉此減少處理步驟數，因而可以節省生產成本。 98223.doc 200537691 根據本發明的繁-古 据 弟—方心供—種主動轉像素裝置，該 衣置包各：複數個以一基板所支樓的多晶石夕島，該等島之 -提供-薄膜電晶體的—通道及摻雜源極以極區 Γ一步包含— PIN二極體，該二極體包括以—非晶石夕本 貝區分開的-P型摻雜區及一 η型摻雜區；其中該本質區覆 盍及接觸提供·型或η型摻雜區之—之該等多晶石夕島之一 之至夕分。ΡΙΝ二極體的非晶石夕本質區覆蓋推雜η型及 Ρ型區以在其間提供㈣。這使❹晶⑪摻雜 非晶矽之前先行處理。 ^ 在本發明的—項較佳具體實施例中，PIN二極體具有橫 向結構，其巾PIN二極體的？型及η型捧雜區係由該等多晶 矽島中的個別多晶石夕島來提供。這些島可和電晶體共用， 致使摻雜PIN:極體區之—或二者可和電晶體的源極/沒極 區共用多晶矽島。最好可利用p型及n型薄膜電晶體的摻雜 區，以提供PIN二極體的兩個摻雜區，藉此進一步減少程 序步驟數。在一個基板上同時有n型及p型薄膜電晶體係屬 平常。因此，獲得薄臈PIN光二極體的所需要額外處理步 驟非常少。此外，還可提供透明導電閘極，該閘極可覆蓋 其間以絕緣層分開之PIN二極體的本質區。該閘極最好用 來對PIN光—極體的本質區施加電壓，以控制打型及p型摻 雜區之間的導電，實際上提供閘控的ρΐΝ二極體。 在本發明的另一項較佳具體實施例中’ PIN光二極體具 有其中層壓η型、本質非晶矽、及p型層的垂直結構，其中 摻雜接觸之一係由在基板上形成的多晶矽島之一提供。例 98223.doc 200537691 如，將電晶體的源極/汲極區換雜為—，及製造方法進— 步包含以下步驟： (c)->儿積及圖案化一層鋁，以在該piN二極體的本質區上 定義一頂部PIN二極體接觸； ⑷-退火該頂部PIN二極體接冑，使銘離子㈣至底下的 本質區，以形成該P型摻雜區。藉由採用鋁作為摻雜物源 極，便不必在此種垂直結構中使用氣相摻雜以提供P摻雜 接觸。這有利於避免使用氣相摻雜的相關危險，藉此使此 形成P型區的程序比已知方法更加便宜及安全。 例如，為了使顯示元件的光線能夠到達二極體的本質部 分，可以使用已知的蝕刻技術蝕刻移除頂部光二極體接觸 的一部分。 根據本發明之主動矩陣像素裝置的範例應用係為採用光 回饋的主動矩陣電致發光顯示裝置，其中光二極體用以測 量關連之顯示元件的光強度輸出及供應信號以驅動和其連 接的電路，以按照所測量的光強度調變光輸出。 【實施方式】 本發明人發現，可在沉積PIN二極體堆疊之本質區所需 的非晶矽之前，先形成薄膜電晶體（TFT)所需的多晶石夕 島。因此’該非晶矽並不會受到形成多晶矽島所需之高溫 的影響。本發人進一步發現，可以採用多晶矽的TFT換雜 源極及汲極接觸區以在非晶矽光感測器中形成摻雜區的至 少之一。依此方式共享摻雜區，便不需要提供光感測器分 開的摻雜區。現在將說明在TFT及光感測器間共享至少一 98223.doc -10- 200537691 摻雜區的範例結構。 圖3顯示配置在基板14上的兩個TFT，1(^及10b ,其各具 有多晶矽通道區，15a及15b。第一TFT l〇a具有n型摻雜源 極及汲極區，16a及17a。第二電晶體l〇b具有ρ型摻雜源極 及汲極區。為了簡單明瞭之故，此處並未顯示個別金屬源 極及汲極接觸。 疋義各TFT之通道、源極及;;及極區的多晶石夕島係依已知 的方式形成。例如，在基板上沉積一層非晶矽，然後利用 離子植入選擇性摻雜源極及汲極區。其後，將多晶石夕層圖 案化成島，然後利用如雷射退火形成結晶。熟習本技術者 應明白，此形成島的方法有各種變化。例如，已知在圖案 化步驟之前使矽層形成結晶。 主動矩陣陣列通常在基板上包含成千上萬個Τρτ。然 而’為了簡單明瞭之故，圖3中只顯示兩個。根據本發明 的第一具體實施例，可使用TFT 10a的η型摻雜汲極區i7a 及相鄰TFT的P型摻雜源極區i6b定義非晶矽光感測器12的 摻雜接觸。因此，不需要圖2之光感測器之分開的摻雜 區。應明白，用於此用途的相鄰TFT屬於相反的導電率類 型，即，一個η型與一個ρ型。 為了和:供光感測器12的本質區，會在基板之上沉積一層 本質非晶矽，然後將其圖案化成位在個別對之相鄰TFT之 間的個別島。各島可覆蓋及接觸一個TFT之η型摻雜區及另 一個TFT的ρ型摻雜區的一部分。 因此’可在基板上定義可當作光感測器的piN二極體， 98223.doc 11 200537691 而：需要專用的氣相摻雜設備。此方法對於製造併入光感 、L的主動矩陣電致發光顯示|置，有利於提供簡單又便 宜的途徑。 以第—具體實施例的方法所形成的配置，如圖3所示， 八己3毛、向PIN—極體12，可提供優於如圖2之垂直配置的 声疋梭‘』首先，此垂直配置需要使用相對較厚的多晶矽 層如0.25-1.50 ，方能確保反向洩漏電流屬於夠低 的數值’讓裝置能夠有效操作。提供具有此厚度的一層相 對較難且非常耗時。相反地，圖3中光感測器之摻雜接觸 區間的距離等於相鄰TFT間的間隙。此時，可因使用較薄 的本質層而維持理想低位準的反向茂漏電流。此本質層最 好只藉由沉積及圖案化加以形成。 然後，在基板之上沉積如Si〇2的閘極絕緣層18。然後， 在基板之上沉積如鋁的金屬層及加以圖案化以定義各TFT 的閘極20a、20b。然後，在n_i_p二極體的本質區之上以相 同的方式形成透明導電閘極30。這在操作期間可用來對二 極體施加電壓，以在某種程度上控制摻雜接觸間的導電。 例如，相鄰絕緣體的電荷可在通道中累積，然後影響關閉 電流。對閘極30施加的偏壓電壓有利於減少關閉電流。閘 極必須透明以讓顯示元件的光線1〇〇從中通過。 應明白，光感測器上的閘極30為可有可無的特徵，不需 要時可予以省去，而不會偏離共用摻雜區所提供的優點。 參考圖4及5,使用η型區之一多晶矽TFT的摻雜區‘，即 可提供垂直n-i-p堆疊。p型區的形成係藉由在本質非晶矽 98223.doc -12- 200537691 島上沉積鋁及退火，使鋁能夠擴散 c政至非晶矽中，藉此將苴 摻雜為P型。然後圖案化鋁以露出 、 路出底下的P型區。現在說明 根據此第二具體實施例之光感洌器的製造。 以和上述具體實施例的相同方式，在基板14上藉由沉 積、圖案化及退火多晶石夕層而形成多晶石夕島。在退火非晶 石夕之前，以離子植入定義n型源極16及沒極㈣。然後曰，曰 在基板之上沉積絕緣層以提供閉極絕緣層18。然後，在通 道15之上形成金屬閘極2〇。然後 便在整個基板之上沉積鈍 化層35」後在鈍化層中開啟接觸窗以曝露η型汲極區 17。然後’在基板之上沉積一層本質非晶石夕及加以圖案化 以定義配置在η型汲極區I?之邱八 匕外分上的島25,，如圖4所示。Canton offers separate semiconductor islands. Adopting electropolymerization to replace impurities; doping n J in each and TFD islands in the TFT structure. One problem with the formation of planar crystals in this way is that the amorphous shell region of the diode must be able to withstand the high temperatures when processing polycrystalline silicon TFT islands. When Fei Shixi and the transistor stack to be heated are in close proximity, it is very difficult to protect the amorphous dream from heat damage. Another problem with the configuration of us_5,589,694 疋 ’must define a series of separate islands for individual transistors and diodes. [Summary] According to one aspect of the present invention, a method for manufacturing an active matrix pixel device is provided. The device includes:-a thin film transistor including a polycrystalline channel and a source / drain exchange region; And a piN diode including a p-type doped region and an n-type doped region separated by an amorphous silicon essential region; the method includes the following steps: (a)-forming a plurality of polycrystalline silicon on a substrate Islands, one of which provides the transistor channel and source / drain region; and (b)-deposits and patterns a layer of amorphous silicon to provide the essential region of the piN diode, so that the essential region covers and contacts provide At least a portion of one of the polycrystalline silicon islands of one of the p-type or n-type doped regions. After processing the polycrystalline silicon island, by depositing the amorphous silicon, the amorphous silicon is not affected by the bad heat treatment ', thereby making it possible to manufacture a higher quality PIN diode. One of the p / type or n-type doped regions of the source / dead region and the PIN diode is preferably provided as the same polycrystalline silicon island. This facilitates the elimination of separate doping contacts, thereby reducing the number of processing steps and thus saving production costs. 98223.doc 200537691 According to the present invention, an ancient-to-familiar-square-heart-feed-type active-to-pixel conversion device is provided, each of which includes: a plurality of polycrystalline stone islands supported by a substrate, such islands- The -channel and doped source electrode of the -thin film transistor are comprised of a PIN diode in one step. The PIN diode includes a -P-type doped region and an η separated by an amorphous stone. Type doped region; wherein the essential region covers and contacts one of the polycrystalline stones, which is provided by a type-type or n-type doped region. The amorphous regions of the PIN diodes cover the doped n-type and p-type regions to provide ytterbium therebetween. This allows the crystalline silicon to be doped before the amorphous silicon is doped. ^ In a preferred embodiment of the present invention, the PIN diode has a horizontal structure. Type and n-type doping regions are provided by individual polycrystalline stones in these polycrystalline silicon islands. These islands can be shared with the transistor, so that the doped PIN: polar body region—or both can share the polysilicon island with the source / dead region of the transistor. It is preferable to use the doped regions of the p-type and n-type thin film transistors to provide two doped regions of the PIN diode, thereby further reducing the number of program steps. It is common to have both n-type and p-type thin film transistor systems on one substrate. Therefore, very few additional processing steps are required to obtain a thin chirped PIN photodiode. In addition, a transparent conductive gate can be provided, which can cover the essential area of the PIN diode separated by an insulating layer therebetween. This gate is best used to apply voltage to the intrinsic region of the PIN photo-polar body to control the conduction between the doped and p-type doped regions, in fact to provide a gated ρΐN diode. In another preferred embodiment of the present invention, the 'PIN photodiode has a vertical structure in which n-type, essentially amorphous silicon, and p-type layers are laminated, wherein one of the doped contacts is formed on a substrate Provided by one of the polycrystalline silicon islands. Example 98223.doc 200537691 For example, the source / drain region of the transistor is replaced with-, and the manufacturing method further includes the following steps: (c)-> accumulating and patterning a layer of aluminum in the piN A top PIN diode contact is defined on the essential region of the diode; ⑷-annealing the top PIN diode is connected to make the ions to the bottom essential region to form the P-type doped region. By using aluminum as the dopant source, it is not necessary to use gas-phase doping in such vertical structures to provide P-doped contacts. This helps to avoid the dangers associated with the use of gas phase doping, thereby making this procedure of forming P-type regions cheaper and safer than known methods. For example, in order for the light from the display element to reach the essential portion of the diode, a portion of the top photodiode contact can be removed by etching using known etching techniques. An example application of an active matrix pixel device according to the present invention is an active matrix electroluminescence display device using light feedback, in which a photodiode is used to measure the light intensity output of an associated display element and supply a signal to drive a connected circuit To adjust the light output according to the measured light intensity. [Embodiment] The present inventors have discovered that before depositing the amorphous silicon required for the essential region of the PIN diode stack, a polycrystalline silicon island required for a thin film transistor (TFT) can be formed. Therefore, 'the amorphous silicon is not affected by the high temperature required to form a polycrystalline silicon island. The author further found that polycrystalline silicon TFTs can be used to replace the source and drain contact regions to form at least one of the doped regions in an amorphous silicon photo sensor. Sharing the doped regions in this manner eliminates the need to provide separate doped regions for the photo sensor. An example structure in which at least one 98223.doc -10- 200537691 doped region is shared between the TFT and the light sensor will now be described. FIG. 3 shows two TFTs 1A and 10B disposed on the substrate 14, each of which has a polycrystalline silicon channel region, 15a and 15b. The first TFT 10a has an n-type doped source and drain region, 16a and 17a. The second transistor 10b has a p-type doped source and drain region. For simplicity and clarity, individual metal source and drain contacts are not shown here. The channels and sources of each TFT are defined. And ;; and the polycrystalline stone island system of the polar region is formed in a known manner. For example, a layer of amorphous silicon is deposited on a substrate, and then the source and drain regions are selectively doped by ion implantation. Thereafter, The polycrystalline stone layer is patterned into islands, and crystals are formed using, for example, laser annealing. Those skilled in the art will appreciate that there are various variations in this method of forming islands. For example, it is known to crystallize a silicon layer before the patterning step. Active matrix arrays typically include thousands of Tρτ on the substrate. However, 'for simplicity and clarity, only two are shown in Figure 3. According to the first embodiment of the present invention, n-type doping of the TFT 10a can be used The amorphous silicon light is defined by the drain region i7a and the P-type doped source region i6b of the adjacent TFT The doped contact of the sensor 12. Therefore, a separate doped region of the photo sensor of FIG. 2 is not needed. It should be understood that the adjacent TFTs used for this purpose are of the opposite conductivity type, that is, an n-type And a p-type. For the sake of: the essential region of the light sensor 12, a layer of essentially amorphous silicon will be deposited on the substrate, and then patterned into individual islands between adjacent pairs of TFTs. The island can cover and contact the n-type doped region of one TFT and a portion of the p-type doped region of another TFT. Therefore, a piN diode that can be used as a light sensor can be defined on a substrate, 98223.doc 11 200537691 And: Special gas phase doping equipment is needed. This method is useful for manufacturing a simple and cheap way to manufacture active matrix electroluminescence display incorporating light sensor and L. The method of the first embodiment The resulting configuration, as shown in Fig. 3, has eight hairs, three hairs, and a PIN-pole body 12, which can provide an acoustic shuttle that is better than the vertical configuration shown in Fig. 2. First, this vertical configuration requires the use of relatively thick polycrystalline silicon Layers such as 0.25-1.50 to ensure that the reverse leakage current is sufficient The value of 'allows the device to operate efficiently. Providing a layer with this thickness is relatively difficult and time-consuming. In contrast, the distance of the doped contact interval of the photo sensor in Figure 3 is equal to the gap between adjacent TFTs. At this time It is possible to maintain the ideal low level of reverse leakage current due to the use of a thinner intrinsic layer. This essential layer is preferably formed only by deposition and patterning. Then, a gate such as Si02 is deposited on the substrate Insulating layer 18. Then, a metal layer such as aluminum is deposited on the substrate and patterned to define the gates 20a, 20b of each TFT. Then, a transparent conductive layer is formed in the same manner over the essential region of the n_i_p diode Gate 30. This can be used to apply a voltage to the diode during operation to control to some extent the conduction between the doped contacts. For example, the charge of an adjacent insulator can build up in the channel and then affect the turn-off current. The bias voltage applied to the gate 30 is beneficial to reduce the off current. The gate must be transparent to allow light from the display element to pass through it. It should be understood that the gate 30 on the light sensor is an optional feature and can be omitted when not needed without deviating from the advantages provided by the common doped region. 4 and 5, using a doped region of a polycrystalline silicon TFT, one of the n-type regions, provides a vertical n-i-p stack. The p-type region is formed by depositing aluminum and annealing on the island of essentially amorphous silicon 98223.doc -12- 200537691 to allow aluminum to diffuse into the amorphous silicon, thereby doping erbium into a p-type. The aluminum is then patterned to expose the P-type region underneath. The manufacturing of a photo sensor according to this second embodiment will now be described. In the same manner as the specific embodiment described above, a polycrystalline stone island is formed on the substrate 14 by depositing, patterning, and annealing a polycrystalline stone layer. Before annealing the amorphous stone, the n-type source 16 and the non-polar region were defined by ion implantation. Then, an insulating layer is deposited on the substrate to provide a closed-electrode insulating layer 18. Then, a metal gate 20 is formed over the channel 15. A passivation layer 35 "is then deposited over the entire substrate, and a contact window is opened in the passivation layer to expose the n-type drain region 17. Then, a layer of substantially amorphous stone is deposited on the substrate and patterned to define an island 25 arranged on the Qiu Baji of the n-type drain region I ?, as shown in FIG.
此島可提供垂直光域>Ρ«! ώΑ -4- jaA 尤以涮裔的主體。通道係形成於鈍化層 中以和TFT底下的源極區j 6及沒極區^ 7接觸。 然後沉積及圖案化—層銘以^義源極接觸36與汲極接觸 3 7、及頂部光感測器接觸 ^ 牧啁應明白，為此用途可以使用 銘口金取代然後，例如，藉由加熱至擔。c持續⑼分 1 Ρ可k火頂光感測器接觸4〇。此退火程序造成铭離 子擴散至底下的本暂I ^ ς, 貝島25 ’將一區域摻雜為ρ型。此外， 退火使摻雜ρ型區的$小 ^ 、 L的至J 一部分形成結晶以加強摻雜效 應。 參考圖5，之德士 a 糟由餘刻移除鋁頂部光感測器接觸40的 部分’以曝露Ρ型區26夕5 b之頂部表面的部分。這可將PIN堆疊 曝露於發射自覆叢夕％ 一 蓋^纟、員不元件的光線100之下。 依此方法，不帛g 4 乳相摻雜物即可形成高效率的P型接觸 98223.doc 200537691 26 ° 在本發明的第二具體實施例中（未顯示），pIN二極體的 非晶矽本質區可覆蓋以絕緣層和其電絕緣的閘極。這可對 一極體提供光線遮蔽以防止遠離TFT之基板側的周圍光線 造成光電流。此種配置在用於電致發光顯示器的光回饋電 路日守尤其有利，因為不要的周圍光線可精確測量關連之顯 示元件的輸出光強度。 應明白，藉由不會形成TFT之部分的多晶矽島可提供 PIN二極體的11型及型摻雜接觸，且不會偏離本發明的 本質。 總而言之，本發明揭示一種主動矩陣像素裝置，如電致 f光顯示裝置，該裳置包含以基板所支撐的電路及包括多 曰曰矽TFT與非晶矽薄膜PIN二極體。在沉積piN二極體的多 曰:曰：層之前，會先形成多晶矽島。這可避免非晶矽曝露於 同/皿處理中。丁FT包含摻雜源極/汲極區，其中之一亦可提 供用於一極體的n型或p型摻雜區。最好不需要提供光二極 ^ 開的摻雜區，藉此節省處理成本。具有相反導電率 類型之摻雜源極/汲極區的第二爪可提供用於二極體的另 多雜區’其中本質區係橫向配置於兩個π丁之， 覆蓋個別多晶矽島的各多晶矽島。 :本揭露内容中，熟習本技術者應明白許多其他的修改 色此種修改及變化可涉及本技術中已知的其他特 並可用來取代或附加於此處已經揭露的特色。應明 白’本申請案之揭露内容的範嘴包括任何及每個本文所揭 98223.doc -14- 200537691 露的新穎特色或特色的組合，無論其為明示或暗示，以及 連同所有此種修改及變化，無論是否有關此處已經揭露的 主要么明概心，及無論其是否如主要發明概念可解決任何 或所有的相同技術問題。甲請人並藉此聲明，在執行本申 請案或任何從其申請優先權衍生的進一步申請案期間，可 根據此類功能及/或此類功能的組合，擬定專利案主 專利範圍。 ％ 【圖式簡單說明】 讀完僅舉例提供的較佳具體實施例說明及參考附圖，即 可明白本發明的這些及其他特色及優點，圖式中： 圖1顯示具有已知電路組件之配置之主動料電致發光 顯示裝置的像素電路； 圖2為通過圖1所示之像素電路之部分的截面圖； 圖3為通過具有本發明第— 弟具體貫轭例之光感測器之傻 素電路之部分的截面圖；及 之 圖4及5為通過具有本發- Θ弟一具體貫轭例之光感測器 像素電路之部分的截面圖。 整份附圖中，相同的參 f數予代表相同或相似的零件。 應明白，圖式僅為略圖， 並未依比例繪製。特別是，某些 尺寸已放大，而其他則已縮小。 【主要元件符號說明】 資料導體 選擇導體 電源線 98223.doc 200537691 8 電致發光顯示元件 10 驅動電晶體 10a、1 Ob 電晶體 12 光感測器（圖1) 12 垂直非晶矽PIN二極體（圖2) 12 橫向PIN二極體（圖3) 14 基板 15 多晶矽通道 15a 、 15b 多晶矽通道區 16 、 16a 源極區 17 、 17a >及極區 18 閘極絕緣層 20、20a、20b 閘極 22 光感測器接觸 24 η型非晶矽 25 本質非晶碎 25f 島 26 ρ型非晶碎 28 頂部二極體接觸 30 透明導電閘極 35 鈍化層 36 源極接觸 37 沒極接觸 40 頂部光感測器接觸 100 光線 98223.doc -16-This island can provide vertical light field > Ρ «! ΏΑ -4- jaA, especially the main body of the Wa people. The channel system is formed in the passivation layer to contact the source region j 6 and the non-electrode region ^ 7 under the TFT. Then deposit and pattern—the layer is connected with the source contact 36 and the drain contact 37, and the top photo sensor is contacted ^ It should be understood that for this purpose you can use inscription gold and then, for example, by heating To the burden. c Continue to scoring 1 PK can fire the light sensor contact 40. This annealing process causes the ions to diffuse to the bottom of the current I ^ ς, Bay Island 25 ′ doped a region into a p-type. In addition, the annealing forms crystals in a portion of $ S ^ to L of the doped p-type region to enhance the doping effect. Referring to FIG. 5, the taxi a removes the portion of the aluminum top photo sensor contact 40 'in the remaining time to expose the portion of the top surface of the P-type region 26x5b. This may expose the PIN stack to light 100 that is emitted from the cover and the device. According to this method, a highly efficient P-type contact can be formed without 帛 g 4 milk phase dopant. 98223.doc 200537691 26 ° In a second specific embodiment of the present invention (not shown), the pIN diode is amorphous The intrinsic silicon region may be covered with an insulating layer and its electrically insulating gate. This can provide light shielding to a polar body to prevent photocurrent caused by ambient light far from the substrate side of the TFT. Such a configuration is particularly advantageous in a light-feedback circuit day guard for an electroluminescence display, because the unnecessary ambient light can accurately measure the output light intensity of an associated display element. It should be understood that 11-type and type doped contacts of PIN diodes can be provided by polycrystalline silicon islands that do not form part of the TFT without departing from the essence of the invention. In summary, the present invention discloses an active matrix pixel device, such as an electro-optical f-light display device, which includes a circuit supported by a substrate and includes a silicon TFT and an amorphous silicon thin film PIN diode. Before depositing piN diodes, polycrystalline silicon islands will form first. This prevents the exposure of amorphous silicon to the same process. T-FT includes doped source / drain regions, one of which can also provide n-type or p-type doped regions for a pole body. It is desirable not to provide a photodiode-doped region, thereby saving processing costs. A second claw with a doped source / drain region of the opposite conductivity type can provide another hetero region for the diode, where the essential region is laterally arranged at two π-d, covering each of the polycrystalline silicon islands. Polycrystalline silicon island. : In this disclosure, those skilled in the art should understand many other modifications. Such modifications and changes may involve other features known in the art and may be used in place of or in addition to the features disclosed herein. It should be understood that the scope of the disclosure of this application includes any and every novel feature or combination of features disclosed in 98223.doc -14- 200537691, whether explicit or implicit, and together with all such modifications and Changes, regardless of whether the subject has been disclosed here or not, and whether they can solve any or all of the same technical problems as the main inventive concept. Party A hereby declares that during the execution of this application or any further application derived from its priority application, the scope of the patentee's patent may be drawn up based on such functions and / or combinations of such functions. [Brief description of the drawings] After reading the description of the preferred embodiments provided by way of example only and referring to the accompanying drawings, these and other features and advantages of the present invention will be understood. In the drawings: FIG. The pixel circuit of the active material electroluminescence display device configured; FIG. 2 is a cross-sectional view through a portion of the pixel circuit shown in FIG. 1; and FIG. 3 is a view through a light sensor having a first embodiment of the present invention. A cross-sectional view of a portion of a stupid circuit; and FIGS. 4 and 5 are cross-sectional views of a portion of a pixel circuit of a light sensor through a specific example of a yoke. Throughout the drawings, the same reference numbers represent the same or similar parts. It should be understood that the drawings are only sketches and are not drawn to scale. In particular, some dimensions have been enlarged while others have been reduced. [Description of main component symbols] Data conductor selection Conductor power line 98223.doc 200537691 8 Electroluminescent display element 10 Driving transistor 10a, 1 Ob transistor 12 Photo sensor (Figure 1) 12 Vertical amorphous silicon PIN diode (Figure 2) 12 lateral PIN diodes (Figure 3) 14 substrate 15 polycrystalline silicon channel 15a, 15b polycrystalline silicon channel region 16, 16a source region 17, 17a > and pole region 18 gate insulating layer 20, 20a, 20b gate Pole 22 Photo sensor contact 24 η-type amorphous silicon 25 Essential amorphous chip 25f Island 26 ρ-type amorphous chip 28 Top diode contact 30 Transparent conductive gate 35 Passive layer 36 Source contact 37 Non-contact 40 Top Light sensor contacts 100 light 98223.doc -16-