TW200536057A - A trench and a trench capacitor and method for forming the same - Google Patents

Abstract

A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. This step is performed in such a way that the topmost layer provided on the trench wall is constructed from a sealing material. A selective epitaxy method is carried out in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate and preferably no semiconductor material grows directly on the sealing material. A partial trench is etched in a surface of the epitaxially grown semiconductor layer. This step is performed in such a way that at least part of the layer made of the sealing material is uncovered. An uncovered part of the layer made of the sealing material is then removed.

Description

200536057 V. Description of the invention (1) --- ~ the technical field to which the invention belongs; the invention and the manufacturing method of the trench, the manufacturing method of the trench capacitor, the manufacturing method of the memory unit, and the trench, and the trench capacitor And related to a memory cell having the trench capacitor. Prior art memory cells of dynamic random access memories (DRAMs) generally include a storage capacitor and a selection transistor. The information stored in the storage power valley expresses logical quantities ^ and ^ in the form of electric charges. The word line drives the read transistor (read — 〇ut transist〇r) or Lu selects the electric wide body ', can store the data stored in the storage capacitor from the bit line (bh 11 ne) . In order to distinguish the reliability between charge storage and data readout, the storage capacitor must have a minimum capacitance value. The current lower limit of the storage capacitor is about 25fF. The memory storage density increases from generation to generation. The area required for a transistor memory cell must be smaller than that of the first generation, while the minimum power requirement of the storage capacitor remains unchanged. For generations up to "bit, both the readout transistor and the storage capacitor are flat = pieces. Starting from the 4Mbit memory generation, memory cells are arranged by the dimension of the storage capacitor to further reduce the area. The storage capacitor in the trench is one Wability. In this example, the diffusion region adjacent to the trench wall and the filled polycrystalline stone filled in the trench serve as the electrodes of the storage capacitor. The electrodes of the storage capacitor are arranged along the surface of the trench, which can be enlarged The effective area of the storage capacitor is related to the valley value of the shirt capacitor and is related to the space requirement of the storage capacitor on the substrate surface. The space requirement is consistent with the cross-sectional area of the trench.

200536057 V. Description of the invention (2) Adding the depth of the trench can be further increased. In the past, many methods have been completed. One is to reduce the storage swell method to amplify the change in the roughness of the trench capacitance to increase the groove inner particle (HSG, advanced hemispherica advanced The method involves relying on consumption, or using metal electrodes to increase the size. In addition, in order to increase the trench to replace the previous nitric oxide dielectric constant dielectric, or metal electrical properties. In addition, in order to produce high aspect ratios, the new technology must be large. The optimization number, for example, the thickness of the individual layer thickness of the hard shield and the trench capacitance by means of energy, voltage, flow, and etching time. For example, the etching rate is reduced. As a result, it is used to etch the block. Area. At the same time, the current technology is 60 to 70. Application Publication No. 1020 2003/0 1 36994 US patent plus package density. Increase the thickness of the storage layer of the trench capacitor. Further internal surface (bottle). This area, for example: coating more grain) Increase the doping to reduce the capacitance and reduce the resistance. The capacitance of the tank capacitor can be used as a capacitor. It may be questionable, especially the metal trenches that need to be developed to obtain the trench structure, that is, the depth and thickness of the stacked hard cover and the etch serviceability, and the optimization of the frequency and bias specific parameters. This material also needs to be optimized. However, it is more and more close to the technical and warp rate and etching selectivity. With the depth-to-width ratio of 1 40 that can be achieved by the hard cover surface of the groove, the German patent and application are described in terms of a single crystal capacitor value. In addition, with the wet chemical expansion, the dielectric value of the k value can be eliminated by the electrons of the coarse-grained silicon hemispherical electrode, which is a temperature-sensitive new material that introduces high dielectric. With the diameter or width of the groove, the etching gas, and the outer 'groove are left for a while. However, the current manufacturing economic limit. The etching depth has been increased, and a large value has been etched. The maximum value is estimated to be disclosed.

P.8 200536057 V. Description of the invention (3)-Selective stupid crystal growth method. German and US patents are incorporated herein by reference. For example, this method can be used to form a trench of a trench capacitor on a silicon substrate, the trench capacitor can only be completed after the high temperature step is performed, and the trench is laterally staggered after each high temperature step is performed. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for generating trenches with a high aspect ratio. It is another object of the present invention to provide a method for generating a high aspect ratio trench capacitor. According to the present invention, the manufacturing of a groove and a groove according to the present invention includes providing a plate with a surface. At the opening The opening The substrate grows in the surface direction, there is a way to remove it. The semiconductor, and preferably the semiconductor wall. To the sealing material, the surface of the layer is covered with a trench method, a conductive material is used to specifically point out, and in addition, a specific material group substrate has one less layer of material to form the sealing material. Finally, one side of the surface is grown on the surface, so that the semiconductor portion is not grown in this way. Another type of plate is formed by half-cutting a trench, which is a half of the surface or filling of the trench embodiment of the present invention. The single material covers the selective grooves, and is composed of the materials used to seal the grooves. In a trench wall, a memory sheet having a specific embodiment of the trench and a capacitor, a trench is used to fabricate a conductor substrate, and the opening is etched to provide a semiconductor method to cover the opening of the semiconductor layer to form a cover. After that, a groove is provided by the record of the uncovered capacitance of the sealing material layer. The method is based on semiconductor etching, the sidewalls and the surface of the semiconductor are transverse, and the topmost part of the epitaxial material layer is formed by providing half of the semiconductor substrate by etching. Available on the trench wall

Page 9 200536057 V. Description of the invention (4) At least one structural layer. This step is performed so that the upper layer provided to the trench is composed of a sealing material. Implementation-Selective stupid crystal method so that: The layer is formed on a -semiconductor substrate and there is no semiconductor material directly on the material. A portion of the trench is etched in an epitaxially grown semiconductor layer. This step is applied so that the sealing material has at least-partly no coverage. The uncovered portion of the sealing material structure layer is then removed. A specific embodiment of the invention provides a method that can be used to create trenches having a particularly high aspect ratio on a semiconductor substrate by means of developed technology. The grooves produced are used in many collars that require particularly high aspect ratio grooves, such as in the field of microelectronics or sensor technology, such as the manufacture of sub-channel systems in liquid or gas fields. The manufacturing and manufacturing method provides a method for manufacturing a trench capacitor, which comprises the aforementioned method steps of trench lifting, and manufacturing steps of providing a bottom capacitor electrode adjacent to a trench wall, a storage dielectric, and an upper capacitor electrode. A small part of the 1 series is located in the middle. a Λ. Therefore, according to a specific embodiment of the present invention, in principle, a capacitor trench is formed on a half-body substrate by a conventional method J, and the capacitor trench is covered by proper cleaning, so that the surface of the trench is not Exposed. In particular, it is provided that the trench wall has at least one structural layer, so that the households provided on the trench wall are composed of a branch sealing material. In the next step, after removing the silver engraved mask of the remaining trenches, a selective crystal method is implemented to epitaxially grow a single crystal silicon layer on the substrate surface. In other words, a smooth, closed epitaxial layer is generated on the surface of the substrate, and the substrate is etched on the substrate. 200536057 V. Description of the invention (5) --- The trenches το are all retained. This is understandable, especially by covering the trench wall in a suitable way. The advantage is that the selective epitaxy method is not covered at the beginning. The selective stupid method is constructed from a non-elemental silicon sealing material. This material is monocrystalline silicon, polycrystalline silicon or amorphous silicon, non-metallic materials, non-so-called compound materials, such as Si Ge or silicide. Furthermore, the staggered crystal method is used to selectively grow the structural layer in the region of the single crystal stone layer. More specifically, a selective epitaxy method typically uses a gas mixture, for example, containing silane or jiiChoroSilane, and an etching gas, such as hydrogen chloride. The _selective epitaxy method uses an etching gas to etch silicon grown on different materials at different speeds. Therefore, in particular, the parameters of the method are set so that the etching rate of the single crystal silicon is smaller than the growth rate of silicon, and thus, the thickness of the entire silicon layer formed on the silicon is increased. For example, in comparison, the polycrystalline silicon seed layer of silicon dioxide (Si02) on the sealing material is etched much larger than that of silicon. As a result, due to the lateral growth of the area covered by the sealing material, silicon only grows on On the single crystal surface region, an epitaxial single crystal silicon layer is formed in the region. The flow rate of dichlorosilyl methane is usually h2 to 丨. 8 times that of hydrogen chloride. Next, a partial trench is formed on the epitaxially grown silicon layer by a conventional method, and the partial trench is connected to a trench formed on a semiconductor substrate. More precisely, the 'm'j part of the groove is such that at least a part of the structural layer composed of the sealing material layer is not covered. Arbitrary weight. It is possible to manufacture trenches of any depth using the above-mentioned method steps. It is possible to manufacture capacitor trenches with high aspect ratios by using techniques that are readily available. Saves development because existing manufacturing methods can be used

Page 11 200536057 V. Description of Invention (6) '--- = Expenses required. In addition, it is possible to reach higher capacitance values without using a temperature-sensitive material, although the method according to the invention includes the use of a temperature-sensitive material. The method according to the invention can be embodied by different modifications. For example, after each etching step of the trench, a bottom capacitor electrode is provided, and the dielectric sound = the trench or part of the trench that is etched by the upper capacitor electrode. Similarly, it is possible to start not filling the trenches, and only provide capacitors and dielectric layers after all trenches are stacked. This slot, or I electrode and surface, I worm layer and upper layer are suitable according to the external conditions. However, it is also possible to complete two trenches and one or one of the trench capacitor electrodes in order to complete the trench. , ,and many more. The other step does not need to connect one or any number of partial trenches to provide capacitance and then lay the next stupid layer on the surface to form a bottom capacitor electrode and continue the dielectric implementation. To be more precise, an example 'must be in the trench The sacrifice material of the stone material that avoids stupid growth can be laid on the groove wall, and it can be removed completely or partially after the groove is completed. Example silicon oxide, which is used in the next field. Dielectric materials are only deposited when trenches are stacked without subsequent epitaxial steps. • High-k dielectric or metal treatment. The structure composed of epitaxial growth in an empty trench is further filled with a layer of sealing material in the trench. For example, the growth of the heat-capacitor electrode wall is then sacrificed. A method, which can be implemented in the trench, and the material can be packaged in the step. If one is provided, under this load, it is possible to introduce any capacitor in the trench stack or a highly doped trench region containing a doped trench electrode. Or in one child there is a temperature sensitive material, such as

Page 12 200536057

The trench sidewalls of the trenches of the semiconductor substrate may be provided. The thickness of the epitaxial growth layer is preferably smaller than the depth of the etching trench. This provides the advantage of targeting the etched epitaxial growth layer. 9 Weishi =: Divided grooves and grips are smaller than the lower part of the groove diameter. The advanced elements of the memory unit are compatible with the epitaxial layer on the top. Especially the choice of the contact point of the transistor and bit line. . Therefore, a valley is formed = small space requirement and high capacitance value. ^ ΐ Ϊ is the material of the bottom capacitor electrode or the upper capacitor electrode and the dielectric layer: the material of the 'especially' capacitor electrode may be highly doped: the barrier layer is made of an insulating layer, and the insulating layer is configured Between the base ΐ i Γ ί and is interrupted-often in the lower area one by one = for contact with the metal layer. In particular, the stone oxide layer consists of a high melting point metal and a material having the same melting point, which is suitable as a material for a metal electrode. To the right of the mouth is a monolithic oxide / nitrified mineral oxide) stacked layer or ^ service stone, 3 silica, alumina (Al203), tin oxide (Ti02), emulsified ^ (Τ% 〇). 5) or other high-k dielectrics. Lin layer mother doping: dt layer can be doped ’, which is different from the junction below. It can be determined from b # 用 麻 ί 2 electrical properties. In addition, in each part of the trench, there are two materials different from the fΐ electrode, the upper capacitor electrode, and the storage dielectric; 〃, the material of the part of the groove or the bottom capacitor electrode. Capacitive dielectric body! In the embodiment, a trench capacitor having a capacitor electrode at the bottom and a capacitor electrode at the top of the capacitor is at least partially disposed in a capacitor.

200536057 V. Description of the invention (8) The bottom capacitor electrode in the trench is adjacent to a trench wall, and the trench has a minimum diameter and a depth, and the ratio of the depth to the diameter is greater than 70, especially greater than 80, and particularly preferably greater than or equal to 85. A specific embodiment of the present invention provides a trench capacitor with a high aspect ratio to provide a trench capacitor with a high storage capacitance value with a particularly small space requirement. In the plan view, the capacitor trench is generally oval rather than circular. . In other words, there are two diameters along two different cross-sectional directions. If the trench etched on the semiconductor substrate has the same diameter as all the trenches, the minimum diameter is equivalent to the minimum diameter or the minimum width of all the trenches. Conversely, if the diameter of the uppermost groove in at least one direction is smaller than the diameter of the groove below it, the smallest diameter is equivalent to the smallest diameter of the uppermost groove. . From the perspective of step f, the present invention provides a half-conducting substrate including a first substrate portion composed of an early-earth conductor material, and a second substrate portion composed of the single crystal half: body :: bucket: The second substrate portion is defined; and most of the grooves extend in a direction perpendicular to the surface of the substrate, and the grooves are formed on the fourth substrate portion. The thickness of the second substrate portion of the lateral door is in the range of _nm to 1000nm, and is mainly in the range of 8000 to 1500nm. Mode of implementation However, I ί: = 明 ί Manufacture and use of preferred embodiments of the invention. Township, m 彳 b & I 2 2 The present invention provides many applicable inventive concepts that can be used under ^ A ^ ^ ^ applications. The specific embodiments of the present invention are only for the purpose of making and using the present invention, but not limiting the scope of the invention.

Page 14 200536057 V. Description of Invention (9). According to a first specific embodiment of the present invention, a trench capacitor having a total depth of about 8 # is defined by a one-step process and two mask steps to define the trench capacitor. ^, An example A, after each trench is etched, a bottom capacitor electrode and a dielectric capacitor and an upper capacitor electrode are directly provided. However, obviously, according to the present invention, the ears are first engraved with grooves of all depths, and then the bottom capacitor electrode, the storage capacitor dielectric, and the upper capacitor electrode are manufactured by a well-known method. -According to the first figure, the surface i of the semiconductor substrate 2 is a two-emulsion silicon layer 3 with a thickness of 3 nm, a nitride layer 4 with a thickness of 220 nm (for example, silicon nitride), and a borophosphosilicate glass layer with a thickness of 62 nm. (Not shown in the figure). The specific thicknesses shown here are for example only, other thicknesses may be used. Use a lithographic mask (not shown in the figure) to nitrify the borophosphosilicate glass layer. For example, further use a trench wall 3 in the trench 5 1 For example, by using a sulfur two layer / tf silicon dioxide layer 3 A pattern is defined, for example: methane / trifluorosulfonate (CHFa) plasma etching to form a hard shield. Use the hard cover as described above. At first, the insect cover is engraved in the main area. 1 The insect is engraved with a groove 5 ′ hydrogen / three gas nitrogen (HBr / NF3) plasma plasma. There is no cover. Thereafter, the borophosphosilicate glass layer is removed by a wet etching method of acid / hydrofluoric acid (HJfVHF): H ′ trench 5 has a depth of 6.6 ⑽, a width of about 100 to 250 nm, and a trench ’pitch of 110 nm. The structure shown in Fig. 1 is thus produced. In the next step, an n + doped region 6 is used to manufacture the bottom capacitor electrode :. 'As shown in Fig. 2, it is a step of 10,000 degrees Celsius heat for one second, a layer of arsenic-doped silicate glass with a thickness of 50 nm, and a thickness of 〇Pe silicate glass. 20nm tetraethoxysilane

200536057 V. Description of the invention (10) A silicon oxide (TEOS-Si 02) layer is used. In this example, the doped region 6 of the capacitive electrode 6a, which is the bottom of an independent capacitor in the completed memory cell configuration / arrangement, is directed by a fragmented doped silicate glass layer on the semiconductor substrate Outer diffusion is formed. One-phase gas doping method is another option, for example, the parameters are as follows: 900 ° C, 3 Torr 1 ^ person (1: 1: 1 ^ 1) 111 ^ 1 &]: magic 1 ^) [33%], 12 minute. 3. Remove the arsenic-doped silicate glass layer and the TEOS_SiO2 layer. For example, recheck the use of ammonium / hydrofluoric acid etching steps that are selective for silicon nitride and silicon. ^ Nitrile oxide and a thickness of i.5nm bis. 5 layers: for the dielectric layer 7. Another method 'dielectric layer 7 comprises alumina, = acoustic: chemical button or other conventional dielectric materials. Next, an erbium-doped polycrystalline silicon layer 8 is used as an upper capacitor electrode in the same-position. The structure as shown in Figure 2 is therefore 吝 &. + Secretary After grinding (⑽) for planarization, the spar spar layer 8 uses chemical machinery. According to the drawing, the polycrystalline spar filling 8 is from the surface 1 of the semiconductor substrate 2 to the mouth and 10 n m. For example, to carry out this step with "tired foreign visits, e p, h, such as Fan 4 IS1 Zhang-, chaos & (SF6) etching. It is on the trench filling surface. For example, this can be charged by 7 = 2. In this example t, the thickness of the sealing layer 9 is about ^ n, m milk = ^ used up = degree of electric lion) method, and the deposition of dioxide: the second layer can be used; After that, the hard cover is removed by a conventional method, and the structure shown in FIG. 5 is generated. After the remainder of the drought 4 ', as shown in Fig. 6, a selective method for growing a thick-yield 5-day-day-day method on the substrate surface 1 is, for example, a layer of 5 ⑽ long presparite. For example, the worm crystal method can

Page 16 200536057 V. Description of the invention (11) It can be a chemical vapor deposition (CVD) method, using a temperature of 90 ° C and a flow rate of 1 8 0 sccm (per cubic centimeter per minute under standard conditions). Shi Xijia roasted with thorium chloride at a temperature of 900 degrees Celsius and a flow of 60 seem. In this example, an epitaxial cavity 10 is formed in the center of each sealing layer 9. In particular, it can be seen from FIG. 6 that a semiconductor substrate includes a first substrate portion 2 composed of a single crystal semiconductor material, and a second substrate portion 11 composed of a single crystal semiconductor material. The second substrate portion is The epitaxial layer is exposed on the first portion, and a surface of the second substrate portion defines a substrate surface; most of the trenches 5 extend in a direction perpendicular to the surface of the substrate and extend in the first substrate portion. 2 forms the trench 5. In particular, the thickness of the second substrate portion may be between 600 nm and 3 / zm, and is mainly between 800 nm and ΐ · 5 // m. Next, a pattern is defined in an epitaxial deposition of a silicon layer by a conventional method, and a groove is etched, which is adjacent to the groove engraved by the previous money. As shown in FIG. 7, first a silicon dioxide layer 3 with a thickness of 3 ηι and a silicon nitride layer 4 with a thickness of 2211111 are laid on the surface of the selective growth epitaxial layer again. A borophosphosilicate glass layer 12 of 6200 nm is laid thereon. After that, a photoresist layer j 3 is applied according to a conventional method. A mask for defining the first groove pattern is also used as the light of the photoresist layer. However, a mask with a smaller opening can also be used. The 5 t alignment of the lower trench structure is preferably performed by a special alignment mask. After the pattern is defined by the lithography of the hard mask layer and the photoresist layer 13 is removed, then, the t-reactive ion etching RIE trench etching transfers the trench mask onto the epitaxial layer Y and is completed from below. The etching of the sealing layer 9 of the trench 5 stops. Relatively; the oxidized Xi Shi Xi was selectively carved by I insects, as shown in Figure 8 for structural reasons

Page 17 200536057 丨 丨 ―_ 丨 · 丨 V. Invention description (12). After that, the sealing layer 9 is removed using dilute hydrofluoric acid (DHF), resulting in the structure shown in FIG. 9. Thereafter, a bottom capacitor electrode and a storage dielectric are formed on the etched portion of the trench in a manner similar to that described in FIG. 2. However, in general, during the formation of the bottom capacitor and the pole, in order to avoid the doping of part of the trench, it is necessary to take into account the coverage of the ## trench region, which has a relatively late insulation ring formation. Dielectric; ::? Second, it is feasible to generate the bottom capacitor electrode and stray electric current by other conventional methods. After that, as shown in FIG. 10, a spacer material " Example ^ Silicon (without crystalline silicon) has a conformal deposition thickness of about 15 to 20 nm. The bottom ΪΠ5Γ ′ is used to remove the gate dielectric layer 7 of the bottom portion of the trench 5 by a reactive ion etching method. When the reactive ion etching is removed, the dielectric layer 7 located on the vertical trench wall is followed by 14 =. In the removal of selective wet etching, '^ ^ 15f' ^ ^ A ^ ^, the dielectric screen 7 knows the tape ~ Γ electric electrode 6, but in this example but "the groove V capacitor = the groove transistor has Superimposed and connected to the storage: electricity j m: storage capacitor structure of the memory cell and link this step element: manufacturing: described below. Appeared. Obviously 'according to the invention can also be completed: sexual talent' Early concept of realization of the trench Page 18 200536057 V. Description of the invention (13) Slot capacitance. Acoustic 16 under 1 η 〇 The figure shows the next step, polycrystalline stone filling 8 times # to the dielectric layer on the side wall of the epitaxial tank The conventional method is used to engraving the thickness of the trench that is not covered by the thickness of 25 ⑽. After the depth of U, the conformal deposition is formed on the upper part of the trench. Parasitic transistor ^ insulating ring. The dioxide dioxide insulating ring 17 is used to develop at this position. Capacitor trench i. Two 1 ^ miscellaneous polycrystalline silicon layers to fill the storage area in the annular area. Select the + i silicon layer to etch back to about 1 20nm below the epitaxial layer 11 to prepare for ^ embedding. The structure as shown in Figure 13 is thus generated. The buried area 17f is removed from the buried cover. After depositing the η-doped polycrystalline silicon, the planarization is performed again after the nitriding process of ^ %% / area. As described above, Y is wrong and θ is polished by chemical mechanical Fang ,. "Early polycrystalline stone layer from the surface of the worm crystal layer 11 down 16 π about 40nm. (Recess etching) spear surface 16 back down to the insulating structure 1 8 laterally defined active The boundary of the area r: Two shadow masks (not shown in the figure) can cover the active area. The depth at which the second name is engraved is related to the depth of the trench insulation Λ;! On it. Emulsification of the evening sun-thermal silica Thin layer, 2. Deposited by the density plasma method to a thickness of 250 nm. I: Using a LI machine ;: Grinding a layer of nitrided stone. 4. Carving of a stone with a linoleic acid release nitrogen button.

Page 19 .200536057 V. Description of the invention (14) And move: f: more barrier layer, namely nitride stone layer 4 and dioxide layer 3. ^ Then, by a sacrificial oxide layer and a shielding oxide (SCreen 3 'IT). N-doped wells and P-doped's are formed by lithographic masks and implants. The crystal is implanted with an initial voltage (into V0Uage). Furthermore, high-energy ion implantation ($ = MUried Weil — ImPlantn) is implemented to form an n-doped region 15 connected to the bottom capacitor electrode. Closing the rabbit The transistor is then focused on the connection and source / dimer 22 by conventionally known method steps. Next, remember the second-and complete it by forming a metal flat plate in a known manner. Figure 14 shows the outline of the memory unit. The trench capacitor 28 and the bottom capacitor electrode a, the storage dielectric 7 and the upper capacitor electrode 8 are arranged in each trench 5, Ϊ: embodied by polycrystalline silicon filling. The upper capacitor electrode 8 is connected to the first source / drain of the selection transistor 29 through a polycrystalline silicon region 20 and a buckle. At 2,: I: The conductivity of the conductive channel between the drain and ⑽ is the idle electrode. Figure 15 is an example of the design of the 8 F2 cell architecture of the memory unit. The configuration of the memory unit is as follows: The early element'-storage capacitor is arranged in the trench 5 and a plane selection transistor% responds to the space requirement of Z, and f is the smallest feature size 1 that can be manufactured in this technical field. The bit line (BL) is band-shaped and parallel to each other. The width is F, and the vertical line of the word line (WL) is shown in the plan view. Similarly, the width is F and the interval is F. The active area is arranged below the character line and the bit line, and the two character lines cross the active area. Adjacent to each bit below the bit line

.200536057 V. Description of the invention (15) A = quantity. -The bit line contact point (BLK) is arranged at the active = there is an electrical connection between each bit line and the active area A. : The slot 5 is arranged below the word line. The main ^ ^ 舻 舻 9 K 9 1 cognition ^ movement & A among the formation of the associated selection circuit B 电 body gate 21 at the intersection of a word line and _ bit line. The active area A is extended between the two grooves 5, after the 1-bit line contact point is connected to the associated bit = the two fine lines are determined by a common moving character line, from the groove 5: On the last day, '* The storage capacitor reads out information. I. Slot 5-or other storage of trench 5: the second embodiment of the present invention-to make a trench capacitor and "; for this purpose, the bottom capacitor trench factory is defined, Day]! Two to four cat-crystal growth-silicon layer method four times. Then you can use epitaxial method whenever necessary according to demand. In this F; fe I describe the second ' In a specific embodiment, firstly, the lower four trenches are fabricated; the bottom is fabricated; the capacitor electrode 26 is formed to form a dielectric layer 7, and is manufactured on the side of: a clever layer. A fourth telecrystalline layer 25 is then laid on the sealing layer. The part of the trench 5 formed by the layer 25 has a smaller size than the lower trench region. The second advantage is that the capacitance area can be greatly reduced. The capacitance value is not maintained. The method can be described in the first embodiment, and the trench capacitor shown in tH6 is covered with the trench wall 31 made of the trench in the same way as in FIG. 1. However, the trench depth is 5 · # m ' I degree 200nm, pitch 60nm. After the trench is cleaned, a cover layer 27 is formed on the trench wall by thermal oxidation. Especially, for example, the thickness is 12nm. The cover layer 27 is used as Of selective epitaxy

.200536057 V. Description of the invention (16) Compliance layer to prevent fragmentary crystal growth on the inner wall of the trench. In addition, the cover layer 27 is also used as the termination of the capacitor trench of the upper stupid layer 11 later. The structure shown in Figure 17 is thus generated. After the covering layer 27 is laid, the hard cover is removed, and the system includes the silicon dioxide layer 3 and the silicon nitride layer 4 which are the same as those in the first embodiment, and are implemented in the same manner as in the first embodiment to generate a monocrystalline stone. Selective stupid method. In particular, a chemical vapor deposition method was used to generate a silicon layer with a thickness of 4 · 3 # m. The temperature was 900 ° C and the flow rate was 180 sccm of dichlorosilane. The temperature was 900 ° C and the flow rate was 60 sccm of hydrogen chloride. ° _ The epitaxial layer 11 grows laterally on the open trench 5, and the trench is completely retained as a cavity. More specifically, a single crystal layer is formed on an unfilled trench. The structure shown in Figure 18 is thus generated. In particular, as shown in FIG. 18, a semiconductor substrate is provided, which includes a first semiconductor substrate portion 2 composed of a single crystal semiconductor and a second semiconductor substrate portion composed of the single crystal semiconductor. . The second substrate portion deposited on the first portion is an epitaxial layer, and the surface of the substrate is defined by the surface of the second portion; and a plurality of grooves 5 extend in a direction perpendicular to the substrate. A trench is formed in the first substrate portion 2. Next, a pattern is defined for the epitaxial growth layer 11, which is similar to that described above. In particular, the silicon dioxide layer 3, the silicon nitride layer 4, and the borophosphosilicate glass layer 12 are once again laid as a hard cover. A photoresist layer 3 is applied and properly aligned, and then exposed with a trench mask. After the hard cover is defined, the structure as shown in Figure 9 is generated. As shown in FIG. 20, the epitaxial layer is etched out by a reactive ion etching method.

Page 22 200536057 V. Description of the invention (17) Trench 'The etching is terminated by the cover layer 27 of the capacitor trench below. The cover layer 27 is removed using, for example, dilute hydrofluoric acid to produce a structure as shown in FIG. 21. After that, a new cover layer 27 covers and forms the entire trench wall 31. After the remaining hard shields 3 and 4 are removed, a selective epitaxial layer 2 3 with a thickness of 4 · 3 e m is formed on the epitaxial layer 11 again using the chemical vapor deposition method. The second remote crystal layer 23 also defines a pattern in the foregoing manner, and the epitaxial layer ^ and the epitaxial layer 23 and the trenches on the silicon substrate 2 have the same diameter. After the pattern of the capacitor trench hard shield is defined, the pattern as shown in Fig. 22 is generated. In the foregoing manner, a part of the trench is etched on the second epitaxial layer. The cover layer 27 is removed and deposited again over the entire trench. The shield is removed and a third parasitic crystal layer 24 is formed, and the selective parasitic method is completed. The structure shown in Fig. 23 is thus produced. A hard cover including a silicon dioxide layer 3, a silicon nitride layer 4, and a borophosphorus glass layer 12 is used. A photoresistive sound is applied by the photolithography step used in the previous study. And use the pattern of the first stone hard cover. Part of the trench was etched on the second μ-day layer in the aforementioned manner. . Then, connect Λ / ν to define the bottom capacitance electrode 6, the storage dielectric 7, and the top capacitance electrode. By example & it can be listed that the Vth bottom capacitance electrode is formed by the n-doped region 6 again. An arsenic-implanted silicate glass is deposited thereon according to one embodiment. One-phase J-layers 11, 23, and 24 are another method. For example, the parameters are as described on page 23, 200536057. 5. Description of the invention (18): 90 ° C, 3 Torr TBA (tributylarsine) [33%] , 12 minutes. After one slice, a silicon nitride layer with a thickness of 4.7 nm and a silicon oxide layer with a thickness of 5 nm were deposited as the dielectric layer 7, and then a polycrystalline silicon oxide with a thickness of 3,000 nm was deposited at the same position. As in the first specific embodiment, chemically mechanical polishing is used to planarize the deposited spar crystal layer 8 and engraved to about 1011111 below the surface of the third epitaxial layer. The formation of a silicon dioxide starting layer and a sealing layer 9 'with a thickness of 12 nm to 15 mm by a thermal process or a high-density plasma process is similar to the first embodiment. Because the grooves carved in the fourth epitaxial layer 25 are smaller in width than the previous grooves, the sealing layer 9 can also ensure continuous insulation of the two capacitor electrodes 6, 8 in this example. Figure 24 is the final structure diagram. It can be seen that the worm crystal layer 25 deposited about 4 · 3, a selective epitaxy method is completed again. As shown in FIG. 24, similar to the first embodiment, the epitaxial layer 25 is defined by a silicon dioxide layer 3, a nitride layer 4, and a borophosphosilicate glass layer 2 as a hard shield. Then, the photoresist layer 13 is coated and exposed using a trench mask. The opening of the trench mask defined by the last pattern is preferably smaller than before. It can reduce the space requirement of the memory cell, and obtain a high storage capacitor capacitance value and a high conductivity above the Λ pole 8. As shown in FIG. 25, a capacitor trench is etched in the fourth epitaxial layer 25 by a method similar to that described in FIGS. 8 and 12. The area not covered by the sealing layer 9 is removed, that is, the area exposed by using the 14-groove portion 30 of the trench 30. After that, use the

200536057 V. Description of the invention (19) The second method of forming the groove on the top of the upper groove area is the capacitor, and it is customary to consider the dispersion.系 Each line can be properly protected to avoid spreading after installation. 'According to the conventional method, it is inserted into the upper trench area, and the interval sound is equal to 1 electrical layer 7. After forming a spacer layer 14, the entire position is on the same place. . After removing the spacer layer, the thickness is about 30nm. As shown in FIG. 26, the polycrystalline silicon layer 8 is filled with 1, and the thickness Η ~ ν and σ are not high, so that peaks are generated. An advanced element similar to the first embodiment is provided for the memory unit. Method, where a trench capacitor is formed and as shown in Figures 26 and 27+, 4 is called from. The cross-sectional area is higher than that of the upper trench area. The body substrate 2 of the trench area below the trench capacitor, the worm crystal layer U, and the lower trench area bordered by the semi-conductor are described above. Before the coincidence, the bottom capacitor electrode 6a is used to form the fourth cat-crystal layer, # μ # A & dielectric 7 and the upper capacitor electrode 8 are formed in the trench below, in a non-shrinking manner. Fill up =; Γ ^ ^ τ „^ ^ Wt 帛: Another variation of the j-body embodiment. Of course, the fourth groove can also be etched to 25. The valley trench is etched to the same cross-sectional area. In this example In the following, the bottom capacitor electrode 6 and the upper capacitor electrode 8 are defined after the pattern of the fourth epitaxial layer 25 is defined. In this example, the material of the capacitor electrode and the dielectric material cannot be used. A high thermal load is advantageous.-Especially by way of example, a silicide layer with a doped layer under it can be used.

Page 25 200536057 V. Description of the invention (20) is the bottom capacitor electrode. A suitable silicide layer is a metal silicide layer, for example, a refractory metal silicide layer is connected to the substrate through a lower doped layer. The lower doped layer is formed in a similar manner to the foregoing. y Furthermore, a stack including a metal layer and a barrier layer can also be used. In this example, the barrier layer includes an insulating layer, especially silicon dioxide, which is directly on the trench wall and in order to make electrical contact with the metal layer above it, the lower area is open. Metal hafnium includes titanium nitride, scale, H or other refractory f compounds. In particular, the so-called high-k material can be used for storage, especially polycrystalline silicon or other metals, or metals as upper capacitor electrodes. The milk is used as the upper capacitor electrode 8, the electric layer 7, and the bottom capacitor electrode 6a of the dielectric material and the upper Λ material or a combination of the above materials to further increase the capacitance value. As a second specific, another advanced variation method of the embodiment, after the groove 5 is engraved on the rice, the groove may also be suitable for dioxygen cutting in soil. As shown in FIG. 17B, for the simplified process, the groove 3 is partially etched in two steps. After the steps, the generated female ditches are filled with the sacrificial layer 26. The specific embodiment of the present invention is described with reference to the diagram. Different modifications of the embodiments of the present invention and ". 2 or specific embodiments." Including various modifications

200536057 Brief Description of Drawings Figures 1 to 12 are the steps for manufacturing a trench capacitor according to the first embodiment of the present invention. Figure 13 shows the steps for further manufacturing a memory unit. Figure 14 is a schematic cross-sectional view of the basic elements of a completed memory unit in the first embodiment of the present invention. Figure 15 shows the layout of an 8 F2 unit structure. 16 to 26 are steps for manufacturing a trench capacitor according to a second embodiment of the present invention. Fig. 27 is a schematic cross-sectional view of > basic elements of a completed memory unit in the second embodiment of the present invention. Description of main component symbols: A Active area BL bit line BLK bit line contact point 1 surface 3 silicon dioxide layer 5 trench 6a bottom capacitor electrode 8 upper capacitor electrode 1 0 stupid cavity cavity 2 borophosphosilicate glass (BPSG ) Layer 14 spacer 1 6 surface of stupid layer 1 8 insulation structure 2 0 polycrystalline silicon filler WL word line 2 semiconductor substrate 4 silicon nitride layer 6 n + doped (n + -doped) region 7 dielectric layer 9 sealing Layer 11 selective epitaxial layer 13 photoresist layer 1 5 η + doped region 17 insulating ring 19 doped region 21 gate electrode

Page 27 200536057

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Claims (1)

200536057 A method for manufacturing a trench, the method comprising: providing a semiconductor substrate composed of a semiconductor material, the semiconductor base engraving an opening side wall on the surface of the semiconductor substrate; the opening has a providing at least one layer or a filler, so that The side wall is covered, and the surface formed by the opening is composed of a sealing material; The crystal method makes an early semiconductor layer formed on the surface of the semiconductor substrate. The surface of the opening of the sealing material is laterally grown on a surface of the staggered semiconductor layer and a layer composed of the bifurcation material layer is etched. At least one of the grooves, part of the grooves, so that the part is not covered 2. Remove the layer composed of the sealing material to form the grooves. For example, the method of applying for the item No. 丨 of the patent application uses substantially no semiconductor material to directly cover the uncovered part, thereby completing the selective epitaxy method on the sealing material. 3. ❿ If the scope of application for the patent item No. 丨Method, more people · provide at least one Lushe I 3 on the side wall of a part of the groove; the surface of one of the grooves is formed by a sealing material 丄 M so that the part implements a selective epitaxy method, so that _ 20%; A single crystal layer is formed on the surface, and a crystalline semiconductor layer grows laterally on the surface of the portion of the trench. ™ Covered in Sealing Material 200536057 6. The scope of the patent application: etching a second part of the trench on a surface of the second single crystal semiconductor layer, so that at least a part of the layer composed of the sealing material is not covered; and removing the layer composed of the sealing material No coverage. 4. The method of claim 3, wherein at least a part of the groove or the second part of the groove has a diameter different from the diameter of the other groove or the opening. 5. The method according to item 4 of the patent application, wherein the diameter of the second part of the groove is smaller than the diameter of the part of the groove, or the diameter of the part of the groove is smaller than the diameter of the opening g. 6. The method of claim 1, wherein the single crystal semiconductor layer has a thickness smaller than the depth of the opening etched on the semiconductor substrate. 7. The method of claim 1, wherein the semiconductor substrate comprises single crystal silicon. 8. The method of claim 1, wherein the single crystal semiconductor layer includes single crystal silicon. 9. The method according to item 1 of the patent application, wherein the opening and the part of the groove have the same diameter. _ 0. The method according to item 1 of the patent application, wherein the part of the groove has a diameter different from the diameter of the opening. 11. The method of claim 10, wherein the diameter of the grooves in the portion is smaller than the diameter of the openings. 1 2. If the method of item 1 of the patent application scope, the method further includes: Page 30 200536057 6. The scope of the patent application forms a bottom capacitor electrode adjacent to a wall of the opening; forms a capacitor dielectric adjacent to the bottom capacitor electrode; forms a capacitor electrode adjacent to the capacitor dielectric above, wherein the The bottom capacitor electrode, the capacitor dielectric, and the upper capacitor electrode are at least partially disposed at the opening. 1 3. The method according to item 12 of the patent application scope, wherein at least one structural layer or a filler is provided including the forming a bottom Capacitive electrode. 14. The method according to item 13 of the patent application scope, wherein providing at least one structural layer or filler further comprises providing the capacitor dielectric. 15. The method according to item 14 of the scope of patent application, wherein providing at least one structure > layer or filler further comprises filling the opening with a filling material and covering the filled opening with a structural layer composed of a sealing material. surface. 16. The method according to item 15 of the scope of patent application, wherein the filling material is a material suitable for forming an upper capacitor electrode. 17. The method according to item 12 of the scope of patent application, wherein the step of forming the bottom capacitor electrode, the capacitor dielectric, and the upper capacitor electrode is performed after etching a portion of the trench on the single crystal semiconductor layer. 18. The method of claim 1 wherein providing at least one structural layer or filler includes providing a sacrificial layer. Lu 9. The method according to item 18 of the scope of patent application, wherein the sacrificial layer is doped so that it is suitable for the doping of adjacent semiconductor materials in the downstream heat treatment step. 20. The method according to item 19 of the scope of patent application, further comprising performing doping of adjacent semiconductor materials. Page 31 200536057 6. Scope of Patent Application 21. The method of claim 18, wherein the sacrificial layer contains; silicon oxide. A method for manufacturing a memory cell having a storage capacitor, characterized in that: a trench capacitor and a selection transistor, the method comprising: providing a semiconductor conductive substrate composed of a semiconductor material with a surface; i θ t • side 22. The opening has an opening wall etched on the surface of the semiconductor substrate; or a filler, so that the side wall is covered by it-ϊ; sex ": 生 Health table: composed of-sealing material; a single crystal semiconductor In the above description, the surface of the semiconductor substrate surface forming opening is covered by a horizontal two-long sealing material, and the surface of the semiconductor layer grown on the stupid crystal is formed by the sealing material layer: 丨 -part of the trench So that at least a part of the photographic layer does not remove the junction composed of the sealing material to form a trench; "the uncovered part, the capacitor electrode at the bottom of the trench; The capacitor dielectric of the bottom capacitor electrode forms a capacitor adjacent to the capacitor dielectric—the capacitor electrode, the capacitor dielectric, and the upper f ′, wherein the bottom is disposed at the trench; and the valley electrode At least a part selection transistor is formed having a first - source / no electrode, a first Page 32 200536057 6. Scope of patent application Source / drain, a conductive channel and gate, the upper capacitor electrode is electrically conductively connected to the first source / drain of the selection transistor. 2 3 · The method according to item 22 of the scope of patent application, wherein a selective epitaxy method is implemented so that substantially no semiconductor material is directly grown on the sealing material. 24. A trench formed on a semiconductor body, the trench having a depth and a minimum diameter, and the ratio of the depth to the minimum diameter being greater than 70. Wherein the depth and the minimum, the depth and the minimum, the gully contains a 25. The method according to item 24 of the patent application > The ratio of the diameter is greater than 80. 26. The groove of claim 25, wherein the ratio of the diameters is greater than or equal to 85. , Wherein the bottom capacitor is at least partially disposed in the trench capacitor including a selection transistor, the first and second source- and second source / drain channels above the gate 2 7 The trench capacitor includes a trench capacitor portion, and the trench capacitor further includes: a bottom capacitor electrode adjacent to a wall of the trench; a capacitor dielectric adjacent to the bottom capacitor electrode and a capacitor electrode adjacent to the bottom capacitor electrode; The capacitor dielectric electrode, the capacitor dielectric and the upper capacitor electrode trench. | 8. For example, the groove of the 27th in the scope of patent application, in which the Lu Jiyi unit part, the memory unit further includes a selection transistor having a pole / drain region located on the semiconductor body and a _ pole located on the semiconductor body. One of the conduction channels in the interval, and in the conduction 200536057 6. The scope of the patent application: The first source electrode and the pole region handle are connected to the upper capacitor electrode. Page 34