200535795 玖、發明說明： 【發明所屬之技術領域】 尤指一種用來處理光 本發明提供一種光碟讀回訊號處理電路與方法 碟讀回訊號之輸入取樣電路與方法。 【先前技術】 近年來光儲存技術如CD、_等規格，由於兼 大等優點，已舰誠_麵體顧社流賊。 統於處理由讀詞（pi咖p)所讀敗辆讀阳 ^ 系 時，會利用-類比數位轉換器（咖㈣。 = ADC) (sarapling), 資料值，再請_之她峨歧。 Μ械應之數位 ;、、'、而，當《機的轉速隨著技術的演進_向高倍速的顧時，類比 數位轉換器的取樣頻率亦隨之提高，甚至高達數百ΜΗζ。另外，類比數位 換器對光碟讀回訊號進行轉換時，為了維持一定程度之取樣解析产 Rampling resGlutiQn) ’類比數位轉換騎產生之數位資料的^元數也 :法減少’通常在讀元以上。綜合以上时，類比轉換器將對光碟 機糸統中之晶片大小（die size)與其功率消耗造成負面的影響。 【發明内容】 因此本發明之料目的之—在於提供—細來處理光碟讀回訊號之輸 入取樣電路與方法，能夠使用位元數較少的類比數位轉換器。 依據本發明之實施例，係揭露一種輸入取樣電路，用來處理一光碟讀回 訊號，該輸入取樣電路包含有一自動增益控制單元，用來調整該光碟讀回 200535795 訊號之增益；-低通濾波/等化n，雛至該自動增益控制單元，用來對 該光碟讀回減進行低通濾波/等化處理，以纽—輪出訊號；以及一類 比數位轉換H，祕至該低通濾波/等化H，絲對該輪出訊號進行類比 數位轉換’以產生一數位STI號；其中該類比數位轉換器係於一實質上較該 輸出訊號之動態範圍為小的轉換範圍中，對該輸出訊號進行類比數位轉換Λ。 依據本發明之實_ m錄人取樣方法，用來處理—光碟讀回訊 號，該輸入取樣方法包含有調整該光碟讀回訊號之增益；低通渡波/等化 遺光碟5胃回祕以產生-輸出1峨；以及於__實質上小於該輸出訊號之動 態範圍的轉換範圍中，對該輸出訊號進行類比數位轉換，以將該輸出訊號 轉換為該數位訊號。 ~ 【實施方式】 請參考圖-’圖-為本發明之部份輸入取樣電路100的第一實施例示 意圖。圖-中之輸人取樣電路⑽制來處理經由光碟機系統中之讀寫頭 所讀回之-捕讀回赠DRB，以魅-紐峨L雜電路剛 係包含有-轉換電路110 ’其中包含有一自動增益控制單元（aut〇_gain control unit)112、一低通濾波/等化器（1〇w__⑴㈣呢/印祕細 umt) 114、以及一低解析度類比數位轉換器（1〇wres〇luti〇nADc) ιΐ6。 於本實施例中之自動增益控鮮元112、低猶波/等化^ 114、及類比數 位轉換ϋ 116之實施方讀為熟f辆m簡倾者職泛悉知， 故無需於此詳細描述。 〃 ^ 睛參閱圖二，圖二為依據本發明-實施例之輸入取樣方法的流程圖。 ，注意，接下來於說關二中之方法時，係關—中之輸人取樣電路為例 來進行說明，而以下步驟之順序並非本發明之限制： 步驟910 :以自動增益控制單元112調整光碟讀回訊號麵之增益值； 步驟912 : α低通濾波/等化器114·碟讀回訊號廳進行^通渡波/ 200535795 #化動作（low-pass filtering/equalizing)，以產生一輪出 訊號SI 1 ;以及 步驟914 ·利用低解析度類比數位轉換器116,於一實質上較輸出訊號Sli 之動態範圍DR為小的轉換範圍邙中，對輸出訊號sil進行類 比數位轉換’以將輸出訊號S11轉換為數位訊號D1。 一關於上述步‘914中類比數位轉換之動作，請參閱圖三，圖三中係顯 不圖-中之低解析度類比數位轉換器116之輸入訊號_c」n (亦即圖— 中之低通濾波/等化器114之輸出訊號sn)的眼狀圖（eyediagram)。目艮 狀成原理及代表意義係為熟習此項技術者所廣泛悉知，故不贊述。 術者應可理解，圖三中所示之眼㈣係於光碟讀回訊號_ 914 ^ 圍DR為小的轉換範圍(即訊號贈C」n)之動態範 訊號su之位準大於轉換範圍= 出訊號su進行類比數位轉換。當輸出 廡於n? HR夕&轉換圍的上限CRJB時，將數位訊號D1設為對200535795 (1) Description of the invention: [Technical field to which the invention belongs] Especially a method for processing light The present invention provides an input sampling circuit and method for processing a read-back signal of an optical disc. [Previous technology] In recent years, optical storage technologies such as CD, _, and other specifications have been adopted due to their advantages. When dealing with the unsuccessful reading of the reading system by the reading word (pi coffee p), the system will use the-analog digital converter (㈣. = ADC) (sarapling), the data value, and then please __ her Eqi. The digits of the MEMS machine should be; ,, ', and when the speed of the machine changes with the evolution of the technology to the high speed, the sampling frequency of the analog digital converter will also increase, even up to hundreds of ΜΗζ. In addition, when the analog digital converter converts the read-back signal of the optical disc, in order to maintain a certain degree of sampling and analysis, Rampling resGlutiQn) is used to generate digital data generated by the analog digital conversion. To sum up, the analog converter will have a negative impact on the die size and power consumption of the optical disc drive system. [Summary of the Invention] Therefore, the object of the present invention is to provide an input sampling circuit and method for processing the read-back signal of an optical disc, which can use an analog-to-digital converter with a small number of bits. According to an embodiment of the present invention, an input sampling circuit is disclosed for processing an optical disc read-back signal. The input sampling circuit includes an automatic gain control unit for adjusting the gain of the optical disc read-back 200535795 signal;-low-pass filtering / Equalization n, to the automatic gain control unit, used to perform low-pass filtering / equalization processing on the read-reduction of the disc to output signals in New Zealand-wheels; and an analog digital conversion H, secret to the low-pass filtering / Equivalent H, the wire performs an analog-to-digital conversion on the output signal to generate a digital STI signal; wherein the analog-to-digital converter is in a conversion range that is substantially smaller than the dynamic range of the output signal. The output signal is analog-to-digital converted Λ. According to the actual method of the present invention, the m-recording sampling method is used to process the read-back signal of the optical disc. The input sampling method includes adjusting the gain of the read-back signal of the optical disc; -Output 1 angstrom; and perform analog digital conversion on the output signal in a conversion range that is substantially smaller than the dynamic range of the output signal to convert the output signal into the digital signal. [Embodiment] Please refer to FIG .- 'FIG.- This is a schematic diagram of a first embodiment of the input sampling circuit 100 according to the present invention. The input sampling circuit in the figure is made to process the DRB read back by the read-write head in the optical disc drive system. The charm-Neuer L hybrid circuit just contains the conversion circuit 110 'which contains There is an automatic gain control unit (aut〇_gain control unit) 112, a low-pass filter / equalizer (1〇w__⑴㈣ 呢 / 印 密 细 umt) 114, and a low-resolution analog-to-digital converter (10Wres). luti〇nADc) ιΐ6. In this embodiment, the implementation of the automatic gain control unit 112, low wave / equalization ^ 114, and analog digital conversion ϋ 116 are read as familiar to everyone, so there is no need to detail here description. 〃 ^ Please refer to FIG. 2, which is a flowchart of an input sampling method according to an embodiment of the present invention. Note that the next step is to explain the method of Guanzhongzhong with the input sampling circuit of Guanzhongzhong as an example, and the order of the following steps is not a limitation of the present invention: Step 910: Adjusted by the automatic gain control unit 112 Gain value of the signal readback surface of the optical disc; Step 912: α low-pass filter / equalizer 114 · Disc readback signal hall performs ^ 通 渡 波 / 200535795 # low-pass filtering / equalizing to generate a round of output signal SI 1; and step 914. Use the low-resolution analog-to-digital converter 116 to perform an analog-to-digital conversion on the output signal sil in a conversion range that is substantially smaller than the dynamic range DR of the output signal Sli to output the signal. S11 is converted into digital signal D1. For the action of analog-to-digital conversion in the above step '914, please refer to Figure 3. Figure 3 shows the input signal _c "n of the low-resolution analog-to-digital converter 116 in (-)- An eyediagram of the output signal sn) of the low-pass filter / equalizer 114. Mugen formation principle and representative meaning are widely known by those familiar with this technology, so they are not praised. The surgeon should understand that the eye shown in Figure 3 is based on the read-back signal of the disc _ 914 ^ The dynamic range of the signal su, whose DR is a small conversion range (that is, the signal gives C "n) is greater than the conversion range = The signal su performs analog-to-digital conversion. When the output 庑 is lower than the upper limit CRJB of the switching range, the digital signal D1 is set to
^0^^ CR 之位準處於脑r円πρ 的數位值。也就是說當輸出訊號犯 SH (saturate! ；^f 116 換範圍CR約為動態範圍DR的_半 D1+°如圖三所示’由於轉 使用較少之位元數。 ^低解析度類比數位轉換器116可 116 請參閱圖四’圖四中顯示圖一 之輸入訊MADC—in的另一眼狀 ^低％析度類比數位轉換器… 示之眼狀目係於觸讀㈣號DRB^，、自此徽術者射轉，圖四中所 轉換範圍CR，甚至可為動態非=靖生所得到。圖四中所示之 轉換器116可使用甚至更少之位-]一刀之一，因此低解析度類比數位 計，對應地減少晶片尺寸與辨^。’崎—步簡化類比數轉換器的設 10 200535795 ，為本發明之輸人取樣電路測的第二實施例示意圖。 样带θ之弟貫施例所不的轉換電路11G之外，第二實施例之輸入取 水电路200 3包含有一直流調整模組12〇，而直流調整模組1 卿吻叫譲如請⑴124，用來 Λ 、 所輪出之數位讯唬D1，產生一補償訊號S AC2，以透過一 對低通遽波/等化器114之輸出訊號S11的直流位準進^整 5 ne«w, sn ;、隹ί為—般光碟機系、统中十分普遍眺L編碼之數值，例如按昭 :===:據==; 位準:ΓΓ遞本實施例’直流調整模組120調整輸出訊號su之直流 的上^ ιιβ、Ξ。如則所述’由於當輸出訊號幻1之位準大於轉換範圍CR 值^而訊號D1設為對應於_之數健（即最高階數 i w輸出减S11之位準小於轉換範圍CR的下限CRJLB時，則將 =ufl#u D1設為對應於CR—LB的數健（即最健數值丨 ===次數M⑻較最低階數值而的出現次_)為多: 二θ 某一^界值時）’表示輸出訊號S11之直流位準偏高，應予 ^日f f皆it011的出現次數Μ(8)較最低階數值101的出現植 ⑴為夕日寺’表不輸出訊號S11之直流位準偏低，應予升高。 除了 六為本發明之輸入取樣電路300的第三實施例示意圖。The level of ^ 0 ^^ CR is at the digital value of the brain r 円 πρ. In other words, when the output signal commits SH (saturate !; ^ f 116, the change range CR is approximately _half D1 + ° of the dynamic range DR, as shown in Figure 3, 'because fewer bits are used for conversion. ^ Low-resolution analog digital The converter 116 can be 116. Please refer to Fig. 4 '. Fig. 4 shows another eye shape of the input signal MADC_in in Fig. ^ Low% resolution analog digital converter ... The eye shape shown is based on the reading of DRB ^, Since then, the magician has shot, and the range CR shown in Figure 4 can even be obtained by dynamic non- = Jing Sheng. The converter 116 shown in Figure 4 can use even fewer positions-] one of the knife, so Low-resolution analog digital meter, correspondingly reduce the chip size and discrimination. 'Saki-step simplified analog-to-digital converter setting 10 200535795, which is a schematic diagram of the second embodiment of the input sampling circuit test of the present invention. In addition to the conversion circuit 11G not described in the example, the input water fetching circuit 200 3 of the second embodiment includes a DC adjustment module 12 0, and the DC adjustment module 1 is called 譲 ⑴ 124, which is used for Λ, The rotated digital signal bluffs D1 to generate a compensation signal S AC2 to pass a The DC level of the output signal S11 of the low-pass oscillating / equalizing device 114 is adjusted to 5 ne «w, sn;, the general optical disc drive system, the L code value is very common in the system, for example, according to Zhao : ===: According to ==; Level: ΓΓ In this embodiment, the 'DC adjustment module 120 adjusts the DC of the output signal su ^ ι β, Ξ. As described above, because when the output signal magic 1 level Greater than the conversion range CR value ^ and the signal D1 is set to correspond to the number of _ (that is, the highest order iw output minus S11 is less than the lower limit CRJLB of the conversion range CR, then = ufl # u D1 is set to correspond to CR —The number health of LB (that is, the most robust value 丨 === number of times M⑻ appears more frequently than the lowest order value_): more than two θ at a certain ^ threshold) 'indicates that the DC level of the output signal S11 is too high, It should be noted that the number of occurrences M (8) of it011 is lower than the appearance of the lowest order value 101. The planting level is low, and the DC level of the output signal S11 is lower, and it should be increased. A schematic diagram of a third embodiment of the input sampling circuit 300.
笛了 t圖五之弟—貫施例所示的轉換電路110及直流調整模組跏之外， 弟二貫施例之輸入取樣電路300另包含有一辩M 1^32 130 ^ AGc'um!) ㈣末據數號Dl產生一增益控制訊號S-DAGC3，以控制自動㈣ 工制早π 112調整光碟讀回訊號腦之增益值。為了配合上述操作，= 11 200535795 知例中之自動ia i控制單元112係為-類比自動增益控制單元，其係為熟 ，此項技術者所2泛悉知，故林述。於本實施射，數位自動增益控制 早π 132係依據珂述各個數位值於特定時間内出現的次數_ a (亦即該 2值之出現鮮）來魅增益控概msj)AGC3，以· DRB之增益值。 描2以下說明依據本實施例，增麵整模組13G調整光碟讀回訊號廳之 值的#作原理。同樣地，由於轉析度類比數位轉換㈣6的飽和處 $特性’則當最高階數值011與最低階數值出現次㈣⑻、m⑴比 ^它階數值_、謝、咖 '議、ln、與m的出現次數m(7:2)為多時 列$其間差異超過某一臨界值時），表示輸出訊號sii之動態範謂過 予減v ’於疋數位自動增益控制單元132會減少光碟讀回訊號讎 ^值。而當最高階數值on與最低階數值1〇1的出現次數關、㈣ 匕1階數值議、_、咖、⑽、lu、與11G的出現次數m(7:2)為少 示輸出訊號S11之動態範㈣過小，應予增加，於是數位自動增益 匕制早70 132會增加光碟讀回訊號DRB之增益值。 ^青參閱圖七，圖七為本發明之輸入取樣電路棚的第四實施例示意圖。 二J圖六之第三實施例所示的轉換電路110、直流調整模組120、及增益 ;:10之外，第四實施例之輸入取樣電路侧另包含有一鎖相迴路 一、於本只知例中，鎖相迴路14〇係由一相位/頻率谓測器（卿）⑷、 :路濾波器（LF) 144、-數位類比轉換器（DAC) 146、及一麼控減写 、=)148所構成，以上電路架構及其操作原理均為熟習此項技術者所廣 ίί號供低騎度獅數轉魅116進躲斜職據之取樣 接;若是類比數位轉換11116的取樣頻補高的話，亦可利用耗 轉換器116之後、數位操作之觸取樣電路（―即⑻ 來取代類轉作之壓控振盪器148, _於鱗取樣電路之娜及操作 12 200535795 熟習此項技術者所廣泛悉知，故不在此贅述。 明茶閱圖八’ 11八為本發明之輸碌樣電路5⑽的第五實施例示意圖。 ，了 ^圖二之第二實施例所示的轉換電路⑽及直流調整模組⑽之外， =貝她例，輸入取樣電路5⑼另包含有—時脈產生模組⑽ ，利用一截波 152及—數位鎖相迴路（DPLL) 154，依據輸出訊號su來提 度類比數位轉換器116進行取樣時所依據之取樣時脈訊號⑽。 μ * Λ =中’不對稱補償單元124則是依據截波器152所產生的方波 Li f周訊號su的直流位準。以上所述之電路架構及操作原理均 樣斤廣泛悉知’故不贅述。此外，經由本實施例之輸入取 及:理後所產生之數位訊號D1亦可再透過一 RLL規則違反檢查 則二杳 V10latl0n checking/correc_tic)n unit) 160 進行 rll 規 ；；：^^(statemachine) 170 w * 114Γϋ ί 114之最佳參數，例如低通據波/等化 L立晋轉红式（transferfunction)中零點（zero)或極點（P〇le) 的位：。：上所述之電路架構及操作原理亦為熟習此項技 ^ 118 工早70 2之W值，此亦為熟習此項技術者所廣泛悉知。 均等ΖΙίΓί發明讀龄齡1，驗树日种請專概圍所做之 -、文匕，、L飾，^應屬本發明專利的涵蓋範圍。 【圖式簡單說明】 圖式之簡單說明 圖=為本發明輸入取樣電路的第一實施例示意圖。 圖=為依據本發明-實施例之輸人取樣方法的流程圖。 =三為圖—所示的低解析度類比數位轉換器的轉換範圍的示意圖。 為圖—所示的低解析度類比數位轉換器的轉換制的示意圖。 13 200535795 圖五為本發明輸入取樣電路的第二實施例示意圖。 圖六為本發明輸入取樣電路的第三實施例示意圖。 圖七為本發明輸入取樣電路的第四貫施例不意圖。 圖八為本發明輸入取樣電路的第五實施例示意圖。 圖式之符號說明 112 自動增益控制單元 114 低通濾波/等化器 144 迴路濾波器 122 加法器 152 截波器 124 不對稱補償單元 140 鎖相迴路 100, 200，300，400，500 輸入取樣電路 110 轉換電路 116 低解析度類比數位轉換器 120 直流調整模組 130 增益調整模組 132 數位自動增益控制單元 140 鎖相迴路 142 相位/頻率偵測器 146 數位類比轉換器 148 振盪器 150 時脈產生模組 154 數位鎖相迴路 160 RLL規則違反檢查/修正單元 170 狀態機 14In addition to the conversion circuit 110 and the DC adjustment module shown in the fifth embodiment of the fifth embodiment, the input sampling circuit 300 of the second embodiment also includes a debate M 1 ^ 32 130 ^ AGc'um! ) The last data number D1 generates a gain control signal S-DAGC3 to control the automatic work system early π 112 to adjust the gain value of the disc read back signal brain. In order to cooperate with the above operation, = 11 200535795 The automatic ia i control unit 112 in the known example is an analogue automatic gain control unit, which is familiar. This technique is widely known by the technicians, so Lin Shu. In this implementation, the digital automatic gain control early π 132 is based on the number of occurrences of each digital value within a specific time _ a (that is, the appearance of the 2 values) to charm gain control profile msj) AGC3, · DRB Gain value. The following description is based on the principle of # in the present embodiment, adjusting the value of the read-back signal hall of the optical disc 13G by adjusting the whole module 13G. Similarly, due to the resolution of the analogue digital conversion ㈣6 at the saturation point, the $ characteristics of the ㈣6 'is saturated when the highest-order value 011 and the lowest-order value appear in the order ⑴, m⑴, ^ other order values _, Xie, Ca', ln, and m The number of occurrences m (7: 2) is a multi-time line (when the difference between them exceeds a certain threshold value), indicating that the dynamic range of the output signal sii is excessively reduced. V 'The digital automatic gain control unit 132 will reduce the read-back signal of the disc雠 ^ value. When the highest-order value on and the lowest-order value 1101 occur, the first-order numerical value, _, coffee, ⑽, lu, and 11G appear m (7: 2). The dynamic range is too small and should be increased, so the digital automatic gain control early 70 132 will increase the gain value of the disc readback signal DRB. ^ Refer to FIG. 7, which is a schematic diagram of a fourth embodiment of the input sampling circuit shed of the present invention. The conversion circuit 110, the DC adjustment module 120, and the gain shown in the third embodiment of FIG. 6 are shown in FIG. 6. In addition to 10, the input sampling circuit side of the fourth embodiment further includes a phase-locked loop. In the known example, the phase-locked loop 14 is composed of a phase / frequency pre-measurement detector (Qing),: filter (LF) 144,-digital analog converter (DAC) 146, and a controlled write reduction, = ), Composed of 148, the above circuit architecture and its operating principles are widely used by those skilled in this technology for the low riding degree lion number transfer charm 116 into the oblique position of the sampling connection; if the analog digital conversion 11116 sampling frequency complement If it is high, you can also use the digital sampling touch sampling circuit (i.e., ⑻) to replace the voltage-controlled oscillator 148, which is similar to the conversion of the voltage-controlled oscillator 148, and the operation of the scale sampling circuit 12 200535795 It is widely known, so I wo n’t repeat it here. Mingcha sees Figure 8 '11 is a schematic diagram of the fifth embodiment of the sample circuit 5⑽ of the present invention. The conversion circuit shown in the second embodiment of Figure 2 二In addition to the DC adjustment module, = Beta case, input sampling circuit 5⑼ Contains-clock generation module ⑽, using a cut-off wave 152 and-digital phase-locked loop (DPLL) 154, according to the output signal su to increase the sampling clock signal ⑽ on which the analog digital converter 116 performs sampling. Μ * Λ = "The asymmetry compensation unit 124 is based on the DC level of the square wave Li f cycle signal su generated by the interceptor 152. The circuit architecture and operating principle described above are widely known, so do n’t To repeat. In addition, through the input of this embodiment: the digital signal D1 generated after processing can also be performed by an RLL rule violation check rule (V10latl0n checking / correc_tic) n unit) 160 to perform rll regulation;; ^^ (statemachine) 170 w * 114Γϋ ί The best parameters of 114, such as the zero or pole position in the low-pass data wave / equalization L transfer to transfer function. : The circuit architecture and operation principle mentioned above are also familiar with the W value of 118 Gongzao 70 2, which is also widely known to those skilled in this technology. Equal ZIZ, the age of invention invention 1, please check the species of tree-checking Japanese-, daggers, and L ornaments, ^ should belong to the scope of the invention patent. [Brief description of the diagram] Brief description of the diagram Figure = is a schematic diagram of the first embodiment of the input sampling circuit of the present invention. FIG. = Is a flowchart of an input sampling method according to an embodiment of the present invention. = Three is the schematic diagram of the conversion range of the low-resolution analog-to-digital converter shown in the figure. It is a schematic diagram of the conversion system of the low-resolution analog-to-digital converter shown in FIG. 13 200535795 Figure 5 is a schematic diagram of the second embodiment of the input sampling circuit of the present invention. FIG. 6 is a schematic diagram of a third embodiment of an input sampling circuit according to the present invention. FIG. 7 is a schematic diagram of a fourth embodiment of the input sampling circuit according to the present invention. FIG. 8 is a schematic diagram of a fifth embodiment of an input sampling circuit according to the present invention. Symbols of the drawing 112 Automatic gain control unit 114 Low-pass filter / equalizer 144 Loop filter 122 Adder 152 Chopper 124 Asymmetric compensation unit 140 Phase-locked loop 100, 200, 300, 400, 500 Input sampling circuit 110 Conversion circuit 116 Low-resolution analog digital converter 120 DC adjustment module 130 Gain adjustment module 132 Digital automatic gain control unit 140 Phase-locked loop 142 Phase / frequency detector 146 Digital analog converter 148 Oscillator 150 Clock generation Module 154 Digital Phase Locked Loop 160 RLL Rule Violation Check / Correction Unit 170 State Machine 14