200531143 九、發明說明： 【發明所屬之技術領域】 本發明涉及具有一基板和一半導體主體的光電子半導體 裝置，通常由矽構成，其中所形成的（C)M〇S影像感测器 具有一輻射敏感區矩陣，該區域形成影像感測器的像素， 且其中層的堆疊在半導體主體上形成，其包括一電絕緣層 和圖案化電傳導層的交替。一（C)MOS(=互補金屬氧化 物半導體）影像感測器被認為是一種固態影像記錄裝置， _ 其藉由（標準）(：：1^〇8技術製成。這類技術有助於ic(=積體 電路）的製造，包括MOSFET(=場效電晶體），通常量都报 大。CMOS影像感測器通常包括，除了用於每個像素的少 數的這類電晶體之外，在像素的矩陣之外，還有一包含電 晶體和其他組件的積體電路，例如用於信號處理和管理。 輻射敏感區可形成例如一電晶體或二極體，或是其相關部 份。 【先前技術】 美國專利第6,506,619號描述一種CMOS影像感測器的製 造方法，其中具有光二極體形態的輻射敏感區在矽的半導 體主體中形成，其同時亦作為基板之用。耦合至該處的一 或若干M0SFET，例如當作轉移或重設電晶體用。影像减 測器利用多層流程製造。在此情況下，半導體主體上提供 層的堆疊，包括一電絕緣或介電層與一圖案化電傳導層的 父替，通常由一金屬或金屬合金或金屬化合物構成。導電 層的圖案化會被鏈結到某些環境，該環境通常不傳輸待偵 99324.doc 200531143 測的輻射，因此在輻射敏感區範圍應具有開口，或鍵結到 電傳導層的功能，該層通常構成該裝置的一多層接線。 . 已知方法和半導體裝置的缺點是，目前趨勢;月向最小零 件尺寸的更縮小化（從大約！陶發展為約〇1㈣，以及大 f、絕緣和傳導層的使用，實際上沒有致使cm卿像感測 器具有好的特性。因此靈敏度不像所希望的—樣高，此 外，串擾會在兩個鄰近像素之間、鄰近像素的輕射敏感區 之上不同顏色的濾光片出現的地方發生。 • 【發明内容】 因此本發明的目的是提供具有高靈敏度和低（色彩）串擾 的CMOS影像感測ϋ。然後製造方法較好與標準的 技術相容’在最小尺寸持續變小的情況下仍樣適用。 本發明係藉由如申請專利範圍之獨立項來定義。申請專 利耗圍之附屬項定義有利的具體實施例。根據本發明，介 、”口文字中提到的方4 ’其特徵為，提供電絕緣和傳導層的 隹且之後凹處在輪射敏感區範圍的堆疊中形成，其中堆 疊的一部份再次被移除，同時位於待形成的凹處之外的堆 邛伤又到一光罩保護。部份堆疊的移除可經由例如蝕刻 么生也可藉由替代的已知方法，例如引導雷射光對準堆 疊’使後者揮發。 本發明所依據的認知為：首先，較低的靈敏度以及特別 疋色先串@是其上出現彩色遽光片層的堆叠層厚度相當 大的、、Ό果例如光的入射輻射的略微角度偏差，可導致朝 向某個像素的輕射到達具有不同色彩的彩色濾光片的鄰近 99324.doc 200531143200531143 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to an optoelectronic semiconductor device having a substrate and a semiconductor body, which is usually composed of silicon. The (C) MOS image sensor formed therein has a radiation sensitivity. A matrix of regions, the regions forming the pixels of the image sensor, and the stack of layers formed on the semiconductor body, which includes an alternation of an electrically insulating layer and a patterned electrically conductive layer. A (C) MOS (= Complementary Metal Oxide Semiconductor) image sensor is considered a solid-state image recording device. It is made using (standard) (:: 1 ^ 〇8 technology. This type of technology helps The manufacturing of ic (= integrated circuit), including MOSFET (= field effect transistor), is usually reported in large quantities. CMOS image sensors usually include, in addition to a few such transistors for each pixel, In addition to the pixel matrix, there is an integrated circuit containing transistors and other components, such as for signal processing and management. The radiation-sensitive area can form, for example, a transistor or a diode, or a related part. Prior Art] US Patent No. 6,506,619 describes a method for manufacturing a CMOS image sensor, in which a radiation-sensitive region having a photodiode shape is formed in a semiconductor body of silicon and also serves as a substrate. Coupling to this One or several MOSFETs, for example, for transferring or resetting transistors. The image subtractor is manufactured using a multi-layer process. In this case, a stack of layers is provided on the semiconductor body, including an electrically insulating or dielectric layer and The parent of the patterned electrically conductive layer is usually composed of a metal or metal alloy or metal compound. The patterning of the conductive layer will be linked to certain environments, which usually do not transmit the radiation to be detected 99324.doc 200531143, Therefore, it should have the function of opening or bonding to the electrically conductive layer in the area of the radiation sensitive area, which usually constitutes a multilayer wiring of the device. The disadvantages of the known methods and semiconductor devices are the current trends; the smallest parts in the moon direction The reduction in size (from about! Tao to about 〇1㈣, and the use of large f, insulation, and conductive layers did not actually make the cm sensor have good characteristics. So the sensitivity is not as expected — The sample height is high. In addition, crosstalk occurs between two adjacent pixels and where different color filters appear above the light-sensitive area of the adjacent pixels. [Summary of the Invention] Therefore, the object of the present invention is to provide high sensitivity. And low (color) crosstalk CMOS image sensing. Then the manufacturing method is better compatible with standard technology. 'It is still applicable when the minimum size continues to decrease. The present invention is defined by independent items such as the scope of the patent application. The appended items of the patent application scope define advantageous specific embodiments. According to the present invention, the "4" mentioned in the "character" feature is to provide The piercing and subsequent recesses of the electrically insulating and conductive layer are formed in a stack in the range of the shot-sensitive area, in which a part of the stack is removed again, and at the same time, the piercing of the stack outside the recess to be formed reaches a light. Cover protection. Partial stack removal can be done by, for example, etching or by alternative known methods, such as directing laser light at the stack to make the latter volatilize. The present invention is based on the recognition that, first, the lower Sensitivity and special black-colored first string @ is the thickness of the stacked layer of the colored light-emitting layer on which a considerable angular deviation of the incident radiation such as light can cause the light shot towards a pixel to have a different The proximity of the color filter for color 99324.doc 200531143
像素。此外，該堆疊厚度相當A 收指生»、臭W * 月，、Y曰發生較鬲的吸 邊界表面反射所導致的損失，因為實際上 =構件在個別層之間有大量的邊界表面。本發明所依 :另=知為：這些缺點可透過在製程末期移除 :區㈣處的部份堆疊來加以克服，同時對堆疊表面其餘 ρ使用先罩。試著使堆疊的厚度變薄或在個別Pixels. In addition, the thickness of the stack is equivalent to the loss caused by the absorption of A, B, W, Y, and Y due to the absorption of the boundary surface reflection due to the absorption, because in fact, the component has a large number of boundary surfaces between individual layers. The invention is based on the following: It is known that these disadvantages can be overcome by removing a part of the stack at the end of the process at the end of the manufacturing process, while using the first mask for the remaining ρ of the stack surface. Try to make the stack thinner or thinner
:不同的開口有若干優點，例如高良率、較小的製程J ，以及不論是否刻意導致的，在凹處形成時使用堆疊特 性的可能性。 ’ 根據本發明方法的第—具體實施例中，選擇電傳導声的 圖案’以致在凹處形成時使凹處壁具有階梯形的外觀。 這種外觀對於凹處底部彩色漶光片層的提供有潛在優 勢’因為更易於以儘可能的同質層覆蓋這個底部。這是因 為，若凹處壁更陡靖時，這類層在底部與壁之間的鄰近角 點比接近底部令心處更傾向於變厚或變薄。原則上，梯度 鲁平滑不陡山肖的凹處壁，也適用這一目的。但是，這一具二 I施例的方法，更適合尺寸逐漸縮小的製程且更相容：目 前製程。如果選擇敍刻技術用於形成凹處，選擇一濕化學 钱刻法優於所謂的電漿或乾蝕刻法。 所選擇的㈣劑’較佳可用於選擇性#刻與傳導層材料 相關的電絕緣層材料。由於蝕刻在達到金屬層或其相關部 伤合止在這類傳導層中特別是透過圖案的使用，凹處很 谷易形成上述所希望的階梯形外觀。 在一有利的具體實施例中，以不間斷的方式在輻射敏感 99324.doc 200531143 區上提供其令—層電傳導層，並在這層上提供另—光罩， 覆蓋其相關部份，在姓刻流程已達到該層之後，在該處之 上該層㈣露部份利用適合的钱刻劑移除，之後姓刻繼續 進行。藉此以簡單的方法產生所需_料觀的階梯。 在另—具體實施例中，其中^間斷的方式在輕射敏感 區上提供其中一層電傳導層，藉由光罩向下韻刻至該傳導 層，在該處之上相關的曝露部份利用相同的光罩和適合的 ㈣劑移除，之後似彳繼續進行n修正後的具體實 藝&例中，凹處的外觀的確比較陡靖，但是這—具體實施例 具有使用不超過一個光罩即可形成所需凹處的優點。 在另一修正後的具體實施例中，堆疊具有一層，該層不 一定要能夠執行CMOS流程的功能，但在凹處形成時作為 姓刻停止層使用。在此情況下可以類似方法再次形成凹處 壁中的階梯。 較好，凹處形成後在凹處内提供一彩色濾光片層。因此 φ 形成具有優良特性的色彩成像單元，例如像一高靈敏度和 一低（色彩）串擾。 較好再在輻射敏感區上提供一當作光圈用的透鏡。 在有利的具體貫如例中，所使用的堆疊包括四個或更 多的傳導層，因此也包括四個或更多的介電層。然後最低 兩層的傳導層用於，例如，形成（連接）導體的多層圖案， 可使用或夕個；丨電層中所謂的通道來互連導體或連接他 們到形成部分裝置的半導體區域。最上面的兩層傳導層， 較好包括鋁或銅或其合金，可作為連接區域，例如用於接 99324.doc 200531143 線連接器。這些層的其中-層或兩層，也用於㈣部份麥 置的入射輻射。尤其，這可與具有整合型電子（辅助）電^ 的一部份有關。 在這類修正後的具體實施例中，選擇凹處的深度以達 所需要的結果。已達到的情況是，例如，#由堆疊厚度的 縮減，從例如大約6 /^11厚度減少到大約3 的厚度。=此 有助於凹處向下形成到達一電絕緣層，該層出現在第二傳 導層上。在另一有利的修改實例中，凹處向下形成到達一 電絶緣層，該層出現在第二傳導層之下。 本發明進一步涉及包括一基板和一半導體主體的光電子 半導體裝置，該半導體主體具有一固態影像感測器，=感 測器包括形成影像感測器像素的輻射敏感區矩陣，在該^ 導體主體上提供一堆疊層’該堆疊包括每次一電絕緣層和 一圖案化電傳導層的交替，其特徵為電絕緣層和傳導層的 堆疊在輻射敏感區的範圍處具有凹處。這具有較少色^串 擾的優點並且堆疊中的吸收損失較低。 堤類裝置可以是價格低廉且體積小，特別適合應用於需 要低功率耗損的裝置。 本發明進一步涉及一種具有一根據本發明的光電子半導 體裝置的照相機。這類照相機可用於提升例如膝上型電腦 或行動電話的優勢。也可以用於高品質的照相機。 【實施方式】 圖1到6概略顯示一光電子半導體裝置，並顯示藉由根據 本發明的第一具體實施例方法，製造該裝置的連續相關階 99324.doc -10, 200531143 段中、在垂直厚度方向上的橫斷 ^ ]也、斷面。裝置】〇(參見圖1)的形 成從具有一基板的一半導體主 粒主體，其在圖中並未分 4表示，此處由石夕製成，且其中形成-輻射敏感區A。韓 感區A是例如一 11型石夕區域，再加上例如位於其之下的 一 P型矽區域，圖中未顯干，π二、 ”、…、形成一輻射敏感光二極體。 本範例的裝置令每個像素有四個電晶體，其中兩個Τ1、 ==)可見於圖1的橫斷面中，用於傳送和放大信號以 ^於重設和選取像素之用。本_的裝置1G包括四個傳 ―層1、2、3、4,在本例中該傳導層的下方、傳導層之間 以及傳導層的上方右介 " 方有"电層5、6、7、8、9,其包括例如 一我化石夕（層 5B、5C、5D、6B、7B、8a、8b、9a、9b、 1、氮化石夕（層5A)所謂&「低k」材料（層m)。 則兩層傳導層1、2彼此相連或經由通道v連接到半導體 主體11中的半導體區域。最上面兩層傳導層3、4,此處以 ，衣成’可形成對抗入射到線段L右側裝置上的輻射的 螢幕。在本範例中，第三傳導層3剛開始是不間斷的，如 圖1所示，同時出現在線段L左邊和右邊的區域，其中出現 輻射敏感區A。本範例中的裝置1〇’在圖1顯示的製造階段 係利用標準0刪技術製造。圖1顯示的裝置10的部份’表 示在裝置的兩個部份之間的轉變。第一部份，在圖i線段 L1的左邊，其中有一輻射敏感區A的矩陣，以及—第二部 份」在圖1線段U的右邊，其中有一或多個電子電路受到 保護以對抗入射輻射。此處這個第二部份包圍第一部份。 附圖只顯示轉變區。輕射敏感區A矩陣的側面尺寸，:如 99324.doc 200531143 疋大、力5公釐x5公釐，㈤時所有裝置⑺測量為大約w公爱 10△厘然、後該第二部份形成一大約2·5公釐寬的半導體 ^體長條圍住輻射敏感區Α的矩陣。在標準⑽⑽製造階 β ,圖1』7F的P皆段正好是施加氮化石夕層形式的刮痕保 護之前的階段。: Different openings have several advantages, such as high yield, smaller process J, and the possibility of using stacking features when forming recesses, whether or not intentionally caused. In the first embodiment of the method according to the present invention, the pattern of electrically conducting sound is selected so that the recess wall has a stepped appearance when it is formed. This appearance has the potential advantage of providing a colored calender sheet layer at the bottom of the recess' because it is easier to cover this bottom with as homogeneous a layer as possible. This is because, if the recessed wall is steeper, the adjacent corners of the layer between the bottom and the wall tend to become thicker or thinner than the center of the bottom. In principle, the gradient wall is smooth and not steep, and the recessed wall is suitable for this purpose. However, this method with two I embodiments is more suitable for a process with gradually decreasing size and is more compatible: the current process. If the engraving technique is selected for the formation of the recess, a wet chemical money engraving method is preferred over the so-called plasma or dry etching method. The selected elixirs' are preferably used to selectively etch the material of the electrically insulating layer associated with the material of the conductive layer. Due to the use of etching to reach the metal layer or its related parts, especially in the use of a pattern in this type of conductive layer, the recesses can easily form the desired stepped appearance described above. In an advantageous specific embodiment, its order-layer electrical conductive layer is provided in an uninterrupted manner on the radiation-sensitive 99324.doc 200531143 area, and another layer of photomask is provided on this layer to cover its relevant parts. After the surname engraving process has reached this layer, the exposed part of the layer above it is removed with a suitable money engraving agent, and then the surname engraving continues. In this way, the desired ladder is produced in a simple way. In another embodiment, an electrically conductive layer is provided intermittently in the light-sensitive area, and the conductive layer is engraved downward through the photomask, and the relevant exposed part is used above it. After removing the same photomask and suitable tincture, it seems that after the n-correction is performed, the appearance of the recess is indeed steep, but this—the specific embodiment has no more than one light. The hood has the advantage of forming the desired recess. In another modified embodiment, the stack has a layer, which does not have to be able to perform the functions of the CMOS process, but is used as a last stop layer when the recess is formed. In this case, steps in the recess wall can be formed again in a similar manner. Preferably, a color filter layer is provided in the recess after the recess is formed. Therefore, φ forms a color imaging unit with excellent characteristics, such as a high sensitivity and a low (color) crosstalk. It is preferred to provide a lens for the aperture in the radiation sensitive area. In an advantageous embodiment, the stack used includes four or more conductive layers and therefore also four or more dielectric layers. The lowest two layers of conductive layers are then used, for example, to form (connect) a multilayer pattern of conductors, which can be used; or so-called channels in the electrical layer to interconnect the conductors or connect them to the semiconductor area forming part of the device. The top two conductive layers, preferably comprising aluminum or copper or an alloy thereof, can be used as connection areas, for example for 99324.doc 200531143 wire connectors. One or two of these layers are also used for incident radiation in a part of the wheat plant. In particular, this may be related to the part with integrated electronic (auxiliary) electricity ^. In this modified embodiment, the depth of the recess is selected to achieve the desired result. It has been achieved, for example, that # is reduced by a reduction in stack thickness from, for example, a thickness of about 6 / ^ 11 to a thickness of about 3. = This helps the recess to form downwards to an electrically insulating layer, which appears on the second conductive layer. In another advantageous modification, the recess is formed downwards to an electrically insulating layer, which layer appears below the second conductive layer. The present invention further relates to an optoelectronic semiconductor device including a substrate and a semiconductor body. The semiconductor body has a solid-state image sensor, and the sensor includes a matrix of radiation-sensitive areas forming pixels of the image sensor. A stack layer is provided. The stack includes an alternation of an electrically insulating layer and a patterned electrically conductive layer at a time, and is characterized in that the stack of the electrically insulating layer and the conductive layer has a recess at the range of the radiation sensitive area. This has the advantage of less color crosstalk and lower absorption losses in the stack. Embankment devices can be inexpensive and small, and are particularly suitable for applications requiring low power consumption. The invention further relates to a camera having an optoelectronic semiconductor device according to the invention. Such cameras can be used to enhance the advantages of, for example, a laptop or a mobile phone. Can also be used for high-quality cameras. [Embodiment] Figs. 1 to 6 schematically show an optoelectronic semiconductor device, and show the continuous correlation stages of manufacturing the device by the method according to the first embodiment of the present invention in paragraphs 99324.doc -10, 200531143, in vertical thickness Cross section in the direction ^] Also, section. Apparatus] (see FIG. 1) is formed from a semiconductor main body having a substrate, which is not shown in the figure. It is made of Shi Xi, and a radiation-sensitive area A is formed therein. The Hangan area A is, for example, a 11-type Shixi area, and a P-type silicon area underneath it, for example, which is not significantly dry in the figure, π, 2, ", ..., forming a radiation-sensitive photodiode. The example device has four transistors per pixel, two of which T1, ==) can be seen in the cross-section of FIG. 1 for transmitting and amplifying signals for resetting and selecting pixels. This _ The device 1G includes four transmission layers-layers 1, 2, 3, and 4, in this example, below the conductive layer, between the conductive layers, and above the conductive layer. 7,8,9, which include, for example, a self-fossil eve (layers 5B, 5C, 5D, 6B, 7B, 8a, 8b, 9a, 9b, 1, and so-called & `` low-k '' materials) (Layer m). Then the two conductive layers 1, 2 are connected to each other or connected to the semiconductor region in the semiconductor body 11 via the channel v. The top two conductive layers 3, 4 are formed here so that they can be formed to resist incidence. The radiating screen on the device on the right side of the line segment L. In this example, the third conductive layer 3 is uninterrupted at first, as shown in Figure 1, and appears on the left side of the line segment L at the same time On the right, there is a radiation-sensitive area A. The device 10 ′ in this example is manufactured using standard zero-cut technology during the manufacturing stage shown in FIG. 1. The part of the device 10 shown in FIG. The first part is on the left side of the line segment L1 in Fig. I, which has a matrix of radiation sensitive area A, and the second part is "on the right side of the line segment U in Fig. 1, which has one or more electrons. The circuit is protected against incident radiation. The second part here surrounds the first part. The figure only shows the transition area. The side dimensions of the light-sensitive area A matrix, such as 99324.doc 200531143 Cm x 5 mm, all devices at this time were measured to be approximately 10 mm, and then the second part formed a matrix of approximately 2.5 mm wide semiconductor ^ body strips surrounding the radiation sensitive area A In the standard manufacturing stage β, the P segments of Fig. 1'7F are just before the application of scratch protection in the form of a nitrided layer.
>根據本發明（參見間，最先經由光微影和㈣法首先 光罩Μ1 (在本例中以光阻製成）。然後裝置1 〇被導入 芑水蝕刻叙置内，在光罩Μι的開口内以乾式的各向里 性銳刻流程移除絕緣層从、犯、9€。這裡的第四金屬層 4(參見圖2)做為—㈣停止層，但是金屬層獨口内的㈣ 持續進订。因此局部移除介電層8八、8B。凹處c藉此在傳 導和介電層1到9堆疊S中的作用區A的範圍處形成。蚀刻流 程在到達第三金屬層3時再次停止。 隨後（參見圖3)，裝置10上提供一第二光罩M2，曝露出 比對應到第二金屬層4開口小的第三金屬層3的部份。第三 金屬層3的曝露部份隨後以不同的蝕刻劑蝕刻移除，不一 定針對下方的介電層7B選擇。然後使用適合蝕刻介電層 7A、7B的蝕刻劑繼續蝕刻（參見圖句，使得在堆疊s中出現 的凹處c的深度略微超過整個堆疊s的一半，此處約為6 μπι厚。 光罩Ml和Μ2(參見圖5)隨後以一般常見的方式移除。首 先提供氮化矽層20形式的刮痕保護。然後（參見圖6)以一旋 轉流程或一噴霧流程，在每個凹處c的底部提供一彩色濾 光片層F。在彩色影像感測器的情況下，三個不同的濾光 99324.doc -12- 200531143 片用於鄰近像素中。這在所提供的三個濾光片層中完成， 其藉由光微影法圖案化。隨後，在影像感測器丨〇的每個輻 射敏感區A之上提供透鏡（未顯示）。 根據本發明的方法，一方面提供具有相當高靈敏度的影 像感測器10，另一方面在鄰近像素之間不產生或產生極少 的（色彩）串擾，其歸因於濾光片F下方堆疊S的較小厚度。 由於凹處C壁的外觀（其中為了簡化，圖中僅顯示一個）具 有一階梯形狀，在凹處c底部的濾光片層！7可具有一相當一 致的厚度，藉此改良影像感測器丨〇的品質。在套用上面曾 提及的透鏡之後，本範例的裝置1〇已準備好最後的安裝。 圖7到1〇，概略顯示一光電子半導體裝置，並顯示藉由 根據本發明的第二具體實施例方法，製造該裝置的連續相 關#又中、在垂直厚度方向上的橫斷面。本範例中裝置1 〇 的製造如在先前範例中，大幅進展到圖7所示的階段。主 要的差異疋在苐二金屬層3藉由光微影和钱刻來圖案化， 緊接在堆皆S貫現期間其提供之後。一般而言，這不需要 額外的光罩，仍然可行。這是因為已位在圖式以外的裝置 10—部份中的第三金屬層3將必須圖案化，然後可適合這 所需要的光罩。但是，符合以上提供的介電層8、9的任何 瑕症’第三金屬層一般可能導致問題。 在根據本發明方法的這個具體實施例中，這類瑕疵並沒 有扮演任何角色，因為在稍後階段中將在這個位置產生凹 處c ’所以該瑕疵會被移除。 完成堆疊S(參見圖7)之後，如先前範例的製造大幅進 99324.doc -13- 200531143 程在達到第三金屬们（參見 白以不斷或修正。在這個範例（參見圖9)中，凹處 的形成會繼續直到達到第二圖案化金屬> According to the present invention (see also, first through photolithography and photolithography method first photomask M1 (made of photoresist in this example). Then device 10 is introduced into the water-etching device and placed in the photomask. In the opening of Mm, the insulating layer is removed by a dry anisotropic sharp cutting process. The fourth metal layer 4 (see Figure 2) is used as the ㈣stop layer, but the metal layer is in the mouth of the metal layer alone.进 Continuous ordering. Therefore, the dielectric layers 88 and 8B are partially removed. The recess c is thereby formed at the area of the active area A in the conductive and dielectric layers 1 to 9 stack S. The etching process is reached at the third metal Layer 3 stops again. Then (see FIG. 3), a second photomask M2 is provided on the device 10 to expose a portion of the third metal layer 3 that is smaller than the opening corresponding to the second metal layer 4. The third metal layer The exposed portion of 3 is subsequently removed by etching with a different etchant, which may not necessarily be selected for the underlying dielectric layer 7B. Then use an etchant suitable for etching the dielectric layers 7A, 7B to continue etching (see the figure, so that the The depth of the recesses c appearing in is slightly more than half of the entire stack s, here about 6 μm thick. The masks M1 and M2 (see FIG. 5) are subsequently removed in a generally common manner. Scratch protection in the form of a silicon nitride layer 20 is first provided. Then (see FIG. 6), in a rotating process or a spray process, in each recess A color filter layer F is provided at the bottom of the position c. In the case of a color image sensor, three different filters 99324.doc -12- 200531143 are used in adjacent pixels. This is in the three provided This is done in a filter layer, which is patterned by photolithography. Subsequently, a lens (not shown) is provided over each radiation sensitive area A of the image sensor. The method according to the invention, on the one hand, An image sensor 10 having a relatively high sensitivity is provided, on the other hand, no or little (color) crosstalk is generated between adjacent pixels, due to the smaller thickness of the stack S under the filter F. Due to the recess The appearance of the C wall (only one of which is shown in the figure for simplicity) has a stepped shape, and the filter layer at the bottom of the recess c! 7 can have a fairly uniform thickness, thereby improving the image sensor. Quality. Apply the lens mentioned above Afterwards, the device 10 of this example is ready for final installation. Figures 7 to 10 schematically show an optoelectronic semiconductor device and show the continuous correlation of manufacturing the device by the method according to the second embodiment of the present invention # The cross section in the vertical thickness direction. The manufacturing of the device 10 in this example progresses to the stage shown in Fig. 7 as in the previous example. The main difference lies in the second metal layer 3 by light. Lithography and money are engraved for patterning, immediately after its provision during the Duyesun period. Generally speaking, this does not require an additional photomask, and it is still feasible. This is because the device is already located outside the figure. The third metal layer 3 in the part will have to be patterned and can then be adapted to the required photomask. However, any defects of the dielectric layers 8, 9 provided above, the third metal layer may generally cause problems. In this particular embodiment of the method according to the invention, this type of defect does not play any role, as the recess c 'will be created at this position in a later stage, so the defect will be removed. After stacking S (see Fig. 7), the manufacturing of the previous example is greatly improved as 99324.doc -13- 200531143 is reaching the third metal (see white for continuous or correction. In this example (see Fig. 9), the concave Formation continues until a second patterned metal is reached
^間位於第二金屬層2下方的介電⑽可當仙刻L 層使用。若需要這樣的話，除了範例所示的二氧化石夕層6B 之^堆疊S形成期間可針對這個目的在該二氧化石夕層沾 提仏非书薄#氮化石夕層（未顯示）。@個修正後且體杏 施例(參見圖:)的製造還利用凹處C壁中階梯形外觀㈣； j間出現在第一傳導層2的圖案。這意謂除了附圖左邊的 第二壁之夕卜’凹處C包括大量上升階梯H，#位在鄰近像 素之間凹處C的底部，且該壁與附圖右邊的壁一致。最後 (參見圖10)，製造如以上第一範例所討論的繼續進行，而 且在凹處C提供彩色渡光片f。 圖11到12概略顯示一光電子半導體裝置，並顯示藉由根 據本發明的第三具體實施例方法，製造該I置的連續相關 階段中、在垂直厚度方向上的橫斷面。與先前範例的唯一 差異為：在那裡使用的長條狀金屬層3(參見圖7到1〇中對 應到圖11和12階段的部份），其出現在圖式左邊，現在不 存在。形成凹處C底部局部提高的外觀Η因此相較於圖1〇 裝置的外觀比較不高並且較不突出（例如，參見圖12)。這 樣修改的優點是彩色濾光片層漆的黏著性較佳。 若需要這樣的話，可以再次根據本發明方法的這類修改 使用一（介電）蝕刻停止層，以與第二範例相同的方式隨後 進行。 99324.doc • 14- 200531143 本發明不限於所描述的具體實施例，因為對熟習本技術 之專業人士許多變化和修改都可以在本發明的範圍内。因 此可以不同的幾何圖形及/或不同的尺寸製作該等裝置。 除了矽基板，還可使用玻璃基板、陶瓷材料、或合成樹 脂。半導體主體可藉由所謂SOI(=絕緣體上矽）技術形成。 這不一定要使用所謂的基板轉移技術。 另外還要 >主意，可使用範例中提及的材料之外的其他材 料，仍不脫離本發明範圍。這同樣適用傳導（或金屬）層及/ • 或介電層。還可以針對相同類型的層使用不同的材料。並 且，該層或材料可使用不同的沈積技術：磊晶、CVD(=化 學汽相沈積）、濺射和蒸發。除了濕式化學蝕刻法，例如 用於包含氧化石夕層的以HF為基礎的溶劑以及用於氮化石夕層 的（熱）磷酸，用法中可包含乾式蝕刻法，以移除形成堆疊 部份的一或若干層。 另外再久/主意，該裝置可包括其他主動和被動半導體元 φ 件或電子組件，例如像大量的二極體及/或電晶體，以及 電阻器及/或電容器，不一定要是積體電路的形式。 本♦月不限於CMOS影像感測器。也可涵蓋其他的技 術’例如像電荷耦合元件（CCD)。 【圖式簡單說明】The dielectric ions located below the second metal layer 2 can be used as the engraved L layer. If this is required, in addition to the SiO 2 layer 6B shown in the example, the formation of a stack S may be performed on the SiO 2 layer for this purpose. The production of the @modified and body apricot embodiment (see figure :) also uses the stepped appearance ㈣ in the recess C wall; the pattern appearing in the first conductive layer 2 between j. This means that in addition to the second wall on the left of the drawing, the recess C includes a large number of ascending steps H, # located at the bottom of the recess C between adjacent pixels, and the wall is consistent with the wall on the right of the drawing. Finally (see FIG. 10), manufacturing proceeds as discussed in the first example above, and a color dome f is provided in the recess C. 11 to 12 schematically show an optoelectronic semiconductor device, and show a cross-section in the vertical thickness direction in successive correlation stages of manufacturing the device by a method according to a third embodiment of the present invention. The only difference from the previous example is that the strip-shaped metal layer 3 used there (see the parts corresponding to Figs. 11 and 12 in Figs. 7 to 10) appears on the left side of the drawing and does not exist. The appearance of the bottom of the formation of the recess C is partially enhanced. Therefore, compared with the appearance of the device of FIG. 10, the appearance is lower and less prominent (for example, see FIG. 12). The advantage of this modification is that the color filter layer paint has better adhesion. If this is desired, a (dielectric) etch stop layer can be used again in accordance with this type of modification of the method of the present invention, and subsequently performed in the same manner as in the second example. 99324.doc • 14- 200531143 The invention is not limited to the specific embodiments described, as many variations and modifications to those skilled in the art can be made within the scope of the invention. These devices can therefore be made in different geometries and / or different sizes. In addition to silicon substrates, glass substrates, ceramic materials, or synthetic resins can be used. The semiconductor body can be formed by so-called SOI (= Silicon On Insulator) technology. This does not necessarily require the use of so-called substrate transfer technology. In addition, > The idea is that materials other than those mentioned in the examples may be used without departing from the scope of the present invention. The same applies to the conductive (or metal) layer and / or the dielectric layer. It is also possible to use different materials for the same type of layers. Also, the layer or material can use different deposition techniques: epitaxy, CVD (= chemical vapor deposition), sputtering, and evaporation. In addition to wet chemical etching methods, such as HF-based solvents for oxide stone layers and (thermal) phosphoric acid for nitride stone layers, dry etching methods can be included in the usage to remove the stacked parts One or more layers. Also long after / idea, the device may include other active and passive semiconductor elements or electronic components, such as, for example, a large number of diodes and / or transistors, and resistors and / or capacitors, not necessarily integrated circuits form. This month is not limited to CMOS image sensors. Other technologies ' may also be covered, such as, for example, a charge coupled device (CCD). [Schematic description]
在將參考若干具體實施例及圖式，詳細說明本發明， 其中： X =1到6概略顯示一光電子半導體裝置，並顯示藉由根據 本毛明的第一具體實施例方法，製造該裝置的連續相關階 99324.doc -15- 200531143 段令、在垂直厚度方向上的橫斷面， 圖7到10概略顯示一光電子半導體裝置，並顯示藉由根 據本發明的第二具體實施例方法，製造該裝置的連續相關 P白#又中、在垂直厚度方向上的橫斷面，以及 圖11到12概略顯示一光電子半導體裝置，並顯示藉由根 據本發明的第三具體實施例方法，製造該裝置的連續相關 階段中、在垂直厚度方向上的橫斷面。 這些圖不是真正依比例和某些尺寸繪製，例如像厚度方 向的尺寸，就特別加以放大以說明清楚。在不同的圖式中 儘可能給予對應的區域或組件相同的細線標示或相同的來 【主要元件符號說明】The present invention will be described in detail with reference to several specific embodiments and drawings, in which: X = 1 to 6 schematically shows an optoelectronic semiconductor device, and shows that the device is manufactured by the method according to the first specific embodiment of the present Maoming Continuous correlation level 99324.doc -15- 200531143 paragraph order, cross-section in vertical thickness direction, Figs. 7 to 10 schematically show an optoelectronic semiconductor device, and show that it is manufactured by the method according to the second embodiment of the present invention The continuous correlation of the device, P #, and the cross section in the vertical thickness direction, and FIGS. 11 to 12 schematically show an optoelectronic semiconductor device, and show that the method is manufactured by the method according to the third embodiment of the present invention. A cross-section in the vertical thickness direction of successive relevant stages of the device. These figures are not really drawn to scale and certain dimensions, such as those in the thickness direction, and they have been specifically enlarged for clarity. In different drawings, give the corresponding area or component the same thin line mark or the same as far as possible. [Description of the main component symbols]
1、2、3、4 5、6、7、8、9 5A-5D 6A-6B 7A-7B 8 A- 8 B 9A-9C 10 11 20 A C 圖案化傳導層 電絕緣層 層 層 層 層 層 光電子半導體裝置 半導體主體 氮化石夕層 輻射敏感區 凹處 99324.doc • 16· 200531143 F 彩色濾光片層 Ml 光罩 M2 第二光罩 S 堆疊 ΤΙ、T2 電晶體 V 通道 99324.doc -17-1, 2, 3, 4 5, 6, 7, 8, 9 5A-5D 6A-6B 7A-7B 8 A- 8 B 9A-9C 10 11 20 AC patterned conductive layer electrical insulation layer layer layer layer photoelectron Semiconductor device Semiconductor body Nitride layer of radiation sensitive area recess 99324.doc • 16 · 200531143 F color filter layer Ml mask M2 second mask S stacked Ti, T2 transistor V channel 99324.doc -17-