TW200529373A - A method of integrating the formation of a shallow junction n channel device with the formation of p channel, ESD and input/output devices - Google Patents

Abstract

The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition he process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.

Description

200529373 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor element ', and particularly to a method for bonding shallow-channel N-channel metal-oxide half-field-effect transistors (N channel Metal Oxide) Semiconductor (NM0S) and other types of components, integrated manufacturing method without damaging the shallow source / drain region of the N-type metal-oxide-semiconductor half field effect transistor. [Previous technology] The fabrication of several different types of components on the same semiconductor wafer can enhance performance and reduce manufacturing costs, as if it contains N-type MOSFETs and P-type MOSFETs (p channel Metal Oxide Semiconductor (PM0S) complementary metal oxide semiconductor field effect transistor (Complimentary Metal Oxide Semiconductor, CMOS) components can be completed through an integrated process step, and electrostatic-discharge (ESD) components The structure can also be implemented in this way. In this method of placing all components on the same semiconductor wafer, the connections between the components are also designed in the same semiconductor wafer, so there can be fewer external connections to reduce resistance and increase efficiency. In comparison, each component is not configured on the same semiconductor wafer, and it is necessary to add multiple external wires between the components that increase resistance. In addition, during the component manufacturing process, manufacturing costs can be reduced by sharing certain specific process steps. In order to obtain the required component characteristics for special components, such as being used in logic

Page 8 200529373 V. Description of the invention (2) N-type metal-oxide-semiconductor field-effect transistors for use in memory or memory circuits will be affected by the process steps chosen to manufacture these components. For example, an N-type metal-oxide-semiconductor field-effect transistor element used in memory applications can narrow the channel width by designing a shallow source / animated region, and the shallow source / drain region can pass low energy. The N-type dopant is implanted into the semiconductor substrate near the surface to form it. However, if other process steps for obtaining other components are performed after the source / drain region implantation procedure of the CMOS half-effect transistor, some of the foreign substances existing near the surface of the semiconductor substrate will be Destroyed or removed. Therefore, the present invention will guide a process step of manufacturing multiple components on the same semiconductor wafer, and first perform some of the specific process steps to manufacture other components before proceeding.

A source / drain region of a type 2 metal-oxide-semiconductor half field effect transistor is generated. In addition, the operating conditions of some sequences performed after the formation of the N-type f-half field effect transistor source / drain region will be changed to reduce the N-type gold ^ half-effect transistor source / drain region that has been formed. Risk of destruction or removal. Previously, technologies such as Alvis et al. In U.S. Patent No. 6,455,38 5 B1 and Doris No. 6,509,221 B1 have the ability to generate complementary gold crystal elements and source electrodes. The method of optimizing the conditions for the / drain ion implantation is described as follows: / y ± ^ ττ, 1 / It is also described in the present invention that the shallow source / drain N-type metal oxide can be photographed μ + It is a new type of pre-processing technology that integrates and manufactures transistor and other component types, such as P-type metal-oxide-semiconductor half-effect transistor, P-type & output and electrostatic discharge components. [Summary of the Invention]

200529373_ V. Description of the invention (3) ~ 'Therefore, the purpose of the present invention is that the early metal-oxygen half-field effect transistor can convert shallow source / drain · crystal elements, p-type input and output elements, such as metal oxide. Method of half field effect electricity manufacturing. The integration of cattle and electrostatic discharge elements is another object of the present invention. After the completion of the A-sequence soil sequence, #the method of making other types of components is to process the source / drain region of the transistor privately to generate N-type metal oxide. Half-field effect Another object of the present invention is that the sister _. Χ source region is implanted with one of the two metal-oxide half-field effects. Except for the dangerous method, the source 7 of the transistor is destroyed or moved. The oxygen main π is described in X. ^ East. The method of the present invention is a method for integrating shallow source / drain N-type gold% efficiency crystal crystal elements and other types of elements together. Reduced the risk of damage or removal of part of the N-type metal-oxide-semiconductor half field effect transistor / drain region. First, an electrostatic discharge device is fabricated on a semiconductor substrate first, and then a p-type input / output device is fabricated on the second part of the same semiconductor substrate. After the gate insulator layer has grown, a conductive pass-through junction (con due t i ve gat e s true ture) is formed over the gate insulation layer. When the P-type source / drain region is formed in the third part of the semiconductor substrate without the protection of the X-conducting gate structure, the fourth point of the semiconductor substrate is being subjected to a photoresist mode (ph〇t〇). resist shape). However, after the photoresist mode is formed to protect the non-N-shaped metal-oxide-semiconductor field-effect transistor region, the fourth part of the semiconductor substrate is not covered by the conductive gate structure.

Page 10 200529373 V. Description of the invention (4) ------- Place where low-energy ion source / drain region is started. Next, it will start. In order to make a shallow junction N-type transistor source / drain region is destroyed: ^ implanted N-shaped metal-oxygen half-field performs conditions such as photoresist mode removal, sidewall creation, and removal as a condition. ^ Isolation and wet cleaning process: implementation method] The process steps of integrating the shallow source / drain and other components will be described in detail here. Transistor source / drain N-type metal-oxide half field effect The transistor is in Yoshiji, and other components used in shallow manufacturing have an electrostatic discharge step-a P-type metal-oxide-semiconductor field-effect transistor element. Niu, ―You can add other species that can participate in the production together with the one-Yang I / O components. ^ You also want to make these components in the shallow source / drain region of the crystal in any case. — 圄 再 * 仃 制作 _Metal Oxide Half-Field Effect Electricity has crystal orientation characteristics < 1 〇〇 > single two J 1 = depicts a P-shaped and material 5 part 丨 used to accommodate electrostatic discharge semiconductor substrate Material 5, semiconductor-based access component, while part 3 will be used to accommodate 7 ^ 0 〇 'f f 2 used to accommodate P-type parts. In the manufacture of these other components, the type of metal-oxide-semiconductor half-field-effect transistor will be produced after the completion of the shallow source / drain N-type line. In the part 4 of the semiconductor base material 5, when an electrostatic discharge photoresist mode 6 is performed to protect the semiconductor wafer in the part 1 = when the second process is made, an opening is formed: the parts 2, 3, and 4 of the candle rdw. The photoresist mode 6 has arsenic or phosphorus ions.

200529373 V. Description of the invention (5) The exposed part of the trowel 1 is implanted to form an n-type region 7 to produce an electrostatic discharge element including an N-region on a p-type half body substrate 5. This can be seen slightly from the second figure. After the previous steps are completed, the photoresist mode 6 is removed by a plasma oxygen ashing process using CI-4 as a reactant. The next step is to make a highly doped p-type (p input / output device) on part 2 of the semiconductor wafer 5. This input / output device may be a conductive gate with a gate insulating layer and a conductive gate covering the gate insulating layer. A p-type metal-oxide-semiconductor field-effect μ-body element with a polar structure is used as an example to illustrate a highly doped p-type region such as a metal-oxide-semiconductor field-effect transistor p-type source / drain region. Before manufacturing a highly doped p-type I / O device on the part 2 of the semiconductor wafer 5, an N-well region 8 is formed on the top of the part 2 3. This is to first shield the parts 1 and 4 with a photoresist, and then Arsenic or phosphorus) ions with a concentration of about OOn to 001s atomic number per square centimeter (atonis / cm2) are implanted and formed with an energy of about 50 to 10,000 electrons. After the completion of the implantation procedure in N-well, the photoresist mode of points e and 1 will be removed and another photoresist mode 9 will be formed. Boron or boron difluoride (Βί? 2) ) Ion implantation into a semiconductor substrate to expose the exposed portion. This p-type implantation procedure will be performed at a concentration of about i 012 £ ^ 2 square centimeters and an energy number of about 50 to 10,000 electron volts. / A heavily doped p-type region i 8 is formed on the upper part of the N-well region 8, and the required heavily doped p-type input / output device is generated. This can be seen from the third step. After the previous steps are completed, the photoresist mode 9 will be removed by one to four, and (BF 4) is the oxygen plasma ashing process of the reactants. Gas Fossil Reverse The P-type and shallow source / drain N-type metal oxide are to be produced below.

200529373 V. Description of the invention (6) ^^ '-〆 The gate insulation layer and conductive gate structure required for crystals are shown in Figure 4 as a rough outline. The gate insulation layer 10 is an edge layer made of a silicon oxide material such as carbon / f, which is grown through a solder and heat in an oxygen flow (ο X yge η-steam) environment. The thickness is about 5 to 60 Angstroms (Angstroms). Next, a conductive layer such as a doped polysilicon layer is used as a material to cover the gate insulating layer 10, and the thickness is about 5,000 to 4,000 angstroms. Polycrystalline silicon layer can be added with low pressure chemical vapor deposition (LpcvD) & at the same time 'arsenide in an environment full of si lane or non-silane (di si lane) Trihydrogen (arsine) or phosphine (phosphine) is doped at the deposition site. It can also be obtained by implanting arsenic or phosphorus ions and then depositing a polycrystalline debris layer. If necessary, the conductive layer can also include a metallized layer such as tungsten silicide (tungsten si 1 pesticide) or a metal layer such as tungsten (tungsten). The next step is to form a photoresist pattern 19 as an etching mask for the anisotropic reactive ion etch process (anisotropy / reactive ion etch) to make the conductive gate structure 11. In this anisotropic reactive ion engraving process, gas (C1 is used as an etching solution for polycrystalline silicon), and the etching is selectively stopped until the upper 2 surfaces of the gate insulating layer 10 are stopped. After these steps are completed, the photoresist mode 19 will be removed by an oxygen plasma ashing process using carbon tetrafluoride as the reactant for the tritium removal process. F After removing the photoresist 19, a buffered or diluted hydrofluoric acid (hydrofluoric ) To perform the post-cleaning (p〇st_clean) procedure,

In order to dissolve the part of the gate insulation layer 10 that is not protected by the conductive gate structure, this can be seen schematically from the fourth figure. Q

200529373 V. Description of the invention (7) The next step is to make a conductive gate structure insulation gap 2 0, which can be formed on the side of the conductive gate structure before forming the metal oxide half field effect transistor source / impedance region. While done. A thickness of about 500 to 4 00 Angstroms, such as oxidized stone (si H c 〇η 〇X ide) or nitrided stone (si 1 ic η nitri de) as a material after low-pressure chemical gas The insulating layer deposited by phase deposition or plasma enhanced chemical vapor deposition (PECVD) process will pass the non- After the isotropic reactive ion etching process, the sidewall insulation gap 20 is generated on the side of the conductive gate structure because of its selective characteristics. If necessary, the semiconductor insulation gap can be 'preceded' in the semiconductor before the sidewall insulation gap 20 is produced. A lightly doped source / drain region is formed in the substrate 5 where it is not covered by the conductive gate structure 丨 1. The lightly doped source / dead region is not drawn in the illustration in this example, but its The channel length can be made narrower, and the risk of hot electron injection into the gate insulation layer can also be reduced. The side wall insulation gap 20 is located on the side of the conductive gate structure, which can be roughly seen in the fifth figure. = To be on semiconductor wafer 5 Part 3 forms the source / drain region of the p-type metal-oxide-semiconductor field-effect transistor, which can be roughly seen in the fifth figure. The first step is to form: the part ((electrostatic discharge element), Heavily doped p-type I / O elements) and photoresistive mode 12 for some 4 power source / non-effect transistor elements), the ion implantation performed here = J 疋 is to bring boron or fluorine to, electricity: and about … To the concentration of two atomic number V cm ^ 'implanted part 3 (p-type metal-oxide half field effect transistor: ri

200529373 V. Description of the invention (8) The N-well region 8 is not covered by the conductive gate structure 11 or the side wall insulation gap 20. After these steps are completed, the photoresist mode 12 is again removed through an oxygen plasma ashing process using carbon tetrafluoride as the ashing reactant. The steps thus far begin to make the shallow source / dead region of the Nl} gold-oxygen half field effect transistor element in the portion 4 on the semiconductor substrate 5. Firstly, a photoresist mode 25 is formed on the semiconductor substrate 5 except for the portion 4 so that the shallow source and the a and the pole region 14 can not be subjected to the conductive gate structure 11 or the side wall insulation gap 20 in the portion 4. The covered part is shaped. As shown in Figure 6, the shallow source and / drain regions \ 4 are via arsenic ions with an energy between about 5 to 50 仟 of electron fluorine and about 10 12 to 10 16 atoms per square centimeter. The implanted concentration. When the implantation procedure is performed under the above conditions, a shallow N-type source / drain region can be produced, but since the implanted ions are close to the surface of the semiconductor substrate 5, it will appear in the next procedure. Fragile and fragile. After the arsenic ions are implanted into the shallow source / drain region 14, the photoresist mode 25 is added through an oxygen plasma ashing process to remove it. Previously, carbon tetrafluoride was used as an important reactant in the oxygen plasma ashing process to achieve the complete removal of photoresist, but carbon tetrafluoride will cause a slight etching effect on the exposed semiconductor materials here. . However, the effect of removing the source / dead material of the shallow source / drain region on the N-type metal-oxide-semiconductor field-effect transistor element will be far greater than that of ordinary deep diffusion or source ^ and polar regions. The impact of this, so in order to reduce the risk of etching or removal in the upper part of the pole / drain region, the tetrafluoride must flow in the plasma ashing equipment during the oxygen ', plasma ashing process. Carbonization is reduced from a rate between about 50 to 70 cubic centimeters per minute (sccm) to a rate between about 50 cubic centimeters per minute. In addition, use after removing the photoresist

Page 15 200529373 V. Description of the invention (9) In the wet cleaning procedure of ammonium hydroxide-hydrogen peroxide-water, the time schedule must also be changed from about 4 to 6 Reduced between minutes to approximately 0.5 to 1.5 minutes. Such a shortened time duration of the wet cleaning procedure can once again limit the exposure time of the shallow source / drain region, so as to reduce the shallow source / drain and have been engraved or moved during the wet cleaning procedure. Divide the risk. From the above results, it can be seen that the production of shallow source / non-polar N-type metal-oxide half-effect transistor can be regarded as a part of the process steps, and components such as electrostatic discharge, input and output and P-type metal-oxide half-efficiency transistor After other components are integrated, this special private manufacturing step and shallow source / drain_metal oxide half field effect transistor shape Ϊ = the following procedure can be used to prevent process confusion and shallow source / drain two Partially removed. Therefore, the oxygen semi-electricity with the characteristics of the shallow source / non-polar region is made after the formation of other elements. Pole, and two V: its execution conditions need to be reduced to avoid the situation where the shallow source // and the pole area are partially removed. The definition: i has been used: the preferred embodiment exposes as i, but it is not intended to limit the scope; two t: those skilled in this art, without departing from the spirit and scope of the present invention: 发明 various changes and Retouching, as defined by the scope of patent application attached to Fantian of the present invention.

200529373 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the accompanying drawings for detailed description. As follows: Figures 1 to 6 are the main stages of the process steps of integrating the shallow source and / or N-type metal-oxide-semiconductor field-effect transistor elements and other elements expressed in a schematic cross-sectional view.

[Simplified description of component representative symbols] 1 Semiconductor substrate part 2 Semiconductor substrate part 3 Semiconductor substrate part 4 Semiconductor substrate part 5 Semiconductor substrate 6 Photoresistive mode 7 N-type area 8 N-well area 9 Photoresistive mode 10 Gate insulation Layer 11 conductive gate structure 12 photoresistive mode 13 source / > and electrode region 14 shallow source / drain region 18 heavily doped P-type region 19 photoresistive mode 20 sidewall spacer 25 photoresistive mode

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Claims (1)

200529373 VI. Scope of patent application 1. A method for simultaneously fabricating metal-oxide-semiconductor field-effect transistor elements and other elements on a semiconductor substrate using integrated manufacturing steps, the steps at least include: forming the other elements on the semiconductor substrate In the first part; forming a gate insulating layer of the metal-oxide-semiconductor field-effect transistor in the second part of the semiconductor substrate; forming a conductive gate structure on the gate insulating layer; forming at least one insulating gap on A side of the conductive gate structure; forming a photoresist mode on the other elements on the first portion of the semiconductor substrate, the photoresist mode exposing the second portion of the semiconductor substrate; Performing an ion implantation procedure to form a source / drain region on a portion of the second portion of the semiconductor substrate that is not covered by the conductive gate structure or the insulating spacer; performing a plasma procedure For removing the photoresist mode; and performing a wet cleaning process. 2. The method according to item 1 of the scope of patent application, wherein the other elements are selected from the group consisting of an electrostatic discharge element, an input / output element, and a complementary metal-oxide-semiconductor field-effect transistor. 3. The method according to item 1 of the scope of patent application, wherein the gate insulating layer is silicon dioxide which grows out upon thermal growth and has a thickness between 5 and 50 angstroms. Page 18, 200529373 6. The scope of patent application. 4. The method according to item 1 of the scope of patent application, wherein the thickness of the conductive gate structure is between 500 and 400 Angstroms and contains doped polycrystalline silicon. 5. The method according to item 1 of the scope of patent application, wherein the thickness of the conductive gate structure is between 500 and 2000 angstroms and contains tungsten silicide. 6. The method according to item 1 of the scope of the patent application, wherein the thickness of the insulating spacer wall is between 500 and 400 angstroms and contains silicon oxide. 7. The method according to item 1 of the scope of patent application, wherein the thickness of the insulating spacer wall is between 500 and 400 Angstroms and contains silicon nitride. 8. The method according to item 1 of the scope of patent application, wherein the ion implantation procedure for forming the source / non-electrode region is performed using arsenic ions, and the execution energy is between 5 and 50 仟 electron volts. The concentration is between 10 and 10 le atoms / cm 2. 9. The method as described in item 1 of the scope of patent applications, wherein the plasma procedure for removing the photoresist mode is an oxygen plasma ashing procedure using carbon tetrafluoride as a reactant, 'carbon tetrafluoride The flow execution rate is between 30 and 50 cubic meters per minute. n Page 19, 200529373_ VI. Patent application scope 10. The method described in item 1 of the patent application scope, wherein the wet cleaning procedure is performed using ammonium hydroxide-hydrogen peroxide synthetic water, and the execution time is 0. 5 to 1.5 minutes. 11. A shallow source / drain region of an N-channel metal-oxide-semiconductor field-effect transistor is formed on a second portion of a semiconductor substrate after at least one other element is formed on a first portion of a semiconductor substrate Method, the steps of which include at least: Forming an N-well region in the second portion of the semiconductor substrate and a third region in the first portion; forming an electrostatic discharge element in a first region in the first portion of the semiconductor substrate; forming an output Inserting a component in a second region of the first portion of the semiconductor substrate; forming a gate insulating layer in the third region of the first portion of the semiconductor substrate and the second portion of the semiconductor substrate; forming At least one conductive gate structure on the gate insulation layer; forming at least one insulating gap on a side of the conductive gate structure; A first ion implantation procedure is performed to form at least one P-type source in the third region of the first portion of the semiconductor substrate and not covered by the conductive gate structure or the insulating barrier wall A pole / drain region, so that a P-channel metal-oxide-semiconductor field-effect transistor is generated in a third region of the first portion of the semiconductor substrate; a photoresist mode is formed on the first portion of the semiconductor substrate, and the photoresist Page 20 200529373 VI. Application scope 1-2 An opening exposes the second part of the semiconductor substrate; (2) Part H The second ion implantation procedure is used to shape the part of the semiconductor substrate. 'Not covered by the conductive gate structure or the insulation gap t_shallow source / non-polar area; t ~ plasma process to remove the photoresist mode; and wet cleaning process. The marginal layer is the method described in item 11 of the scope of patent application, wherein the gate insulation layer. ···· ~ Thermal growth of silicon dioxide with a thickness between 5 and 50 angstroms 13 Gate 钤 · The method according to item 11 of the patent application scope ', wherein the conductive silicon. The thickness of the structure is between 50 and 400 Angstroms and contains doped polycrystalline 14 κ gate 钤 The method as described in item 11 of the scope of the patent application, where the thickness of the conductive structure Between 500 and 2000 angstroms and contains tungsten silicide. 15 Partition wall · The method as described in item 11 of the scope of patent application, wherein the insulation has a thickness between 500 and 400 Angstroms and contains silicon oxide. 16 hidden walls. The method described in item 11 of the scope of patent application, wherein the thickness of the insulation is between 500 and 400 Angstroms and contains silicon nitride. Page 21, 200529373_ VI. Patent application scope 1 7. The method described in item 11 of the patent application scope, wherein the second ion implantation procedure for forming the N-type source / drain region uses arsenic ions The execution energy is between 5 and 50 仟 electron volts, and the execution concentration is between 10 12 and 10 16 atoms / cm 2. 18. The method according to item 11 of the scope of patent application, wherein the plasma procedure for removing the photoresist mode is an oxygen plasma ashing procedure using carbon tetrafluoride as a reactant, tetrafluoro The flow rate of chemical carbon flow is between 30 and 50 cubic centimeters per minute. 19. The method according to item 11 of the scope of patent application, wherein the wet cleaning procedure is performed using ammonium hydroxide-hydrogen peroxide synthetic water, and the execution time range is from 0.5 to 1.5 minutes. . Page 22