TW200528995A - Peripheral controller with shared EEPROM - Google Patents

Peripheral controller with shared EEPROM Download PDF

Info

Publication number
TW200528995A
TW200528995A TW093134383A TW93134383A TW200528995A TW 200528995 A TW200528995 A TW 200528995A TW 093134383 A TW093134383 A TW 093134383A TW 93134383 A TW93134383 A TW 93134383A TW 200528995 A TW200528995 A TW 200528995A
Authority
TW
Taiwan
Prior art keywords
controller
memory
peripheral
memory device
common
Prior art date
Application number
TW093134383A
Other languages
English (en)
Chinese (zh)
Inventor
Kameran Azadet
Isaac M Livny
Anil Mudichintala
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200528995A publication Critical patent/TW200528995A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)
  • Read Only Memory (AREA)
  • Multi Processors (AREA)
  • Programmable Controllers (AREA)
TW093134383A 2003-11-25 2004-11-11 Peripheral controller with shared EEPROM TW200528995A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52523003P 2003-11-25 2003-11-25
US10/924,280 US20050114554A1 (en) 2003-11-25 2004-08-23 Peripheral controller with shared EEPROM

Publications (1)

Publication Number Publication Date
TW200528995A true TW200528995A (en) 2005-09-01

Family

ID=34468049

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093134383A TW200528995A (en) 2003-11-25 2004-11-11 Peripheral controller with shared EEPROM

Country Status (5)

Country Link
US (1) US20050114554A1 (enExample)
EP (1) EP1536342A3 (enExample)
JP (1) JP2005158074A (enExample)
KR (1) KR20050050548A (enExample)
TW (1) TW200528995A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8856401B2 (en) * 2003-11-25 2014-10-07 Lsi Corporation Universal controller for peripheral devices in a computing system
TWI391941B (zh) * 2008-03-25 2013-04-01 Genesys Logic Inc 支援開機執行之儲存裝置
US8288599B2 (en) 2008-06-30 2012-10-16 Kior, Inc. Co-processing solid biomass in a conventional petroleum refining process unit
US8558043B2 (en) * 2009-03-04 2013-10-15 Kior, Inc. Modular biomass treatment unit
EP3568451A1 (en) * 2009-05-22 2019-11-20 KiOR, Inc. Processing biomass with a hydrogen source
US8623634B2 (en) * 2009-06-23 2014-01-07 Kior, Inc. Growing aquatic biomass, and producing biomass feedstock and biocrude therefrom
CN103119573A (zh) * 2010-09-21 2013-05-22 三菱电机株式会社 Dma控制器以及数据读出装置
WO2013103872A1 (en) 2012-01-06 2013-07-11 Kior, Inc. Two-stage reactor and process for conversion of solid biomass material
US9697358B2 (en) * 2013-06-13 2017-07-04 Google Inc. Non-volatile memory operations
US9208072B2 (en) 2013-06-25 2015-12-08 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Firmware storage and maintenance
WO2016171648A1 (en) * 2015-04-20 2016-10-27 Hewlett Packard Enterprise Development Lp Configuration of configurable components

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101490A (en) * 1989-01-10 1992-03-31 Bull Hn Information Systems Inc. Peripheral device controller with an EEPROM with microinstructions for a RAM control store
US5583810A (en) * 1991-01-31 1996-12-10 Interuniversitair Micro-Elektronica Centrum Vzw Method for programming a semiconductor memory device
US5694356A (en) * 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5761516A (en) * 1996-05-03 1998-06-02 Lsi Logic Corporation Single chip multiprocessor architecture with internal task switching synchronization bus
US6119192A (en) * 1998-10-21 2000-09-12 Integrated Technology Express, Inc. Circuit and method for configuring a bus bridge using parameters from a supplemental parameter memory
US6615378B1 (en) * 1999-12-22 2003-09-02 Advanced Micro Devices, Inc. Method and apparatus for holding failing information of a memory built-in self-test
US6629158B1 (en) * 2000-02-16 2003-09-30 International Business Machines Corporation System, apparatus, and method for configuring an array controller
WO2002086751A1 (en) * 2001-04-24 2002-10-31 Broadcom Corporation Alerte standard format memory loading and handling
JP4840553B2 (ja) * 2001-07-31 2011-12-21 日本電気株式会社 無線通信機と、そのブートプログラム書き換え方法及びプログラム
US6792511B2 (en) * 2002-08-16 2004-09-14 Hewlett-Packard Development Company, L.P. Dual cache module support for array controller
DE60317816D1 (de) * 2002-10-15 2008-01-10 Socket Communications Inc Softwarekompatible parallele schnittstelle mit bidirektionalem handshaking für serielle peripherien

Also Published As

Publication number Publication date
EP1536342A3 (en) 2005-06-22
JP2005158074A (ja) 2005-06-16
US20050114554A1 (en) 2005-05-26
EP1536342A2 (en) 2005-06-01
KR20050050548A (ko) 2005-05-31

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